Cache memory system allowing concurrent reads and

专利名称：Cache memory system allowing concurrent

reads and writes to cache lines to increasesnoop bandwith

发明人：Robert Cypher申请号：US10673654申请日：20030929公开号：US06901495B2公开日：20050531

专利附图：

摘要：A cache memory includes a plurality of memory chips, or other separatelyaddressable memory sections, which are configured to collectively store a plurality of

cache lines. Each cache line includes data and an associated cache tag. The cache tag mayinclude an address tag which identifies the line as well as state information indicating thecoherency state for the line. Each cache line is stored across the memory chips in a rowformed by corresponding entries (i.e., entries accessed using the same index address).The plurality of cache lines is grouped into separate subsets based on index addresses,thereby forming several separate classes of cache lines. The cache tags associated withcache lines of different classes are stored in different memory chips. During operation,the cache controller may receive multiple snoop requests corresponding to, for example,transactions initiated by various processors. The cache controller is configured toconcurrently access the cache tags of multiple lines in response to the snoop requests ifthe lines correspond to differing classes.

申请人：Robert Cypher

地址：Saratoga CA US

国籍：US

代理机构：Meyertons Hood Kivlin Kowert & Goetzel, P.C.

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