CDB4344
Evaluation Board for CS4344
Features
zDemonstrates recommended layout and
Description
The CDB4344 evaluation board is an excellent meansfor quickly evaluating the CS4344 24-bit, 10 pin stereoD/A converter. Evaluation requires an analog signal an-alyzer, a digital signal source, and a power supply.Analog line level outputs are provided via RCA phonojacks.
The CS8416 digital audio receiver I.C. provides the sys-tem timing necessary to operate the Digital-to-Analogconverter and will accept S/PDIF, and EIAJ-340-compat-ible audio data. The evaluation board may also beconfigured to accept external timing and data signals foroperation in a user application during systemdevelopment.
ORDERING INFORMATION
CDB4344 Evaluation Board
grounding arrangements
zCS8416 receives S/PDIF, & EIAJ-340 compatible digital audio
zHeader for external PCM audio
zRequires only a digital signal source and power supplies for a complete Digital-to-Analog-Converter system
Inputs for Clocksand DataCS8416 Digital AudioInterfaceCS4344Analog Outputshttp://www.cirrus.comCopyright © Cirrus Logic, Inc. 2004
(All Rights Reserved)
June ‘04DS613DB2
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CDB4344
TABLE OF CONTENTS
1. CS4344 DIGITAL TO ANALOG CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32. CS8416 DIGITAL AUDIO RECEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33. INPUT FOR CLOCKS AND DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34. POWER SUPPLY CIRCUITRY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35. GROUNDING AND POWER SUPPLY DECOUPLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46. ANALOG OUTPUT FILTERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47. ERRATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
LIST OF FIGURES
Figure 1. System Block Diagram and Signal Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Figure 2. CS4344 and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Figure 3. CS8416 S/PDIF Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Figure 4. PCM Input Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Figure 5. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Figure 6. Silkscreen Top. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Figure 7. Top Side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Figure 8. Bottom Side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
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CDB4344
CDB4344 SYSTEM OVERVIEW
The CDB4344 evaluation board is an excellent means of quickly evaluating the CS4344. TheCS8416 digital audio interface receiver provides an easy interface to digital audio signal sourcesincluding the majority of digital audio test equipment. The evaluation board also allows the userto supply external PCM clocks and data through a header for system development.
The CDB4344 schematic has been partitioned into 4 schematics shown in Figures 2 through 5.Each partitioned schematic is represented in the system diagram shown in Figure 1. Notice thatthe system diagram also includes the interconnections between the partitioned schematics.
1.CS4344 DIGITAL TO ANALOG CONVERTER
A description of the CS4344 is included in the CS4344 datasheet.
2.CS8416 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard S/PDIF data format using a CS8416 Digital Au-dio Receiver, Figure 3. The outputs of the CS8416 include a serial bit clock, serial data, left-rightclock, and a 128/256Fs master clock. The CS8416 data format is fixed to I2S (can be changedwith R42 and R47). The operation of the CS8416 and a discussion of the digital audio interfaceis included in the CS8416 datasheet.
The evaluation board has been designed such that the input can be either optical or coax, seeFigure 3. However, both inputs cannot be driven simultaneously.
The right hand switch of S2 sets the output MCLK to LRCK ratio of the CS8416. This switchshould be set to 256 (closed) for inputs Fs<=96kHz and 128 (open) for Fs>=64kHz. The 8416must be manually reset using RX_RST (S1) when this switch is changed.
3.INPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow interfacing to external systems via the headerJ9. Header J9 allows the evaluation board to accept externally generated PCM clocks and data.The schematic for the clock/data input is shown in Figure4. The left hand switch of S2 selectsthe source as either CS8416 (closed) or header J9 (open).Please see the CS4344 datasheet for more information.
4.POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by three binding posts (GND, +5V, and ‘+3.3Vto+5V’),see Figure5. The ‘+3.3Vto+5V’ which supplies VA can be jumpered to a +3.3V regulator or the+5V binding post. The VA supply should be set to the recommended values stated in the CS4344datasheet.
WARNING: Refer to the CS4344 datasheet for maximum allowable voltages levels. Operationoutside of this range can cause permanent damage to the device.
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CDB4344
5.GROUNDING AND POWER SUPPLY DECOUPLING
As with any high performance converter, the CS4344 requires careful attention to power supplyand grounding arrangements to optimize performance. Figure 2 details the connections to theCS4344 and Figures 6, 7, and 8 show the component placement and top and bottom layout. Thedecoupling capacitors are located as close to the CS4344 as possible. Extensive use of groundplane fill in the evaluation board yields large reductions in radiated noise.
6.ANALOG OUTPUT FILTERING
The analog output on the CDB4344 has been designed according to the CS4344 datasheet. Thisoutput circuit includes an AC coupling cap and a single pole R and C. An additional load resis-tance may be added by stuffing R10 and R26 to test the CS4344’s load driving capability.
CONNECTOR
+5VGND+3.3V to +5VS/PDIF INPUT - J5S/PDIF INPUT - OPT1PCM INPUT - J9LEFT_OUT and RIGHT_OUT
INPUT/OUTPUT
InputInputInputInputInputInputOutput
+ 5V power
Ground connection from power supply
+3.3V to +5V positive supply for the CS4344 VA powerDigital audio interface input via coaxDigital audio interface input via optical
Input for master, serial, left/right clocks and serial dataRCA line level analog outputs
Table 1. System Connections
SIGNAL PRESENT
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CDB4344
JUMPER / SWITCH
J4
PURPOSE
Selects source of voltage for the CS4344 VA supplyProvides contact points to
measure current
Resets CS8416Sets clock sourceSets MCLK ratio of CS8416
leftrightPOSITIONVA+3.3V*+5V-FUNCTION SELECTED
Voltage source is the +3.3V to +5V binding post
Voltage source is a +3.3V regulatorVoltage source is +5V binding postMeasure voltage across these nodes and divide
result by 10 to get current in AmpsThe CS8416 must be reset if switch S2 is
changedSets clock source for CS4344 (open=J9, *closed
= CS8416)
Selects 128x (open) or 256x (*closed) MCLK/LRCK ratio output for CS8416
J7S1S2
Table 2. CDB4344 Jumper Settings
*Default Factory Settings.
7.ERRATA
CDB4344 Revision B.0
Switch S2 is oriented incorrectly on some boards (if open is away from binding posts) and thusthe 0 and 1 labels above and below are incorrect. Using closed for 0 and open for 1, the tablenext to the switch will be correct.
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PowerFigure 5 ResetCircuitLeft Channel Output
Figure 2 8416 DigitalAudio ReceiverFigure 3MCLKSCLKLRCKSDINCS4344Figure 2Right Channel OutputFigure 2PCM InputsFigure 4CDB4344
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Figure 1. System Block Diagram and Signal Flow元器件交易网www.cecb2b.com
CDB4344
Figure 2. CS4344 and outputsDS613DB27
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CDB4344
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Figure 3. CS8416 S/PDIF Input元器件交易网www.cecb2b.com
CDB4344
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Figure 4. PCM Input Header9
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CDB4344
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Figure 5. Power Supply Connections元器件交易网www.cecb2b.com
CDB4344
Figure 6. Silkscreen TopDS613DB211
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CDB4344
Figure 7. Top Side12DS613DB2
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CDB4344
Figure 8. Bottom SideDS613DB213
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CDB4344
REVISION HISTORY
ReleaseDB1DB2DateDEC 2003JUN 2004Changes
Initial ReleaseChanged C29 in Figure2 on page7 from 3.3 to 10 µF to improve popguard performance
Contacting Cirrus Logic SupportFor all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com
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