Freescale SemiconductorData Sheet
MCF5475ECRev. 2, 10/2004
MCF547x Integrated
Microprocessor Electrical Characteristics
Applies to the MCF5470, MCF5471, MCF5472, MCF5473, MCF5474, and MCF5475
This chapter contains electrical specification tables and reference timing diagrams for the MCF547x microprocessor. This section contains detailed
information on power considerations, DC/AC electrical characteristics, and AC timing specifications of the MCF547x.
NOTE
The parameters specifiedin this MPU documentsupersede any valuesfound in the modulespecifications.
Table of Contents
12345678910111213141516
Maximum Ratings................................................1Thermal Characteristics......................................2DC Electrical Specifications................................3Supply Voltage Sequencing and Separation
Cautions..............................................................5Output Driver Capability and Loading.................6PLL Timing Specifications...................................7Reset Timing Specifications................................8FlexBus................................................................8SDRAM Bus......................................................11PCI Bus.............................................................17Fast Ethernet AC Timing Specifications............18General Timing Specifications...........................21I2C Input/Output Timing Specifications.............21JTAG and Boundary Scan Timing.....................23DSPI Electrical Specifications...........................26Timer Module AC Timing Specifications............26
1Maximum Ratings
Table1 lists maximum and minimum ratings for supply and operating voltages and storage temperature. Operating outside of these ranges may cause erratic behavior or damage to the processor.
©Freescale Semiconductor, Inc., 2004. All rights reserved.
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Thermal Characteristics
Table1. Absolute Maximum Ratings
Rating
External (I/O pads) supply voltage (3.3-V power pins)Internal logic supply voltage
Memory (I/O pads) supply voltage (2.5-V power pins)PLL supply voltage
Internal logic supply voltage, input voltage levelStorage temperature range
SymbolEVDDIVDDSD VDDPLL VDD
VinTstg
Value–0.3 to +4.0–0.5 to +2.0
–0.3 to +4.0 SDR Memory–0.3 to +2.8 DDR Memory
–0.5 to +2.0 –0.5 to +3.6 –55 to +150
UnitsVVVVV
oC
2
2.1
Thermal Characteristics
Operating Temperatures
Table2. Operating Temperatures
Characteristic
Maximum operating junction temperatureMaximum operating ambient temperatureMinimum operating ambient temperature
SymbolTjTAmaxTAmin
Value105<701–0
Units
oTable2 lists junction and ambient operating temperatures.
C
oCoC
NOTES:
1This published maximum operating ambient temperature should be used only as a system design guideline. All device operating parameters are guaranteed only when the junction temperature lies within the specified range.
2.2Thermal Resistance
Table3. Thermal Resistance
Characteristic
SymbolθJMAθJMA
Value22–241,220–221,2
Unit°C/W°C/W
Table3 lists thermal resistance values.
324 pin TEPBGA — Junction to ambient, natural Four layer board (2s2p)convection
388 pin TEPBGA — Junction to ambient, natural Four layer board (2s2p)convection
Junction to ambient (@200 ft/min)Junction to boardJunction to case
Junction to top of package
Four layer board (2s2p)
θJMAθJBθJC
231,215310421,5°C/W°C/W°C/W°C/W
Natural convection
Ψjt
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DC Electrical Specifications
NOTES:1
θJA and Ψjt parameters are simulated in accordance with EIA/JESD Standard 51-2 for natural convection.
Freescale recommends the use of θJA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device
junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the
device junction temperature specification can be verified by physical measurement in the customer’s system using the Ψjt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.2
Per JEDEC JESD51-6 with the board horizontal.
3Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.4
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
5Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
3DC Electrical Specifications
Table4. DC Electrical Specifications
Characteristic
External (I/O pads) operation voltage range
Memory (I/O pads) operation voltage range (DDR Memory)Internal logic operation voltage range 1PLL Analog operation voltage range 1USB oscillator operation voltage rangeUSB digital logic operation voltage rangeUSB PHY operation voltage range
USB oscillator analog operation voltage rangeUSB PLL operation voltage range
Input high voltage SSTL 3.3V (SDR DRAM)Input low voltage SSTL 3.3V (SDR DRAM)Input high voltage SSTL 2.5V (DDR DRAM)Input low voltage SSTL 2.5V (DDR DRAM)Output high voltage IOH=8 mA, 16 mA,24 mAOutput low voltage IOL=8 mA, 16 mA,24 mA5Capacitance 2, Vin=0V,f=1MHz
SymbolEVDDSD VDDIVDDPLL VDDUSB_OSVDDUSBVDDUSB_PHYVDDUSB_OSCAVDDUSB_PLLVDD
VIHVILVIHVILVOHVOLCIN
Min3.02.301.431.433.03.03.01.431.432.0–0.52.0–0.52.4——
Max3.62.701.581.583.63.63.61.581.583.60.82.80.8
UnitsVVVVVVVVVVVVV
Table4 lists DC electrical operating temperatures. This table is based on an operating voltage of EVDD=3.3 VDC ± 0.3 VDC and IVDD of 1.5 ± 0.07 VDC.
— V0.5TBD
VpF
NOTES:1
IVDD and PLL VDD should be at the same voltage. PLL VDD should have a filtered input. Please see Figure1 for an example circuit. Note: There are three PLL VDD inputs. A filter circuit should used on each PLL VDD input.2Capacitance C is periodically sampled rather than 100% tested.
IN
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DC Electrical Specifications
3.1PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins. The filter shown in Figure1 should be connected between the board VDD and the PLL VDD pins. The resistor and capacitors should be placed as close to the dedicated PLL VDD pin as possible.
10 W
Board VDD
10 µF
0.1 µF
PLL VDD Pin
GND
Figure1. System PLL VDD Power Filter
3.2USB Power Filtering
To minimize noise, a external filters are required for each of the USB power pins. The filter shown in Figure2 should be connected between the board EVDD or IVDD and each of the USB VDD pins. The resistor and capacitors should be placed as close to the dedicated USB VDD pin as possible. A separate filter circuit should be included for each USB VDD pin, a total of five circuits.
R
Board EVDD/IVDD
10 µF
0.1 µF
USB VDD Pin
GND
Figure2. USB VDD Power Filter
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is alsorecommended in parallel with those shown.
Table5 lists the resistor values and supply voltages to be used in the circuit for each of the USB VDD pins.
Table5. USB Filter Circuit Values
USB VDD PinUSB_OSCVDDUSBVDDUSB_PHYVDDUSB_OSCAVDDUSB_PLLVDD
Nominal Voltage
3.3V3.3V3.3V1.5V1.5V
Resistor Value (R)
0Ω0Ω0Ω0Ω10Ω
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Supply Voltage Sequencing and Separation Cautions
4
Supply Voltage Sequencing and Separation Cautions
Figure3 shows situations in sequencing the I/O VDD (EVDD), SDRAM VDD (SD VDD), PLL VDD (PLL VDD), and Core VDD (IVDD).
DC Power Supply Voltage3.3VSupplies Stable2.5VEVDD, SD VDD (3.3V)SD VDD (2.5V)1.5V1IVDD, PLL VDD20Time
NOTES:
1.IVDD should not exceed EVDD, SD VDD or PLL VDD by more than0.4V at any time, including power-up.
2.Recommended that IVDD/PLL VDD should track EVDD/SD VDD up to0.9V, then separate for completion of ramps.
3.Input voltage must not be greater than the supply voltage (EVDD, SD VDD,IVDD, or PLL VDD) by more than 0.5V at any time, including during power-up.4.Use 1 microsecond or slower rise time for all supplies.
Figure3. Supply Voltage Sequencing and Separation Cautions
The relationship between SD VDD and EVDD is non-critical during power-up and power-down sequences. Both SD VDD (2.5V or 3.3V) and EVDD are specified relative to IVDD.
4.1Power Up Sequence
If EVDD/SD VDD are powered up with the IVDD at 0V, then the sense circuits in the I/O pads will cause all pad output drivers connected to the EVDD/SD VDD to be in a high impedance state. There is no limit on how long after EVDD/SD VDD powers up before IVDD must power up. IVDD should not lead the EVDD, SD VDD or PLL VDD by more than 0.4V during power ramp up, or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1 microsecond to avoid turning on the internal ESD protection clamp diodes.
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Output Driver Capability and Loading
The recommended power up sequence is as follows:
1.Use 1 microsecond or slower rise time for all supplies.
2.IVDD/PLL VDD and EVDD/SD VDD should track up to 0.9V, then separate for the completion of ramps with EVDD/SD VDD going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator.
4.2Power Down Sequence
If IVDDPLL VDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high impedance state. There is no limit on how long after IVDD and PLL VDD power down before EVDD or SD VDD must power down. IVDD should not lag EVDD, SD VDD, or PLL VDD going low by more than 0.4V during power down or there will be undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies.The recommended power down sequence is as follows:1.Drop IVDD/PLL VDD to 0V 2.Drop EVDD/SD VDD supplies
5Output Driver Capability and Loading
Table6. I/O Driver Capability
Signal
SDRAMC (SDADDR[12:0], SDDATA[31:0], RAS, CAS, SDDM[3:0], SDWE, SDBA[1:0]SDRAMC DQS and clocks (SDDQS[3:0], SDRDQS, SDCLK[1:0], SDCLK[1:0], SDCKE)SDRAMC chip selects (SDCS[3:0])FlexBus (AD[31:0], FBCS[5:0], ALE, R/W, BE/BWE[3:0], OE)FEC (EnMDIO, EnMDC, EnTXEN, EnTXD[3:0], EnTXERTimer (TOUT[3:0])DACK[1:0]PSC (PSCnTXD[3:0], PSCnRTS/PSCnFSYNC,
DSPI (DSPISOUT, DSPICS0/SS, DSPICS[2:3], DSPICS5/PCSS)PCI (PCIAD[31:0], PCIBG[4:1], PCIBG0/PCIREQOUT, PCIDEVSEL, PCICXBE[3:0], PCIFRM, PCIPERR, PCIRESET, PCISERR, PCISTOP, PCIPAR, PCITRDY, PCIIRDYI2C (SCL, SDA)
BDM (PSTCLK, PSTDDATA[7:0], DSO/TDO, RSTO
Drive Output CapabilityLoad (CL)24 mA24 mA24 mA16 mA8 mA8 mA8 mA8 mA24 mA16 mA
15 pF15 pF15 pF20 pF15 pF50 pF30 pF30 pF50 pF50 pF
Table6 lists values for drive capability and output loading.
8 mA8 mA8 mA
50 pF25 pF50 pF
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PLL Timing Specifications
6PLL Timing Specifications
Table7. Clock Timing Specification
NumCharacteristicC1C2C3C4
Cycle time
Rise time (20% of Vdd to 80% of vdd)Fall time (80% of Vdd to 20% of Vdd)Duty cycle (at 50% of Vdd)
Min15.15——40
Max33.32260
Unitsnsnsns%
The specifications in Table7 are for the CLKIN pin.
C1
CLKIN
C4
C4
C3
C2
Input Clock Timing Diagram
Table8 shows the supported PLL encodings.
Table8. MCF547X Divide Ratio Encodings
CLKIN—PCI and FlexBus
Clock RatioFrequency Range
(MHz)
1:21:21:4
41.6–66.6625.0–44.425.0–33.3
Internal XLB, SDRAM Bus, and PSTCLK Frequency Range
(MHz)
83.33–133.3350.0–88.8100–133.33
Core Frequency Range
(MHz)
166.66–266.66100.0–177.66200–266.66
AD[12:8]1
000110010101111
NOTES:1
All other values of AD[12:8] are reserved.
Figure4 correlates CLKIN, internal bus, and core clock frequencies for the 1x–4x multipliers.
CLKIN
Internal Clock
Core Clock
2x
25.0
66.66
4x
25.033.3325
50
70
30
50
70
100.090
110
50.0
133.33
2x
100.0
2x133.33130
60
80
100
120
140
160
180
200.0200
220
240
266.66260266.66
CLKIN (MHz)Internal Clock (MHz)Core Clock (MHz)
Figure4. CLKIN, Internal Bus, and Core Clock Ratios
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Reset Timing Specifications
7Reset Timing Specifications
Table9. Reset Timing Specification
66 MHz CLKIN
NumR1 1R2R3
Characteristic
Min
Valid to CLKIN (setup)CLKIN to invalid (hold)RSTI to invalid (hold)81.01.0
Max———
nSnSnSUnits
Table9 lists specifications for the reset timing parameters shown in Figure5
NOTES:
1RSTI and FlexBus data lines are synchronized internally. Setup and hold times must be met only if recognition on a particular clock is required.
Figure5 shows reset timing for the values in Table9.
CLKIN
R1
RSTIR2
Mode Select
FlexBus
R1
R3
NOTE:
Mode selects are registered on the rising clock edge beforethe cycle in which RSTI is recognized as being negated.Figure5. Reset Timing
8FlexBus
A multi-function external bus interface called FlexBus is provided on the MCF5472 with basic
functionality to interface to slave-only devices up to a maximum bus frequency of 66 MHz. It can be directly connected to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For
asynchronous devices, a simple chip-select based interface can be used. The FlexBus interface has six general purpose chip-selects (FBCS[5:0]). Chip-select FBCS0 can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing is compatible with common ROM / flash memories.
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FlexBus
8.1FlexBus AC Timing Characteristics
Table10. FlexBus AC Timing Specifications
Num
Frequency of Operation
FB1FB2FB3FB4FB5FB6FB7FB8FB9
Clock Period (CLKIN)
Address, Data, and Control Output Valid (AD[31:0], FBCS[5:0], R/W, ALE, TSIZ[1:0], BE/BWE[3:0], OE, and TBST)Address, Data, and Control Output Hold ((AD[31:0], FBCS[5:0], R/W, ALE, TSIZ[1:0], BE/BWE[3:0], OE, and TBST)Data Input SetupData Input Hold
Transfer Acknowledge (TA) Input SetupTransfer Acknowledge (TA) Input HoldAddress Output Valid (PCIAD[31:0])Address Output Hold (PCIAD[31:0])
Characteristic
Min3015.15—13.5040—0
Max6633.337.0—————7.0—
UnitMhznsnsnsnsnsnsnsnsns
55
The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the system clock.
Notes
1233, 4NOTES:
1The frequency of operation is the same as the PCI frequency of operation. The MCF547X supports a single external reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI.2Max cycle rate is determined by CLKIN and how the user has the system PLL configured.
3Timing for chip selects only applies to the FBCS[5:0] signals. Please see Section9.2, “DDR SDRAM AC Timing Characteristics” for SDCS[3:0] timing.4
The FlexBus supports programming an extension of the address hold. Please consult the MCF547X specification manual for more information.5
These specs are used when the PCIAD[31:0] signals are configured as 32-bit, non-muxed FlexBus address signals.
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FlexBus
CLKIN
FB1
FB3
AD[X:0]
FB2
A[X:0]
FB5
AD[31:Y]A[31:Y]DATA
R/WFB4
ALE
TSIZ[1:0]TSIZ[1:0]
FBCSn, BE/BWEnFB7
OEFB6
TAFigure6. FlexBus Read Timing
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SDRAM Bus
CLKIN
FB1
FB3
AD[X:0]
FB2
A[X:0]
FB3
AD[31:Y]A[31:Y]DATA
R/WALE
TSIZ[1:0]TSIZ[1:0]
FBCSn, BE/BWEnFB7
OEFB6
TAFigure7. FlexBus Write Timing
9SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time. The SDRAM controller uses SSTL2 and SSTL3 I/O drivers. Both SSTL drive modes are programmable for either Class I or Class II drive strength.
9.1SDR SDRAM AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the memory bus clock, when operating in SDR mode on write cycles and relative to SDR_DQS on read cycles. The MCF547x SDRAM controller is a DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must still be supplied to the MCF547x for each data beat of an SDR read. The MCF547x accomplishes this by asserting a signal called SDR_DQS during read cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the SDR_DQS signal and its usage.
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SDRAM Bus
Table11. SDR Timing Specifications
Symbol
Characteristic
Frequency of Operation
SD1SD2SD3SD4SD5SD6SD7SD8SD9SD10SD11SD12SD13
Clock Period (tCK)Clock Skew (tSK)Pulse Width High (tCKH)Pulse Width Low (tCKL)
Address, CKE, CAS, RAS, WE, BA, CS - Output Valid (tCMV)Address, CKE, CAS, RAS, WE, BA, CS - Output Hold (tCMH)SDRDQS Output Valid (tDQSOV)
SDDQS[3:0] input setup relative to SDCLK (tDQSIS)SDDQS[3:0] input hold relative to SDCLK (tDQSIH)Data Input Setup relative to SDCLK (reference only) (tDIS)Data Input Hold relative to SDCLK (reference only) (tDIH)Data and Data Mask Output Valid (tDV)
0.25×SDCLK
2.0
Selftimed0.40×SDCLK
0.450.45Min837.52
Max13312TBD0.550.550.5×SDCLK+
1.0ns
SDCLKSDCLKnsnsnsns
567834UnitMhzns
Notes
12Does not apply. 0.5 SDCLK fixed width.0.25×SDCLK
1.0
nsnsnsns
0.75×SDCLK +0.500ns
Data and Data Mask Output Hold (tDH)1.5
NOTES:
1The frequency of operation is either 2x or 4x the CLKIN frequency of operation. The MCF547X supports a single external reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI, but SDRAM clock operates at the same frequency as the internal bus clock. Please see the PLL chapter of the MCF547X Specification for more information on setting the SDRAM clock rate.2
SDCLK is one SDRAM clock in (ns).3
Pulse width high plus pulse width low cannot exceed min and max clock period.4
Pulse width high plus pulse width low cannot exceed min and max clock period.
5SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each data beat.
6SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each data beat.
7The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does not affect the memory controller.
8Since a read cycle in SDR mode still uses the DQS circuit within the MCF547X, it is most critical that the data valid window be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input setup spec is just provided as guidance.
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SDRAM Bus
SD2
SDCLK0
SD1SD3
SD2
SDCLK1
SD4
SD6
SDCSn,SDWE,
RAS, CAS
CMD
SD5
SDADDR,SDBA[1:0]
ROWCOL
SD12
SDDM
SD13
SDDATA
WD1WD2WD3WD4Figure8. SDR Write Timing
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SDRAM Bus
SD2
SDCLK0
SD1
SD2
SDCLK1
SD6
SDCSn,SDWE,
RAS, CAS
CMD
SD5
3/4 MCLKReference
ROW
COL
tDQS
SDADDR,SDBA[1:0]
SDDM
SD7
SDRQS
(Measured at Output Pin)
Board Delay
SD9
SDDQS
(Measured at Input Pin)
Board Delay
SD8
DelayedSDCLK
SD10
SDDATA
formMemories
WD1NOTE: Data driven from memories relative
to delayed memory clock.
SD11
WD2WD3WD4Figure9. SDR Read Timing
9.2DDR SDRAM AC Timing Characteristics
When using the DDR SDRAM controller, the following timing numbers must be followed to properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte lanes.Table12shows the DDR clock crossover specifications.
Table12. DDR Clock Crossover Specifications
SymbolVMPVOUTVIDVIX
Characteristic
Clock output mid-point voltageClock output voltage level
Clock output differential voltage (peak to peak swing)Clock crossing point voltage1Min1.05–0.30.7
Max1.45SD_VDD + 0.3SD_VDD + 0.6
UnitVVV
1.05 1.45 V
NOTES:
1The clock crossover voltage is only guaranteed when using the highest drive strength option for the SDCLK[1:0] and SDCLK[1:0] signals.MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2
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SDRAM Bus
SDCLK
VIXVMPVIX
SDCLKVID
Figure10. DDR Clock Timing DiagramTable13. DDR Timing Specifications
Symbol
Characteristic
Frequency of Operation
DD1DD2DD3DD4DD5DD6DD7DD8DD9DD10DD11DD12DD13DD14DD15DD16
Clock Period (tCK)Pulse Width High (tCKH)Pulse Width Low (tCKL)
Address, SDCKE, CAS, RAS, WE, SDBA, SDCS—Output Valid (tCMV)
Address, SDCKE, CAS, RAS, WE, SDBA, SDCS—Output Hold (tCMH)
Write Command to first DQS Latching Transition (tDQSS)Data and Data Mask Output Setup (DQ−>DQS) Relative to DQS (DDR Write Mode) (tQS)
Data and Data Mask Output Hold (DQS−>DQ) Relative to DQS (DDR Write Mode) (tQH)
Input Data Skew Relative to DQS (Input Setup) (tIS)Input Data Hold Relative to DQS (tIH)
DQS falling edge to SDCLK rising (output setup time) (tDSS)DQS falling edge from SDCLK rising (output hold time) (tDSH)DQS input read preamble width (tRPRE)DQS input read postamble width (tRPST)DQS output write preamble width (tWPRE)DQS output write postamble width (tWPST)
0.25×SDCLK
+0.5ns
0.50.50.90.40.250.4Min837.520.450.45—2.0—1.01.0
Max133120.550.550.5×SDCLK +1.0ns
—1.25——1———1.10.6—0.6
UnitMHznsSDCLKSDCLKnsnsSDCLKnsnsnsnsnsnsSDCLKSDCLKSDCLKSDCLK
678Notes
12345910NOTES:
1
The frequency of operation is either 2x or 4x the CLKIN frequency of operation. The MCF547X supports a single external reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI, but SDRAM clock operates at the same frequency as the internal bus clock. Please see Section2.2.6, “Reset Configuration Pins.”2SDCLK is one memory clock in (ns).3
Pulse width high plus pulse width low cannot exceed max clock period.4
Pulse width high plus pulse width low cannot exceed max clock period.
5Command output valid should be 1/2 the memory bus clock (SDCLK) plus some minor adjustments for process, temperature, and voltage variations.
6This specification relates to the required input setup time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3, SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0.7
The first data beat will be valid before the first rising edge of SDDQS and after the SDDQS write preamble. The remaining data beats will be valid for each subsequent SDDQS edge.
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SDRAM Bus
8
This specification relates to the required hold time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3, SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0. 9
Data input skew is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors).
10Data input hold is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the first data line becomes invalid.
DD1
SDCLK0
DD2
DD3
SDCLK1
SDCLK0
SDCLK1
DD5
SDCSn,SDWE,
RAS, CAS
DD4
SDADDR,SDBA[1:0]
CMD
DD6
ROWCOL
DD7
SDDM
DD8
SDDQS
DD7
SDDATA
WD1WD2WD3WD4DD8
Figure11. DDR Write Timing
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PCI Bus
DD1
SDCLK0
DD2
DD3
SDCLK1
SDCLK0
SDCLK1
DD5
SDCSn,SDWE,
RAS, CAS
DD4
SDADDR,SDBA[1:0]
CL=2
CMD
CL=2.5
ROW
COL
DQS ReadPreamble
DD10
DD9
SDDQS
DQS ReadPostamble
SDDATA
SDDQS
WD1WD2WD3WD4
DQS ReadDQS ReadPreamblePostamble
WD1WD2WD3WD4
SDDATA
Figure12. DDR Read Timing
10PCI Bus
Table14. PCI Timing Specifications
Num
Frequency of OperationP1P2P3P4P5
Clock Period (tCK)
Address, Data, and Command (33< PCI ≤ 66 Mhz)—Input Setup (tIS)Address, Data, and Command (0 < PCI ≤ 33 Mhz)—Input Setup (tIS)Address, Data, and Command (33-66 Mhz) - Output Valid (tDV)Address, Data, and Command (0 -33 Mhz) - Output Valid (tDV)
Characteristic
Min3015.153.07.0——
Max6633.33——6.011.0
UnitMHznsnsnsnsns
3The PCI bus on the MCF547x is PCI 2.2 compliant. The following timing numbers are mostly from the
PCI 2.2 spec. Please refer to the PCI 2.2 spec for a more detailed timing analysis.
Notes
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Fast Ethernet AC Timing Specifications
Table14. PCI Timing Specifications (continued)
NumP6P7P8P9P10P11P12
1
Characteristic
PCI signals (0 - 66 Mhz) - Output Hold (tDH)PCI signals (0 - 66 Mhz) - Input Hold (tIH)
PCI REQ/GNT (33 < PCI ≤ 66Mhz) - Output valid (tDV)PCI REQ/GNT (0 < PCI ≤ 33Mhz) - Output valid (tDV)PCI REQ/GNT (33 < PCI ≤ 66Mhz) - Input Setup (tIS)PCI REQ (0 < PCI ≤ 33Mhz) - Input Setup (tIS)PCI GNT (0 < PCI ≤ 33Mhz) - Input Setup (tIS)
Min00———1210
Max——6125——
Unitnsnsnsnsnsnsns
Notes
456NOTES:
Please see Section2.2.6, “Reset Configuration Pins,” for more information on setting the PCI clock rate. Also specific guidelines may need to be followed when operating the system PLL below certain frequencies.2Max cycle rate is determined by CLKIN and how the user has the system PLL configured.3
All signals defined as PCI bused signals. Does not include PTP (point-to-point) signals.
4PCI 2.2 spec does not require an output hold time. Although the MCF547X may provide a slight amount of hold, it is not required or guaranteed.
5PCI 2.2 spec requires zero input hold.
6These signals are defined at PTP (Point-to-point) in the PCI 2.2 spec.
P1
CLKIN
P4
P6
OutputValid/Hold
Output Valid
P2
InputSetup/Hold
Input Valid
P7
Figure13. PCI Timing
11Fast Ethernet AC Timing Specifications
11.1MII/7-WIRE Interface Timing Specs
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the EMAC_10_100 I/O signals.
The following timing specs meet the requirements for both MII and 7-Wire style interfaces for a range of transceiver devices. If this interface is to be used with a specific transceiver device the timing specs may be altered to match that specific transceiver.
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Fast Ethernet AC Timing Specifications
Table15. MII Receive Signal Timing
NumM1M2M3M4
Characteristic
RXD[3:0], RXDV, RXER to RXCLK setupRXCLK to RXD[3:0], RXDV, RXER holdRXCLK pulse width highRXCLK pulse width low
Min5535%35%
Max——65%65%
UnitnsnsRXCLK periodRXCLK period
M3
RXCLK (Input)
M1
RXD[3:0] (Inputs)
RXDV,RXER
M2
M4
Figure14. MII Receive Signal Timing Diagram
11.2MII Transmit Signal Timing
Table16. MII Transmit Signal Timing
NumM5M6M7M8
Characteristic
TXCLK to TXD[3:0], TXEN, TXER invalidTXCLK to TXD[3:0], TXEN, TXER validTXCLK pulse width highTXCLK pulse width low
Min0—35%35%
Max—2565%65%
UnitnsnsTXCLK periodTXCLK period
M7
TXCLK (Input)
M5
TXD[3:0] (Outputs)
TXEN,TXER
M6M8
Figure15. MII Transmit Signal Timing Diagram
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Fast Ethernet AC Timing Specifications
11.3MII Async Inputs Signal Timing (CRS, COL)
Table17. MII Transmit Signal Timing
NumM9
Characteristic
CRS, COL minimum pulse width
Min1.5
Max—
UnitTX_CLK period
CRS, COL
M9
Figure16. MII Async Inputs Timing Diagram
11.4MII Serial Management Channel Timing (MDIO,MDC)
Table18. MII Serial Management Channel Signal Timing
NumM10M11M12M13M14M15
Characteristic
MDC falling edge to MDIO output invalid (min prop delay)
MDC falling edge to MDIO output valid (max prop delay)
MDIO (input) to MDC rising edge setupMDIO (input) to MDC rising edge holdMDC pulse width highMDC pulse width low
Min0—10040%40%
Max—25——60%60%
UnitnsnsnsnsMDC periodMDC period
M14
MDC (Output)
M10
MDIO (Output)
M12
MDIO (Input)
M13
M15
M11
Figure17. MII Serial Management Channel TIming Diagram
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General Timing Specifications
12General Timing Specifications
Table19. General AC Timing Specifications
Table19 lists timing specifications for the GPIO, PSC, DREQ, DACK, and external interrupts.ameG1G2G3
Characteristic MinCLKIN high to signal output validCLKIN high to signal invalid (output hold)Signal input pulse width
—02
Max2——
UnitPSTCLKnsPSTCLK
13
I2C Input/Output Timing Specifications
Table20. I2C Input Timing Specifications between SCL and SDA
NumI1I2I3I4I5I6I7I8I9
Characteristic
Start condition hold timeClock low period
SCL/SDA rise time (VIL=0.5 V to VIH=2.4 V)Data hold time
SCL/SDA fall time (VIH=2.4 V to VIL=0.5 V)Clock high timeData setup time
Start condition setup time (for repeated start condition only)Stop condition setup time
Min28—0—4022
Max——1—1————
UnitsBus clocksBus clocks
mSnsmSBus clocks
nsBus clocksBus clocks
Table20 lists specifications for the I2C input timing parameters shown in Figure18.
Table21 lists specifications for the I2C output timing parameters shown in Figure18.
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I2C Input/Output Timing Specifications
Table21. I2C Output Timing Specifications between SCL and SDA
NumI11I2 1I3 2I4 1I5 3I6 1I7 1I8 1I9 1
Characteristic
Start condition hold timeClock low period
SCL/SDA rise time (VIL=0.5 V to VIH=2.4 V)Data hold time
SCL/SDA fall time (VIH=2.4 V to VIL=0.5 V)Clock high timeData setup time
Start condition setup time (for repeated start condition only)
Stop condition setup time
Min610—7—1022010
Max————3————
UnitsBus clocksBus clocks
µSBus clocks
nsBus clocksBus clocksBus clocksBus clocks
NOTES:1
Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR=0x20) results in minimum output timings as shown in Table21. The I2C interface is designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table21 are minimum values.
2Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up resistor values.3
Specified at a nominal 50-pF load.
Figure18 shows timing for the values in Table20 and Table21.
I2
I6
SCL
I1
I4
SDA
I7
I8
I3
I9
I5
Figure18. I2C Input/Output Timings
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JTAG and Boundary Scan Timing
14
NumJ1J2J3J4J5J6J7J8J9J10J11J12J13J14
JTAG and Boundary Scan Timing
Table22. JTAG and Boundary Scan Timing
Characteristics1
TCLK Frequency of OperationTCLK Cycle PeriodTCLK Clock Pulse WidthTCLK Rise and Fall Times
Boundary Scan Input Data Setup Time to TCLK RiseBoundary Scan Input Data Hold Time after TCLK RiseTCLK Low to Boundary Scan Output Data ValidTCLK Low to Boundary Scan Output High ZTMS, TDI Input Data Setup Time to TCLK RiseTMS, TDI Input Data Hold Time after TCLK RiseTCLK Low to TDO Data ValidTCLK Low to TDO High ZTRST Assert TimeTRST Setup Time (Negation) to TCLK HighSymbolfJCYCtJCYCtJCWtJCRFtBSDSTtBSDHTtBSDVtBSDZtTAPBSTtTAPBHTtTDODVtTDODZtTRSTATtTRSTST
MinDC215.150.05.024.00.00.05.010.00.00.0100.010.0
Max10——3.0——15.015.0——15.015.0——
UnitMHztCKnsnsnsnsnsnsnsnsnsnsnsns
NOTES:
1MTMOD is expected to be a static signal. Hence, it is not associated with any timing
J2
J3
TCLK (Input)
VIH
VIL
J4
J4J3
Figure19. Test Clock Input Timing
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JTAG and Boundary Scan Timing
TCLK
VIL
5
VIH
6
Data Inputs
7
Data Outputs
8
Data Outputs
7
Data Outputs
Input Data Valid
Output Data Valid
Output Data Valid
Figure20. Boundary Scan (JTAG) Timing
VIH
9
TDI, TMS, BKPT11
TDO
12
TDO
11
TDO
Output Data ValidOutput Data Valid
10
TCLK
VIL
Input Data Valid
Figure21. Test Access Port Timing
TCLK
14
TRST13
Figure22. TRST Timing Debug AC Timing SpecificationsMCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2
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JTAG and Boundary Scan Timing
Table23 lists specifications for the debug AC timing parameters shown in Figure24.
Table23. Debug AC Timing Specification
66 MHz
NumD1D2D3 D4 1D5
Characteristic
Min
PSTDDATA to PSTCLK setupPSTCLK to PSTDDATA holdDSI-to-DSCLK setupDSCLK-to-DSO holdDSCLK cycle time
4.54.5145
Max
nsnsPSTCLKsPSTCLKsPSTCLKsUnits
NOTES:1
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of CLKOUT.
Figure23 shows real-time trace timing for the values in Table23.
PSTCLK
D1
PSTDDATA[7:0]
D2
Figure23. Real-Time Trace AC Timing
Figure24 shows BDM serial port AC timing for the values in Table23.
D5
DSCLK
D3
DSI
Current
D4
DSO
Past
CurrentNext
Figure24. BDM Serial Port AC Timing
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DSPI Electrical Specifications
15DSPI Electrical Specifications
Table24. DSPI Modules AC Timing Specifications
Table24 lists DSPI timings.
ameDS1DS2 DS3 DS4DS5
DSPI_CS[3:0] to DSPI_CLK
Characteristic Min1 × tck—21010
Max510 × tck12———
Unitnsnsnsnsns
DSPI_CLK high to DSPI_DOUT valid.
DSPI_CLK high to DSPI_DOUT invalid. (Output hold)DSPI_DIN to DSPI_CLK (Input setup)DSPI_DIN to DSPI_CLK (Input hold)
The values in Table24 correspond to Figure25.
DSPI_CS[3:0]
DS1DSPI_CLK
DS2DSPI_DOUT
DS3DSPI_DIN
DS4DS5Figure25. DSPI Timing
16Timer Module AC Timing Specifications
Table25. Timer Module AC Timing Specifications
0–66 MHz
NameT1T2
Characteristic
Min
TIN0 / TIN1 / TIN2 / TIN3 cycle timeTIN0 / TIN1 / TIN2 / TIN3 pulse width
31
Max——
PSTCLKPSTCLKUnit
Table25 lists timer module AC timings.
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