元器件交易网www.cecb2b.com CD54HCT373, CD74HCT373OCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCLS453B – FEBRUARY 2001 – REVISED MAY 2003D4.5-V to 5.5-V VCC OperationDWide Operating Temperature Range ofDDDD–55°C to 125°CBalanced Propagation Delays andTransition TimesStandard Outputs Drive Up To 10 LS-TTLLoadsSignificant Power Reduction Compared toLS-TTL Logic ICsInputs Are TTL-Voltage CompatibleCD54HCT373...FPACKAGECD74HCT373...E OR M PACKAGE(TOP VIEW)description/ordering informationThe ’HCT373 devices are octal transparentD-type latches. When the latch-enable (LE) inputis high, the Q outputs follow the data (D) inputs.When LE is low, the Q outputs are latched at thelogic levels of the D inputs.OE1Q1D2D2Q3Q3D4D4QGND1234567891020191817161514131211VCC8Q8D7D7Q6Q6D5D5QLEA buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (highor low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus linessignificantly. The high-impedancestate and increased drive provide the capability to drive bus lines withoutinterface or pullup components.OE does not affect the internal operations of the latches. Old data can be retained or new data can be enteredwhile the outputs are in the high-impedance state.To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.ORDERING INFORMATIONTAPACKAGE†PDIP – E–5555°C to 125Cto125°CSOICMSOIC – MCDIP – FTubeTubeTape and reelTubeORDERABLEPART NUMBERCD74HCT373ECD74HCT373MCD74HCT373M96CD54HCT373F3ATOP-SIDEMARKINGCD74HCT373EHCT373MCD54HCT373F3A†Package drawings, standard packing quantities, thermal data, symbolization, and PCB designguidelines are available at www.ti.com/sc/package.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright 2003, Texas Instruments IncorporatedOn products compliant to MIL-PRF-38535, all parameters are testedunlss othrwis notd. On all othr products, productionprocessing does not necessarily include testing of all parameters.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•1元器件交易网www.cecb2b.comSCLS453B – FEBRUARY 2001 – REVISED MAY 2003CD54HCT373, CD74HCT373OCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSFUNCTION TABLE(each latch)INPUTSOELLLHLEHHLXDHLXXOUTPUTQHLQ0Z logic diagram (positive logic)OE1LE11C121D31D1QTo Seven Other Channelsabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 VInput clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mAOutput clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mAContinuous output drain current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mAContinuous output source or sink current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . ±25 mAContinuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mAPackage thermal impedance, θJA (see Note 2):E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/WM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/WStorage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTES:1.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.2.The package thermal impedance is calculated in accordance with JESD 51-7.2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com CD54HCT373, CD74HCT373OCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCLS453B – FEBRUARY 2001 – REVISED MAY 2003recommended operating conditions (see Note 3)TA = 25°CMINVCCVIHVILVIVO∆t/∆vSupply voltageHigh-level input voltageLow-level input voltageInput voltageOutput voltageInput transition rise or fall rate4.520.8VCCVCC500MAX5.5TA = –55°CTO 125°CMIN4.520.8VCCVCC500MAX5.5TA = –40°CTO 85°CMIN4.520.8VCCVCC500MAX5.5VVVVVnsUNITNOTE 3:All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERTEST CONDITIONSIOH = –20 µAIOH = –6 mAIOL = 20 µAIOL = 6 mAVCCTA = 25°CMINVOHVOLIIIOZICC∆ICC‡CiCoVI = V=VIH or VorVILVI = V=VIH or VorVILVI = VCC or 0VO = VCC or 0VI = VCC or 0,IO = 045V4.5 V45V4.5 V5.5 V5.5 V5.5 V4.5 V to5.5 V4.43.980.10.26±0.1±0.583601010MAXTA = –55°CTO 125°CMIN4.43.70.10.4±1±101604901010MAXTA = –40°CTO 85°CMIN4.43.840.10.33±1±5804501010MAXVVµAµAµAµApFpFUNITOne input at VCC – 2.1 V, Other inputs at 0 or VCC‡Additional quiescent supply current per input pin, TTL inputs high, 1 unit load. For dual-supply systems, theoretical worst-case(VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA.HCT INPUT LOADING TABLEINPUTOEAny DLEUNIT LOAD1.50.41Unit load is ∆ICC limitspecified in electricalcharacteristics table (e.g.,360 µA max at 25°C).POST OFFICE BOX 655303 DALLAS, TEXAS 75265•3元器件交易网www.cecb2b.comSCLS453B – FEBRUARY 2001 – REVISED MAY 2003CD54HCT373, CD74HCT373OCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTS timing requirements over recommended operating free-air temperature range, VCC = 4.5 V (unlessotherwise noted) (see Figure 1)TA = 25°CMINtwtsuthPulse duration, LE highSetup time, data before LE↓Hold time, data after LE↓161310MAXTA = –55°CTO 125°CMIN242015MAXTA = –40°CTO 85°CMIN201613MAXnsnsnsUNITswitching characteristics over recommended operating free-air temperature range, VCC = 4.5 V(unless otherwise noted) (see Figure 1)PARAMETERFROM(INPUT)DLEOEOETO(OUTPUT)QQQQLOADCAPACITANCECL = 50 pF=50pFCL = 50 pFCL = 50 pFCL = 50 pFTA = 25°CMINMAX3235353512TA = –55°CTO 125°CMINMAX4853535318TA = –40°CTO 85°CMINMAX4044444415nsnsnsnsUNITtpddtentdisttoperating characteristics, VCC = 5 V, TA = 25°CPARAMETERCpdPower dissipation capacitanceTYP53UNITpF4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com CD54HCT373, CD74HCT373OCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCLS453B – FEBRUARY 2001 – REVISED MAY 2003PARAMETER MEASUREMENT INFORMATIONVCCS11 kΩtdisS2tpd or ttLOAD CIRCUITInput1.3 VVOLTAGE WAVEFORMSPULSE DURATION3 V1.3 V0 Vtrec3 VCLK1.3 V0 VVOLTAGE WAVEFORMSRECOVERY TIME3 VInput1.3 VtPLHIn-PhaseOutput1.3 V10%tPHLOut-of-PhaseOutput90%90%tr1.3 V10%tf1.3 V0 VtPHL90%1.3 V10%tfVOHVOLOutputWaveform 1(see Note B)tPZHOutputWaveform 2(see Note B)1.3 VOutputControltPZL1.3 V1.3 V1.3 V0 VtPLZ≈VCC10%tPHZ90%VOH≈0 VVOLData1.3 VInput0.3 VReferenceInputtsu2.7 Vtr3 V1.3 V0 Vth2.7 V3 V1.3 V0.3 V0 VtfPARAMETERtentPZHtPZLtPHZtPLZS1OpenClosedOpenClosedOpentw3 V1.3 V0 VS2ClosedOpenClosedOpenOpenFrom OutputUnder TestCL(see Note A)TestPointCLRInputVOLTAGE WAVEFORMSSETUP AND HOLD AND INPUT RISE AND FALL TIMES3 VtPLH1.3 V10%V90%OHtrVOLVOLTAGE WAVEFORMSPROPAGATION DELAY AND OUTPUT TRANSITION TIMESVOLTAGE WAVEFORMSOUTPUT ENABLE AND DISABLE TIMESNOTES:A.CL includes probe and test-fixture capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.C.Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the followingcharacteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.D.For clock inputs, fmax is measured with the input duty cycle at 50%.E.The outputs are measured one at a time with one input transition per measurement.F.tPLZ and tPHZ are the same as tdis.G.tPZL and tPZH are the same as ten.H.tPLH and tPHL are the same as tpd.Figure 1. Load Circuit and Voltage WaveformsPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•5元器件交易网www.cecb2b.com
PACKAGEOPTIONADDENDUM
www.ti.com
30-Mar-2005
PACKAGINGINFORMATION
OrderableDeviceCD54HCT373FCD54HCT373F3ACD74HCT373ECD74HCT373MCD74HCT373M96
(1)
Status(1)ACTIVEACTIVEACTIVEACTIVEACTIVE
PackageTypeCDIPCDIPPDIPSOICSOIC
PackageDrawing
JJNDWDW
PinsPackageEcoPlan(2)
Qty2020202020
1120252000
TBDTBDPb-Free(RoHS)Pb-Free(RoHS)Pb-Free(RoHS)
Lead/BallFinish
CallTICallTICUNIPDAUCUNIPDAUCUNIPDAU
MSLPeakTemp(3)Level-NC-NC-NCLevel-NC-NC-NCLevel-NC-NC-NCLevel-2-250C-1YEAR/Level-1-235C-UNLIMLevel-2-250C-1YEAR/Level-1-235C-UNLIM
Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)
EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS)orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)
(3)
MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
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Addendum-Page1
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