M25P16-VMC6TG

Features

Micron M25P16 Serial Flash EmbeddedMemory

16Mb, 3VFeatures

••••••

SPI bus compatible serial interface16Mb Flash memory

75 MHz clock frequency (maximum)2.7V to 3.6V single supply voltage

Page program (up to 256 bytes) in 0.64ms (TYP)Erase capability

–Sector erase: 512Kb in 0.6 s (TYP)–Bulk erase: 16Mb in 13 s (TYP)•Write protection

–Hardware write protection: protected area sizedefined by non-volatile bits BP0, BP1, BP2•Deep power down: 1µA (TYP)

•Electronic signature

–JEDEC standard 2-byte signature (2015h)

–Unique ID code (UID) and 16 bytes of read-onlydata, available upon customer request

–RES command, one-byte signature (14h) forbackward compatibility

•More than 100,000 write cycles per sector•More than 20 years data retention•Automotive grade parts available•Packages (RoHS compliant)–SO8N (MN) 150 mils–SO8W (MW) 208 mils–SO16 (MF) 300 mils

–VFDFPN8 (MP) MLP8 6mm x 5mm–VFDFPN8 (ME) MLP8 8mm x 6mm–UFDFPN8 (MC) MLP8 4mm x 3mm

PDF: 09005aef8456656cm25p16.pdf - Rev. J 1/18 EN1

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2011 Micron Technology, Inc. All rights reserved.

Micron M25P16 Serial Flash Embedded Memory

SPI Modes

SPI Modes

These devices can be driven by a microcontroller with its serial peripheral interface(SPI) running in either of the following two SPI modes:•CPOL = 0, CPHA = 0•CPOL = 1, CPHA = 1

For these two modes, input data is latched in on the rising edge of serial clock (C), andoutput data is available from the falling edge of C.

The difference between the two modes is the clock polarity when the bus master is instandby mode and not transferring data:•C remains at 0 for (CPOL = 0, CPHA = 0)•C remains at 1 for (CPOL = 1, CPHA = 1)

Figure 4: SPI Modes Supported

CPOL

CPHA

00C

11C

DQ0MSB

DQ1

MSB

Because only one device is selected at a time, only one device drives the serial data out-put (DQ1) line at a time, while the other devices are High-Z. An example of three devi-ces connected to an MCU on an SPI bus is shown here.

PDF: 09005aef8456656cm25p16.pdf - Rev. J 1/18 EN10Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2011 Micron Technology, Inc. All rights reserved.

Micron M25P16 Serial Flash Embedded Memory

SPI Modes

Figure 5: Bus Master and Memory Devices on the SPI Bus

VSSVCCRSDOSPI interface with(CPOL, CPHA) =(0, 0) or (1, 1)SDISCKCSPI Bus MasterDQ1DQ0VCCVSSCDQ1DQ0VCCVSSCDQ1DQ0VCCVSSRCS3CS2CS1S#SPI memorydeviceRSPI memorydeviceRSPI memorydeviceW#HOLD#S#W#HOLD#S#W#HOLD#Notes:

1.WRITE PROTECT (W#) and HOLD# should be driven HIGH or LOW as appropriate.

2.Resistors (R) ensure that the memory device is not selected if the bus master leaves the

S# line High-Z.

3.The bus master may enter a state where all I/O are High-Z at the same time; for exam-ple, when the bus master is reset. Therefore, C must be connected to an external pull-down resistor so that when all I/O are High-Z, S# is pulled HIGH while C is pulled LOW.This ensures that S# and C do not go HIGH at the same time and that the tSHCH require-ment is met.

4.The typical value of R is 100kΩ, assuming that the time constant R × Cp (Cp = parasitic

capacitance of the bus line) is shorter than the time during which the bus master leavesthe SPI bus High-Z.

5.Example: Given that Cp = 50pF (R × Cp = 5μs), the application must ensure that the bus

master never leaves the SPI bus High-Z for a time period shorter than 5μs.

PDF: 09005aef8456656cm25p16.pdf - Rev. J 1/18 EN11Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2011 Micron Technology, Inc. All rights reserved.