www.fairchildsemi.com
FM24C04U/05U Rev. A.3
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROMConnection DiagramsDual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)NC18VCCA127NC24C04A236SCLVSS45SDASee Package Number N08E, M08A and MTC08Pin NamesA1,A2Device Address InputsVSSGroundSDASerial Data I/OSCLSerial Clock InputNCNo ConnectionVCCPower SupplyDual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)NC18VCCA127WP24C05A236SCLVSS45SDASee Package Number N08E, M08A and MTC08Pin NamesA1,A2Device Address InputsVSSGroundSDASerial Data I/OSCLSerial Clock inputWPWrite ProtectVCCPower SupplyNCNo Connection2
www.fairchildsemi.com
FM24C04U/05U Rev. A.3
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROMOrdering InformationFM24CXXUFLZEXXXLetter
Description
Package
N8-pin DIPM88-pin SOICMT88-pin TSSOPTemp. Range
Blank0 to 70°C
V-40 to +125°CE-40 to +85°C
Voltage Operating Range
Blank4.5V to 5.5VL2.7V to 5.5VLZ
2.7V to 5.5V and
<1µA Standby CurrentSCL Clock Frequency
Blank100KHzF400KHz
ProcessUUltralite CS100ULDensity
044K
054K with Write ProtectC
CMOS TechnologyInterface24IIC
FM
Fairchild Non-VolatileMemory
3
www.fairchildsemi.com
FM24C04U/05U Rev. A.3
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROMProduct SpecificationsAbsolute Maximum RatingsOperating ConditionsAmbient Storage Temperature–65°C to +150°CAmbient Operating TemperatureAll Input or Output VoltagesFM24C04U/05U0°C to +70°Cwith Respect to Ground –0.3V to 6.5VFM24C04UE/05UE-40°C to +85°CLead TemperatureFM24C04UV/05UV-40°C to +125°C(Soldering, 10 seconds)+300°CPositive Power SupplyESD Rating2000V min.FM24C04U/05U4.5V to 5.5VFM24C04UL/05UL2.7V to 5.5VFM24C04ULZ/05ULZ2.7V to 5.5VDC Electrical Characteristics (2.7V to 5.5V)SymbolParameterTest ConditionsLimitsUnitsMinTypMax(Note 1)ICCAActive Power Supply CurrentfSCL = 400 KHz (\"F\" version)0.21.0mAfSCL = 100 KHzISBStandby CurrentVIN = GNDVCC = 2.7V - 5.5V1050µA(Note 3)or VCCVCC = 2.7V - 5.5V (L)110µAVCC = 2.7V - 4.5V (LZ)0.11µAILIInput Leakage CurrentVIN = GND to VCC0.11µAILOOutput Leakage CurrentVOUT = GND to VCC0.11µAVILInput Low Voltage–0.3VCC x 0.3VVIHInput High VoltageVCC x 0.7VCC + 0.5VVOLOutput Low VoltageIOL = 3 mA0.4VCapacitance TA = +25°C, f = 100/400 KHz, VCC = 5V (Note 2)SymbolTestConditionsMaxUnitsCI/OInput/Output Capacitance (SDA)VI/O = 0V8pFCINInput Capacitance (A0, A1, A2, SCL)VIN = 0V6pFNote 1:Typical values are TA = 25°C and nominal supply voltage of 5V for 4.5V-5.5V operation and at 3V for 2.7V-4.5V operation.Note 2:This parameter is periodically sampled and not 100% tested.Note 3:The \"L\" and \"LZ\" versions can be operated in the 2.7V to 5.5V VCC range. However, for a standby current (ISB) of 1µA, the VCC should be within 2.7V to 4.5V.4
www.fairchildsemi.com
FM24C04U/05U Rev. A.3
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROMAC Test ConditionsAC Testing Input/Output WaveformsInput Pulse LevelsVCC x 0.1 to VCC x 0.90.9VCC0.7VCCInput Rise and Fall Times10 ns0.1VCC0.3VCCInput & Output Timing LevelsVCC x 0.3 to VCC x 0.7Output Load1 TTL Gate and CL = 100 pFRead and Write Cycle Limits (Standard and Low VCC Range 2.7V - 5.5V)SymbolParameter100 KHz400 KHzUnitsMinMaxMinMaxfSCLSCL Clock Frequency100400KHzTINoise Suppression Time Constant atSCL, SDA Inputs (Minimum VIN10050nsPulse width)tAASCL Low to SDA Data Out Valid0.33.50.10.9µstBUFTime the Bus Must Be Free before4.71.3µsa New Transmission Can StarttHD:STAStart Condition Hold Time4.00.6µstLOWClock Low Period4.71.5µstHIGHClock High Period4.00.6µstSU:STAStart Condition Setup Time4.70.6µs(for a Repeated Start Condition)tHD:DATData in Hold Time00nstSU:DATData in Setup Time250100nstRSDA and SCL Rise Time10.3µstFSDA and SCL Fall Time300300nstSU:STOStop Condition Setup Time4.70.6µstDHData Out Hold Time30050nstWRWrite Cycle Time(Note 4)4.5V to 5.5V VCC1010ms2.7V to 4.5V VCC1515Note 4:The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, theFM24C04U/05U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer\"Write Cycle Timing\" diagram.Bus TimingtFtRtHIGHtLOWtLOWSCLtSU:STAtttHD:DATtSU:DATSU:STOSDAHD:STAINtBUFtAAtDHSDAOUT5
www.fairchildsemi.com
FM24C04U/05U Rev. A.3
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROMWrite Cycle TimingSCLSDA8th BITACKWORD ntWRSTOPSTARTCONDITIONCONDITIONNote:The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.Typical System ConfigurationVCCVCCSDASCLMasterSlaveMasterTransmitter/SlaveReceiverReceiverTransmitter/MasterReceiverTransmitterTransmitter/ReceiverNote:Due to open drain configuration of SDA and SCL, a bus-level pull-up resistor is called for, (typical value = 4.7kΩ)Example of 16K of Memory on 2-Wire BusNote:The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices.The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state.It is recommended that the total line capacitance be less than 400pFVCCVCCSDASCLVCCVCCVCCVCC24C02/0324C02/0324C04/0524C08/09A0 A1 A2 VSSA0 A1 A2 VSS A1 A2 VSS A2 VSSTo To To To To To To To To VSSVSSVSSVCCVSSVSSVCCVSSVCCDeviceAddress Pins PresentMemory Size# of PageA0A1A2BlocksFM24C02U/03UYesYesYes2048 Bits1FM24C04U/05UNoYesYes4096 Bits2FM24C08U/09UNoNoYes8192 Bits4FM24C16U/17UNoNoNo16,384 Bits86
www.fairchildsemi.com
FM24C04U/05U Rev. A.3
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROMBackground Information (IIC Bus)AcknowledgeIIC bus allows synchronous bi-directional communication be-Acknowledge is an active LOW pulse on the SDA line driven by antween a TRANSMITTER and a RECEIVER using a Clock signaladdressed receiver to the addressing transmitter to indicate(SCL) and a Data signal (SDA). Additionally there are up to threereceipt of 8-bits of data. The receiver provides an ACK pulse forAddress signals (A2, A1 and A0) which collectively serve as \"chipevery 8-bits of data received. This handshake mechanism is doneselect signal\" to a device (example EEPROM) on the IIC bus.as follows: After transmitting 8-bits of data, the transmitter re-All communication on the IIC bus must be started with a validleases the SDA line and waits for the ACK pulse. The addressedSTART condition (by a MASTER), followed by transmittal (by thereceiver, if present, drives the ACK pulse on the SDA line duringMASTER) of byte(s) of information (Address/Data). For every bytethe 9th clock and releases the SDA line back (to the transmitter).of information received, the addressed RECEIVER provides a validRefer Figure 3.ACKNOWLEDGE pulse to further continue the communicationArray Addressunless the RECEIVER intends to discontinue the communication.Depending on the direction of transfer (Write or Read), the RE-Array address is an 8-bit information containing the address of aCEIVER can be a SLAVE or the MASTER. A typical IIC communi-memory location to be selected within a page block of the device.cation concludes with a STOP condition (by the MASTER).16K bit Addressing Limitation:Addressing an EEPROM memory location involves sending aStandard IIC specification limits the maximum size of EEPROMcommand string with the following information:memory on the bus to 16K bits. This limitation is due to the[DEVICE TYPE]—[DEVICE/PAGE BLOCK SELECTION]—[R/Waddressing protocol implemented which consists of the 8-bit SlaveBIT]—{acknowledge pulse}—[ARRAY ADDRESS]Address and an additional 8-bit field called Array Address. ThisArray Address selects 1 out of 256 locations (28=256). Since theSlave Addressdata format of IIC specification is 8-bit wide, a total of 256 x 8 =2048 = 2K bits now becomes addressable by this 8-bit ArraySlave Address is an 8-bit information consisting of a Device typeAddress. These 2K bits are typically referred as a “Page Block”.field (4bits), Device/Page block selection field (3bits) and Read/Combining this 8-bit Array Address with the 3-bit Device/PageWrite bit (1bit).address (part of Slave Address) allows a maximum of 8 pagesSlave Address Format(23=8) of memory that can be addressed. Since each page is 2Kbits in size, 8 x 2K bits = 16K bits is the maximum size of memoryDevice TypeDevice/Page Block that is addressable on the Standard IIC bus. This 16Kb of memoryIdentifierSelectioncan be in the form of a single 16Kb EEPROM device or multipleEEPROMs of varying density (in 2Kb multiples) to a maximumtotal of 16Kb. To address the needs of systems that require more1010A2A1A0R/W(LSB)than 16Kb on the IIC bus, a different specification called “Ex-tended IIC Specification” is used.Device TypeDEFINITIONSIIC bus is designed to support a variety of devices such as RAMs,WORD8 bits (byte) of dataEPROMs etc., along with EEPROMS. Hence to properly identifyvarious devices on the IIC bus, a 4-bit “Device Type” identifierPAGE16 sequential byte locationsstring is used. For EEPROMS, this 4-bit string is 1-0-1-0. Every IICstarting at a 16-byte addressdevice on the bus internally compares this 4-bit string to its ownboundary, that may be pro-“Device Type” string to ensure proper device selection.grammed during a \"page write\"programming cycleDevice/Page Block SelectionPAGE BLOCK2048 (2K) bits organized into 16When multiple devices of the same type (e.g. multiple EEPROMS)pages of addressable memory. (8are present on the IIC bus, then the A2, A1 and A0 addressbits) x (16 bytes) x (16 pages) =information bits are also used as part of the Slave Address. Every2048 bitsIIC device on the bus internally compares this 3-bit string to its ownphysical configuration (A2, A1 and A0 pins) to ensure properMASTERAny IIC device CONTROLLING thedevice selection. This comparison is in addition to the “Devicetransfer of data (such as aType” comparison. In addition to selecting an EEPROM, these 3microprocessor)bits are also used to select a “page block” within the selectedSLAVEDevice being controlledEEPROM. Each page block is 2Kbit (256Bytes) in size. Depend-(EEPROMs are always considereding on the density, an EEPROM can contain from a minimum of 1Slaves)to a maximum of 8 page blocks (in multiples of 2) and selection ofa page block within a device is by using A2, A1 and A0 bits.TRANSMITTERDevice currently SENDING data onthe bus (may be either a Master orRead/Write BitSlave).Last bit of the Slave Address indicates if the intended access isRECEIVERDevice currently RECEIVING dataRead or Write. If the bit is \"1,\" then the access is Read, whereason the bus (Master or Slave)if the bit is \"0,\" then the access is Write.7
www.fairchildsemi.com
FM24C04U/05U Rev. A.3
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROMPin DescriptionsDevice OperationSerial Clock (SCL)The FM24C04U/05U supports a bi-directional bus oriented proto-The SCL input is used to clock all data into and out of the device.col. The protocol defines any device that sends data onto the busas a transmitter and the receiving device as the receiver. TheSerial Data (SDA)device controlling the transfer is the master and the device that iscontrolled is the slave. The master will always initiate dataSDA is a bi-directional pin used to transfer data into and out of thetransfers and provide the clock for both transmit and receivedevice. It is an open drain output and may be wire–ORed with anyoperations. Therefore, the FM24C04U/05U will be considered anumber of open drain or open collector outputs.slave in all applications.Write Protect (WP) (FM24C05U Only)Clock and Data ConventionsIf tied to VData states on the SDA line can change only during SCL LOW.2Kbits) of the memory will not be executed. READ operations areCC, PROGRAM operations onto the upper half (upperSDA state changes during SCL HIGH are reserved for indicatingpossible. If tied to VSS, normal operation is enabled, READ/start and stop conditions. Refer to Figure 1 and Figure 2 on nextWRITE over the entire memory is possible.page.This feature allows the user to assign the upper half of the memoryStart Conditionas ROM which can be protected against accidental programming.When write is disabled, slave address and word address will beAll commands are preceded by the start condition, which is aacknowledged but data will not be acknowledged.HIGH to LOW transition of SDA when SCL is HIGH. TheFM24C04U/05U continuously monitors the SDA and SCL lines forThis pin has an internal pull-down circuit. However, on systemsthe start condition and will not respond to any command until thiswhere write protection is not required it is recommended that thiscondition has been met.pin is tied to VSS.Stop ConditionDevice Selection Inputs A2, A1 and A0 (asAll communications are terminated by a stop condition, which is aappropriate)LOW to HIGH transition of SDA when SCL is HIGH. The stopThese inputs collectively serve as “chip select” signal to ancondition is also used by the FM24C04U/05U to place the deviceEEPROM when multiple EEPROMs are present on the same IICin the standby power mode, except when a Write operation isbus. Hence these inputs, if present, should be connected to Vbeing executed, in which case a second stop condition is requiredCCor Vafter tSS in a unique manner to allow proper selection of an EEPROMWR period, to place the device in standby mode.amongst multiple EEPROMs. During a typical addressing se-quence, every EEPROM on the IIC bus compares the configura-tion of these inputs to the respective 3 bit “Device/Page blockselection” information (part of slave address) to determine a validselection. For e.g. if the 3 bit “Device/Page block selection” is 1-0-1, then the EEPROM whose “Device Selection inputs” (A2, A1and A0) are connected to VCC-VSS-VCC respectively, is selected.Depending on the density, only appropriate numbers of “DeviceSelection inputs” are provided on an EEPROM. For every “Deviceselection input” that is not present on the device, the correspond-ing bit in the “Device/Page block selection” field is used to selecta “Page Block” within the device instead of the device itself.Following table illustrates the above:EEPROMNumber ofDevice Selection InputsAddress BitsDensityPage BlocksProvidedSelecting Page Block2k bit1A0A1A2None4k bit2—A1A2A08k bit4——A2A0 and A116k bit8———A0, A1 and A2Note that even when just one EEPROM present on the IIC bus,these pins should be tied to VCC or VSS to ensure proper termina-tion.8
www.fairchildsemi.com
FM24C04U/05U Rev. A.3
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROMData Validity (Figure 1)SCLSDADATA STABLEDATA CHANGEStart and Stop Definition (Figure 2)SCLSDASTART STOP CONDITIONCONDITIONAcknowledge Response from Receiver (Figure 3)SCL FROMMASTER189DATA OUTPUTFROMTRANSMITTERtDHDATA OUTPUTtAAFROMRECEIVERSTARTACKNOWLEDGECONDITIONPULSE9
www.fairchildsemi.com
FM24C04U/05U Rev. A.3
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROMAcknowledgeRefer the following table for Slave Addresses string details:The FM24C04U/05U device will always respond with an acknowl-edge after recognition of a start condition and its slave address. IfDeviceA0A1A2PagePage Blockboth the device and a write operation have been selected, theBlocksAddressesFM24C04U/05U will respond with an acknowledge after theFM24C04U/05UPAA20, 1receipt of each subsequent eight bit byte.A:Refers to a hardware configured Device Address pin.In the read mode the FM24C04U/05U slave will transmit eight bitsP:Refers to an internal PAGE BLOCK.of data, release the SDA line and monitor the line for an acknowl-edge. If an acknowledge is detected, FM24C04U/05U will continueAll IIC EEPROMs use an internal protocol that defines a PAGEto transmit data. If an acknowledge is not detected,FM24C04U/05UBLOCK size of 2K bits (for Word addresses 0x00 through 0xFF).will terminate further data transmissions and await the stop condi-Therefore, address bits A0, A1, or A2 (if designated 'P') are usedtion to return to the standby power mode.to access a PAGE BLOCK in conjunction with the Word addressused to access any individual data byte.Device AddressingThe last bit of the slave address defines whether a write or readFollowing a start condition the master must output the address ofcondition is requested by the master. A '1' indicates that a readthe slave it is accessing. The most significant four bits of the slaveoperation is to be executed, and a '0' initiates the write mode.address are those of the device type identifier. This is fixed as1010 for all EEPROM devices.A simple review: After the FM24C04U/05U recognizes the startcondition, the devices interfaced to the IIC bus wait for a slaveDevice TypeDevice address to be transmitted over the SDA line. If the transmittedIdentifierAddressslave address matches an address of one of the devices, thedesignated slave pulls the SDA line LOW with an acknowledgesignal and awaits further transmissions.1010A2A1A0R/W(LSB)24C04/05PageBlock Address10
www.fairchildsemi.com
FM24C04U/05U Rev. A.3
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROMWrite OperationsBYTE WRITEPage Write is initiated in the same manner as the Byte Writeoperation; but instead of terminating the cycle after transmittingFor a write operation, a second address field is required which is athe first data byte, the master can further transmit up to 15 moreword address that is comprised of eight bits and provides access tobytes. After the receipt of each byte, FM24C04U/05U will respondany one of the 256 bytes in the selected page of memory. Uponwith an acknowledge pulse, increment the internal address counterreceipt of the byte address, the FM24C04U/05U responds with anto the next address, and is ready to accept the next data. If theacknowledge and waits for the next eight bits of data, again,master should transmit more than sixteen bytes prior to generat-responding with an acknowledge. The master then terminates theing the STOP condition, the address counter will “roll over” andtransfer by generating a stop condition at which time the FM24C04U/previously written data will be overwritten. As with the Byte Write05U begins the internal write cycle to the nonvolatile memory. Whileoperation, all inputs are disabled until completion of the internalthe internal write cycle is in progress, the FM24C04U/05U inputswrite cycle. Refer to Figure 5 for the address, acknowledge, andare disabled, and the device will not respond to any requests fromdata transfer sequence.the master for the duration of tWR. Refer to Figure 4 for the address,acknowledge, and data transfer sequence.Acknowledge PollingPAGE WRITEOnce the stop condition is issued to indicate the end of the host’swrite operation, the FM24C04U/05U initiates the internal writeTo minimize write cycle time, FM24C04U/05U offer Page Writecycle. ACK polling can be initiated immediately. This involvesfeature, by which, up to a maximum of 16 contiguous byteissuing the start condition followed by the slave address for a writelocations can be programmed all at once (instead of 16 individualoperation. If the FM24C04U/05U is still busy with the writebyte writes). To facilitate this feature, the memory array is orga-operation no ACK will be returned. If the FM24C04U/05U hasnized in terms of “Pages.” A Page consists of 16 contiguous bytecompleted the write operation, an ACK will be returned and thelocations starting at every 16-Byte address boundary (for ex-host can then proceed with the next read or write operation.ample, starting at array address 0x00, 0x10, 0x20 etc.). PageWrite operation limits access to byte locations within a page. InWrite Protection (FM24C05U Only)other words a single Page Write operation will not cross over tolocations on another page but will “roll over” to the beginning of theProgramming of the upper half (upper 2Kbit) of the memory will notpage whenever end of Page is reached and additional locationstake place if the WP pin of the FM24C05U is connected to Vare continued to be accessed. A Page Write operation can beThe FM24C05U will respond to slave and byte addresses; but ifCC.initiated to begin at any location within a page (starting address ofthe memory accessed is write protected by the WP pin, thethe Page Write operation need not be the starting address of aFM24C05U will not generate an acknowledge after the first bytePage).of data has been received. Thus, the program cycle will not bestarted when the stop condition is asserted.Byte Write (Figure 4)STSBus Activity:ASLAVEWORDTMasterRADDRESSADDRESSDATAOTPSDA LineAAABus Activity:CCCEEPROMKKKPage Write (Figure 5)STSBus Activity:ASLAVETMasterRADDRESSWORD ADDRESS (n)DATA nDATA n + 1DATA n + 15OTPSDA LineAAAAABus Activity:CCCCCEEPROMKKKKK11
www.fairchildsemi.com
FM24C04U/05U Rev. A.3
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROMRead Operationsimmediately issues another start condition and the slave addresswith the R/W bit set to one. This will be followed by an acknowl-Read operations are initiated in the same manner as writeedge from the FM24C04U/05U and then by the eight bit word. Theoperations, with the exception that the R/W bit of the slavemaster will not acknowledge the transfer but does generate theaddress is set to a one. There are three basic read operations:stop condition, and therefore the FM24C04U/05U discontinuescurrent address read, random read, and sequential read.transmission. Refer to Figure 7 for the address, acknowledge, andCurrent Address Readdata transfer sequence.Internally the FM24C04U/05U contains an address counter thatSequential Readmaintains the address of the last byte accessed, incremented bySequential reads can be initiated as either a current address readone. Therefore, if the last access (either a read or write) was toor random access read. The first word is transmitted in the sameaddress n, the next read operation would access data frommanner as the other read modes; however, the master nowaddress n + 1. Upon receipt of the slave address with R/W set toresponds with an acknowledge, indicating it requires additionalone, the FM24C04U/05U issues an acknowledge and transmitsdata. The FM24C04U/05U continues to output data for eachthe eight bit word. The master will not acknowledge the transferacknowledge received. The read operation is terminated by thebut does generate a stop condition, and therefore the FM24C04U/master not responding with an acknowledge or by generating a05U discontinues transmission. Refer to Figure 6 for the se-stop condition.quence of address, acknowledge and data transfer.The data output is sequential with the data from address nRandom Readfollowed by the data from n + 1. The address counter for readRandom read operations allow the master to access any memoryoperations increments all word address bits, allowing the entirelocation in a random manner. Prior to issuing the slave addressmemory contents to be serially read during one operation. Afterwith the R/W bit set to one, the master must first perform athe entire memory has been read, the counter \"rolls over\" to the“dummy” write operation. The master issues the start condition,beginning of the memory. FM24C04U/05U continues to outputslave address with the R/W bit set to zero and then the bytedata for each acknowledge received. Refer to Figure 8 for theaddress is read. After the byte address acknowledge, the masteraddress, acknowledge, and data transfer sequence.Current Address Read (Figure 6)STSBus Activity:ASLAVETMasterRADDRESSOTPSDA Line1 0 1 0 1Bus Activity:ANOEEPROMCDATAAKCKRandom Read (Figure 7)SSTTSBus Activity:ASLAVEWORDASLAVETMasterRADDRESSADDRESSRADDRESSOTTPSDA LineAAABus Activity:CCCDATA nNOAEEPROMKKKCKSequential Read (Figure 8)SBus Activity:AAATMasterAddressSlaveCCCOKKKPSDA LineANOBus Activity:CDATA n +1DATA n +1DATA n + 2DATA n + xAEEPROMKCK12
www.fairchildsemi.com
FM24C04U/05U Rev. A.3
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROMPhysical Dimensions inches (millimeters) unless otherwise noted0.189 - 0.197(4.800 - 5.004)87650.228 - 0.244(5.791 - 6.198)1234Lead #1IDENT0.150 - 0.157(3.810 - 3.988)0.053 - 0.0690.010 - 0.020x 45¡8¡ Max, Typ.(1.346 - 1.753)0.004 - 0.010(0.254 - 0.508)All leads(0.102 - 0.254)Seating0.004Plane0.0075 - 0.0098(0.102)0.014(0.190 - 0.249)All lead tips0.016 - 0.050(0.356)Typ. All Leads(0.406 - 1.270)0.0500.014 - 0.020Typ. All Leads(1.270)(0.356 - 0.508)Typ.Typ8-Pin Molded Small Outline Package (M8) Package Number M08A0.114 - 0.122(2.90 - 3.10)85(4.16) Typ(7.72) Typ0.246 - 0.2560.169 - 0.177(6.25 - 6.5)(4.30 - 4.50)(1.78) Typ0.123 - 0.128(0.42) Typ(3.13 - 3.30)(0.65) Typ14Land pattern recommendationPin #1 IDENT0.0433(1.1)Max0.002 - 0.006See detail A0.0035 - 0.0079(0.05 - 0.15)0.0256 (0.65)Typ.0.0075 - 0.0118Gage(0.19 - 0.30)0¡-8¡planeDETAIL ATyp. Scale: 40X0.0075 - 0.00980.020 - 0.028Seating (0.19 - 0.25)(0.50 - 0.70)planeNotes: Unless otherwise specified1. Reference JEDEC registration MO153. Variation AA. Dated 7/938-Pin Molded Thin Shrink Small Outline Package (MT8) Package Number MTC0813
www.fairchildsemi.com
FM24C04U/05U Rev. A.3
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROMPhysical Dimensions inches (millimeters) unless otherwise noted0.373 - 0.400(9.474 - 10.16)0.090(2.286)0.032 ± 0.005870.0928765(0.813 ± 0.127)RAD(2.337)DIAPin #1 IDENT+0.250 - 0.005IDENTPin #1(6.35 ± 0.127)Option 110.2801234Option 2(7.112)MIN0.0400.030(1.016)Typ.0.300 - 0.3200.0390.145 - 0.200(0.762)MAX(7.62 - 8.128)20° ± 1°(0.991)(3.683 - 5.080)0.130 ± 0.005(3.302 ± 0.127)95° ± 5°0.125 - 0.1400.009 - 0.0150.1250.065(3.175 - 3.556)(3.175)(1.651)90° ± 4°0.020(0.229 - 0.381)DIATyp(0.508)NOM0.018 ± 0.003Min0.325+0.040-0.015(0.457 ± 0.076)8.255+1.0160.100 ± 0.010-0.381(2.540 ± 0.254)0.045 ± 0.015(1.143 ± 0.381)0.0600.050(1.524)(1.270)Molded Dual-In-Line Package (N) Package Number N08ELife Support PolicyFairchild's products are not authorized for use as critical components in life support devices or systems without the express writtenapproval of the President of Fairchild Semiconductor Corporation. As used herein:1. Life support devices or systems are devices or systems which,2. A critical component is any component of a life support device(a) are intended for surgical implant into the body, or (b) supportor system whose failure to perform can be reasonably ex-or sustain life, and whose failure to perform, when properlypected to cause the failure of the life support device or system,used in accordance with instructions for use provided in theor to affect its safety or effectiveness.labeling, can be reasonably expected to result in a significantinjury to the user.Fairchild SemiconductorFairchild SemiconductorFairchild SemiconductorFairchild SemiconductorAmericasEuropeHong KongJapan Ltd.Customer Response CenterFax:+44 (0) 1793-8568588/F, Room 808, Empire Centre4F, Natsume Bldg.Tel. 1-888-522-5372DeutschTel:+49 (0) 8141-6102-068 Mody Road, Tsimshatsui East2-18-6, Yushima, Bunkyo-kuEnglishTel:+44 (0) 1793-856856Kowloon. Hong KongTokyo, 113-0034 JapanFrançaisTel:+33 (0) 1-6930-3696Tel; +852-2722-8338Tel: 81-3-3818-8840ItalianoTel:+39 (0) 2-249111-1Fax: +852-2722-8383Fax: 81-3-3818-8841Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.14
www.fairchildsemi.com
FM24C04U/05U Rev. A.3
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM
因篇幅问题不能全部显示，请点此查看更多更全内容