SP8716/8/9
520MHz LOW CURRENT TWO-MODULUS DIVIDERS
SP8716 ÷ 40/41, SP8718 ÷ 64/65, SP8719 ÷ 80/81 are50mW programmable dividers with a maximum specifiedoperating frequency of 520MHz over the temperature range-40 °C to + 85 °C.
The signal (clock) inputs are biased internally and requireto be capacitor coupled. The output stage is of an unusual lowpower design featuring dynamic pull-up, and optimised fordriving CMOS. The 0 to 1 output edge should be used to givethe best loop delay performance.
MODULUS CONTROL UNITOUTPUT Vcc OUTPUT0V12348Vcc NO CONNECTIONINPUTINPUT DECOUPLINGSP8716/8/9765FEATURES
DC to 520MHz Operation
-40°C to +85°C Temperature Range
Control Inputs and Outputs are CMOS Compatible
Figure : 1 Pin connections - top viewDP8, MP8QUICK REFERENCE DATA
Supply Voltage 5.0V ± 0.25VSupply Current 10.5mA typ.
ABSOLUTE MAXIMUM RATINGS
Supply voltage pin 2 or 8):
8V
-55°C to +150°C
+175°C2.5V p-p
Storage temperature range:
Max. Junction temperature:https://www.ichunt.comMax. clock I/P voltage:
Vcc8Vcc27kSIGNALINPUT65÷P/P + 11.5k1k3003 OUTPUT40V1MODULUSCONTROLINPUTFigure 2 : Functional diagramSP8716/8/9
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):]
Supply voltage: Vcc = +4/95 to 5.45V, Temperature: Tamb = -40°C to +85°C
Value CharacteristicsMax. frequencyMin. frequency (sinewave input)Power supply currentOutput high voltageOutput low voltageControl input high voltageControl input low voltageControl input high currentControl input low currentClock to output delaySet-up timeRelease timeNOTES
1.Tested at 25°C only
2.Guaranteed but not tested
SymbolfmaxfminICCVOHVOLVINHVINLVINHVINLtptstr1010-0.20283.30(Vcc - 1.2)181.70.41Min.5203011.9Max.MHzMHzmAVVVVmAmAnsnsnsUnitsConditionsInput 100-280mV p-pInput 400-800mV p-pCL = 3pF; pins 2, 8 linkedIL = -0.2mAIL = 0.2mA÷P÷P +1VINH = 8VVINL = 0VCL = 10pFCL = 10pFCL = 10pFNotes121111111222https://www.ichunt.comNOTE
The set-up time ts is defined as the minimum time that can elapse between a L ¡ H transition of the control inputand the next L ¡ H clock pulse transition to ensure that the ÷P mode is obtained.
The release time tr is defined as the minimum time that can elapse between a H ¡ L transition of the control inputand the next L ¡ H clock pulse transition to ensure that the ÷(P +1) mode is obtain
Figure 3 : Timing diagramINPUT AMPLITUDE (mV p-p)10008006004002000520mV30100200300400500FREQUENCY IN MHz
GUARANTEED *OPERATINGWINDOW280mV*Tested asspecified intable ofElectrical
Characteristics
Figure 4 : Typical input characteristicsSP8716/8/9
OPERATING NOTES
1.The inputs are biased internally and coupled to a signalsource with suitable capacitors.
2.If no signal is present the devices will self-oscillate. If thisis undesirable it may be prevented by connecting a 15kresistor from one input to pin 4 (ground). This will reduce thesensitivity.
3.The circuits will operate down to DC but slew rate mustbe better than 100V/,us.
4.The output stage is of an unusual design and is intendedto interface with CMOS. External pull-up resistors or circuitsmust not be used.
5.This device is NOT suitable for driving TTL or itsderivatives.
VccCONTROLINPUT123OUTPUT487651n50SIGNALSOURCE50MONITOR1n0VFigure 5: Toggle frequency test circuithttps://www.ichunt.comFigure 6 : Typical input impedance
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