P89LPC933HDH资料

2020-03-25 来源：步旅网

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P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core4 kB/8 kB/16 kB 3 V byte-erasable ﬂash with 8-bit ADCs

Rev. 07 — 26 November 2008

Product data sheet

1.General description

TheP89LPC933/934/935/936 is a single-chip microcontroller, available in low cost

packages,basedonahighperformanceprocessorarchitecturethatexecutesinstructionsin two to four clocks, six times the rate of standard 80C51 devices. Many system-levelfunctions have been incorporated into theP89LPC933/934/935/936 in order to reducecomponent count, board space, and system cost.

2.Features

2.1Principal features

I4kB/8kB/16kB byte-erasable ﬂash code memory organized into 1kB/2 kB sectorsand 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatiledata storage.

I256-byte RAM data memory. Both the P89LPC935 and P89LPC936 also include a512-byte auxiliary on-chip RAM.

I512-byte customer data EEPROM on chip allows serialization of devices, storage ofsetup parameters, etc. (P89LPC935/936).

IDual 4-input multiplexed 8-bit A/D converters/DAC outputs (P89LPC935/936, singleA/D on P89LPC933/934).Two analog comparators with selectable inputs andreference source.

ITwo 16-bit counter/timers (each may be conﬁgured to toggle a port output upon timeroverﬂowortobecomeaPWMoutput)anda23-bitsystemtimerthatcanalsobeusedas an RTC.

IEnhanced UART with fractional baud rate generator, break detect, framing errordetection, and automatic address detection; 400kHz byte-wide I2C-buscommunication port and SPI communication port.

ICapture/Compare Unit (CCU) provides PWM, input capture, and output comparefunctions (P89LPC935/936).

IHigh-accuracyinternalRCoscillatoroptionallowsoperationwithoutexternaloscillatorcomponents.The RC oscillator option is selectable and ﬁne tunable.

I2.4V to 3.6V VDD operating range. I/O pins are 5V tolerant (may be pulled up ordriven to 5.5V).

I28-pin TSSOP, PLCC, and HVQFN packages with 23 I/O pins minimum and up to 26I/O pins while using on-chip oscillator and reset options.

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P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

2.2Additional features

IA high performance 80C51 CPU provides instruction cycle times of 111ns to 222nsfor all instructions except multiply and divide when executing at 18MHz. This is sixtimes the performance of the standard 80C51 running at the same clock frequency. AlowerclockfrequencyforthesameperformanceresultsinpowersavingsandreducedEMI.

ISerial ﬂash In-Circuit Programming (ICP) allows simple production coding withcommercial EPROM programmers. Flash security bits prevent reading of sensitiveapplication programs.

ISerial ﬂash In-System Programming (ISP) allows coding while the device is mountedin the end application.

IIn-ApplicationProgramming(IAP)oftheﬂashcodememory.Thisallowschangingthecode in a running application.

IWatchdog timer with separate on-chip oscillator, requiring no external components.The watchdog prescaler is selectable from eightvalues.

ILow voltage reset (brownout detect) allows a graceful system shutdown when powerfails. May optionally be conﬁgured as an interrupt.

IIdle and two different power-down reduced power modes. Improved wake-up fromPower-down mode (a LOW interrupt input starts execution). Typical power-downcurrent is 1µA (total power-down with voltage comparators disabled).

IActive-LOW reset. On-chip power-on reset allows operation without external resetcomponents. A reset counter and reset glitch suppression circuitry prevent spuriousand incomplete resets. A software reset function is also available.

IConﬁgurable on-chip oscillator with frequency range options selected by userprogrammed ﬂash conﬁguration bits. Oscillator options support frequencies from20kHz to the maximum operating frequency of 18MHz.

IOscillator fail detect. The watchdog timer has a separate fully on-chip oscillatorallowing it to perform an oscillator fail detect function.

IProgrammable port output conﬁguration options: quasi-bidirectional, open drain,push-pull, input-only.

IPort ‘input pattern match’ detect. Port0 may generate an interrupt when the value ofthe pins match or do not match a programmable pattern.

ILED drive capability (20mA) on all port pins. A maximum limit is speciﬁed for theentire chip.

IControlled slew rate port outputs to reduce EMI. Outputs have approximately 10nsminimum ramp times.

IOnly power and ground connections are required to operate theP89LPC933/934/935/936 when internal reset option is selected.IFour interrupt priority levels.

IEight keypad interrupt inputs, plus two additional external interrupt inputs.ISchmitt trigger port inputs.ISecond data pointer.IEmulation support.

Product data sheetRev. 07 — 26 November 20082 of 75

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P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

3.Product comparison overview

Table1 highlights the differences between the four devices. For a complete list of devicefeatures please seeSection 2 “Features”.

Table 1.DeviceP89LPC933P89LPC934P89LPC935P89LPC936

Product comparison overview

Flash memorySector size4 kB8 kB8 kB16 kB

1 kB1 kB1 kB2 kB

ADC1XXXX

ADC0--XX

CCU--XX

DataEEPROM--XX

4.Ordering information

Table 2.

Ordering information

PackageNameP89LPC935FAP89LPC933HDHP89LPC933FDHP89LPC934FDHP89LPC935FDHP89LPC936FDHP89LPC935FHN

HVQFN28

plastic thermal enhanced very thinquad ﬂat package; no leads;

28terminals; body6×6×0.85mm

SOT788-1

PLCC28TSSOP28

Descriptionplastic leaded chip carrier; 28 leadsplastic thin shrink small outline

package; 28leads; body width 4.4mm

VersionSOT261-2SOT361-1

Type number4.1Ordering options

Table 3.

Ordering options

Flash memory4 kB4kB8kB

Temperature range−40°Cto+125°C−40°Cto+85°C

Frequency0 MHzto18MHzType numberP89LPC933HDHP89LPC933FDHP89LPC935FAP89LPC934FDHP89LPC935FDHP89LPC935FHNP89LPC936FDH

16kB

Product data sheetRev. 07 — 26 November 20083 of 75

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P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

5.Block diagram

P89LPC933/934/935/936ACCELERATED 2-CLOCK 80C51 CPU4 kb/8 kB/16 kBCODE FLASH256-BYTEDATA RAM512-BYTEAUXILIARY RAM512-BYTEDATA EEPROM(P89LPC935/936)P3[1:0]PORT 3CONFIGURABLE I/OsPORT 2CONFIGURABLE I/OsPORT 1CONFIGURABLE I/OsPORT 0CONFIGURABLE I/OsUARTinternal busI2C-BUSTXDRXDSCLSDASPICLKMOSIMISOSSSPIREAL-TIME CLOCK/SYSTEM TIMERTIMER 0TIMER 1T0T1CMP2CIN2BCIN2ACMP1CIN1ACIN1BOCAOCBOCCOCDICAICBAD10AD11AD12AD13DAC1AD00AD01AD02AD03DAC1P2[7:0]ANALOGCOMPARATORSP1[7:0]P0[7:0]CCU (CAPTURE/COMPARE UNIT)(P89LPC935/936)KEYPADINTERRUPTWATCHDOG TIMERAND OSCILLATORADC1/DAC1PROGRAMMABLEOSCILLATOR DIVIDERCPUclockADC0/DAC0(P89LPC935/936)CRYSTALORRESONATORX1X2CONFIGURABLEOSCILLATORON-CHIPRCOSCILLATORPOWER MONITOR(POWER-ON RESET, BROWNOUT RESET)002aab070Fig 1.Block diagramP89LPC933_934_935_936_7© NXP B.V. 2008. All rights reserved.

Product data sheetRev. 07 — 26 November 20084 of 75

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P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

6.Pinning information

6.1Pinning

P2.0/DAC0P2.1P0.0/CMP2/KBI0P1.7P1.6P1.5/RSTVSSP3.1/XTAL1P3.0/XTAL2/CLKOUT12345678928P2.727P2.626P0.1/CIN2B/KBI1/AD1025P0.2/CIN2A/KBI2/AD1124P0.3/CIN1B/KBI3/AD1223P0.4/CIN1A/KBI4/DAC1/AD13P89LPC933HDHP89LPC933FDHP89LPC934FDH22P0.5/CMPREF/KBI521VDD20P0.6/CMP1/KBI619P0.7/T1/KBI718P1.0/TXD17P1.1/RXD16P2.5/SPICLK15P2.4/SSP1.4/INT110P1.3/INT0/SDA11P1.2/T0/SCL12P2.2/MOSI13P2.3/MISO14002aab071Fig 2.P89LPC933/934 TSSOP28 pin conﬁgurationP2.0/ICB/DAC0/AD03P2.1/OCD/AD02P0.0/CMP2/KBI0/AD01P1.7/OCC/AD00P1.6/OCBP1.5/RSTVSSP3.1/XTAL1P3.0/XTAL2/CLKOUT12345678928P2.7/ICA27P2.6/OCA26P0.1/CIN2B/KBI1/AD1025P0.2/CIN2A/KBI2/AD1124P0.3/CIN1B/KBI3/AD1223P0.4/CIN1A/KBI4/DAC1/AD1322P0.5/CMPREF/KBI521VDD20P0.6/CMP1/KBI619P0.7/T1/KBI718P1.0/TXD17P1.1/RXD16P2.5/SPICLK15P2.4/SS002aab072P89LPC935FDHP89LPC936FDHP1.4/INT110P1.3/INT0/SDA11P1.2/T0/SCL12P2.2/MOSI13P2.3/MISO14Fig 3.P89LPC935/936 TSSOP28 pin conﬁgurationP89LPC933_934_935_936_7© NXP B.V. 2008. All rights reserved.

Product data sheetRev. 07 — 26 November 20085 of 75

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P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

26P0.1/CIN2B/KBI1/AD1025P0.2/CIN2A/KBI2/AD1124P0.3/CIN1B/KBI3/AD1223P0.4/CIN1A/KBI4/DAC1/AD1322P0.5/CMPREF/KBI521VDD20P0.6/CMP1/KBI619P0.7/T1/KBI7P1.0/TXD1822P0.1/CIN2B/KBI1/AD1021P0.2/CIN2A/KBI2/AD1120P0.3/CIN1B/KBI3/AD1219P0.4/CIN1A/KBI4/DAC1/AD13002aab074P0.0/CMP2/KBI0/AD01P2.0/ICB/DAC0/AD03125P2.0/ICB/DAC0/AD03P2.4/SS15P1.7/OCC/AD00P2.1/OCD/AD02P1.6/OCBP1.5/RSTVSSP3.1/XTAL1P3.0/XTAL2/CLKOUT56789P89LPC935FAP1.4/INT110P1.3/INT0/SDA11P2.5/SPICLK1624P2.7/ICAP1.2/T0/SCL12P2.2/MOSI13P2.3/MISO14P1.1/RXD1723P2.6/OCAFig 4.P89LPC935 PLCC28 pin conﬁguration27P0.0/CMP2/KBI0/AD0128P1.7/OCC/AD00terminal 1index areaP1.6/OCBP1.5/RSTVSSP3.1/XTAL1P3.0/XTAL2/CLKOUTP1.4/INT1P1.3/INT0/SDA1234567P89LPC935FHN26P2.1/OCD/AD0227P2.6/OCA28P2.7/ICA43218P0.5/CMPREF/KBI517VDD16P0.6/CMP1/KBI615P0.7/T1/KBI7P2.3/MISO10P2.4/SS11P2.5/SPICLK12P1.1/RXD13P1.0/TXD148P1.2/T0/SCL9P2.2/MOSI002aab076Transparent top viewFig 5.P89LPC935 HVQFN28 pin conﬁgurationP89LPC933_934_935_936_7© NXP B.V. 2008. All rights reserved.

Product data sheetRev. 07 — 26 November 20086 of 75

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P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

6.2Pin description

Table 4.SymbolPin descriptionPinTSSOP28,HVQFN28PLCC28P0.0 to P0.7

I/O

Port0:Port0 is an 8-bit I/O port with a user-conﬁgurable output type.DuringresetPort0latchesareconﬁguredintheinputonlymodewiththeinternal pull-up disabled. The operation of Port0 pins as inputs andoutputs depends upon the port conﬁguration selected. Each port pin isconﬁgured independently. Refer toSection 8.13.1 “Port conﬁgurations”andTable 11 “Static characteristics” for details.The Keypad Interrupt feature operates with Port0 pins.All pins have Schmitt trigger inputs.

Port0 also provides various special functions as described below:

P0.0/CMP2/KBI0/AD01

I/OOII

P0.1/CIN2B/26KBI1/AD10

I/OIII

P0.2/CIN2A/25KBI2/AD11

I/OIII

P0.3/CIN1B/24KBI3/AD12

I/OIII

P0.4/CIN1A/23KBI4/DAC1/AD13

I/OIIOI

P0.5/

CMPREF/KBI5P0.6/CMP1/KBI6

I/OII

I/OOI

P0.7/T1/KBI7

I/OI/OI

P89LPC933_934_935_936_7

TypeDescriptionP0.0 —Port0 bit0.

CMP2 —Comparator2 output.KBI0 —Keyboard input0.

AD01 —ADC0 channel 1 analog input. (P89LPC935/936)P0.1 —Port0 bit1.

CIN2B —Comparator2 positive input B.KBI1 —Keyboard input1.

AD10 —ADC1 channel 0 analog input.P0.2 —Port0 bit2.

CIN2A —Comparator2 positive input A.KBI2 —Keyboard input2.

AD11 —ADC1 channel 1 analog input.P0.3 —Port0 bit3.

CIN1B —Comparator1 positive input B.KBI3 —Keyboard input3.

AD12 —ADC1 channel 2 analog input.P0.4 —Port0 bit4.

CIN1A —Comparator1 positive input A.KBI4 —Keyboard input4.

DAC1 —Digital-to-analog converter output 1.AD13 —ADC1 channel 3 analog input.P0.5 —Port0 bit5.

CMPREF —Comparator reference (negative) input.KBI5 —Keyboard input5.P0.6 —Port0 bit6.

CMP1 —Comparator1 output.KBI6 —Keyboard input6.P0.7 —Port0 bit7.

T1 —Timer/counter1 external count input or overﬂow output.KBI7 —Keyboard input7.

Product data sheetRev. 07 — 26 November 20087 of 75

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P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

Table 4.SymbolPin description …continuedPinTSSOP28,HVQFN28PLCC28TypeDescriptionP1.0 to P1.7I/O,I[1]Port1: Port1 is an 8-bit I/O port with a user-conﬁgurable output type,except for three pins as noted below. During reset Port1 latches areconﬁgured in the input only mode with the internal pull-up disabled. Theoperation of the conﬁgurable Port1 pins as inputs and outputs dependsupon the port conﬁguration selected. Each of the conﬁgurable port pinsare programmed independently. Refer toSection 8.13.1 “Port

conﬁgurations” andTable 11 “Static characteristics” for details. P1.2 andP1.3 are open drain when used as outputs. P1.5 is input only.

All pins have Schmitt trigger inputs.

Port1 also provides various special functions as described below:

P1.0/TXDP1.1/RXD

1817

14138

I/OOI/OII/OI/OI/O

P1.0 —Port1 bit0.

TXD —Transmitter output for the serial port.P1.1 —Port1 bit1.

RXD —Receiver input for the serial port.

P1.2 —Port1 bit2 (open-drain when used as output).

T0 —Timer/counter0 external count input or overﬂow output (open-drainwhen used as output).

SCL —I2C serial clock input/output.

P1.3 —Port1 bit3 (open-drain when used as output).INT0 —External interrupt0 input.SDA —I2C serial data input/output.P1.4 —Port1 bit4.INT1 —External interrupt1 input.tP1.5 —Port1 bit5 (input only).RST —External reset input during power-on or if selected via UCFG1.When functioning as a reset input, a LOW on this pin resets the

microcontroller, causing I/O ports and peripherals to take on their defaultstates,andtheprocessorbeginsexecutionataddress0.Alsousedduringa power-on sequence to force ISP mode.When using an oscillatorfrequency above 12MHz, the reset input function of P1.5 must beenabled. An external circuit is required to hold the device in reset atpower-up until VDD has reached its speciﬁed level. When systempower is removed VDD will fall below the minimum speciﬁedoperating voltage. When using an oscillator frequency above

12MHz, in some applications, an external brownout detect circuitmayberequiredtoholdthedeviceinresetwhenVDDfallsbelowtheminimum speciﬁed operating voltage.P1.6 —Port1 bit6.

OCB —Output Compare B. (P89LPC935/936)P1.7 —Port1 bit7.

OCC —Output Compare C. (P89LPC935/936)

AD00 —ADC0 channel 0 analog input. (P89LPC935/936)

P1.2/T0/SCL12

P1.3/INT0/SDA

117I/OII/O

P1.4/INT1P1.5/RST10662IIIIP1.6/OCBP1.7/OCC/AD00

128

I/OOI/OOI

Product data sheetRev. 07 — 26 November 20088 of 75

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P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

Table 4.SymbolPin description …continuedPinTSSOP28,HVQFN28PLCC28TypeDescriptionP2.0 to P2.7I/OPort2: Port2 is an 8-bit I/O port with a user-conﬁgurable output type.DuringresetPort2latchesareconﬁguredintheinputonlymodewiththeinternal pull-up disabled. The operation of Port2 pins as inputs andoutputs depends upon the port conﬁguration selected. Each port pin isconﬁgured independently. Refer toSection 8.13.1 “Port conﬁgurations”andTable 11 “Static characteristics” for details.All pins have Schmitt trigger inputs.

Port2 also provides various special functions as described below:

P2.0/ICB/DAC0/AD03

125I/OIII

P2.0 —Port2 bit0.

ICB —Input Capture B. (P89LPC935/936)DAC0 —Digital-to-analog converter output.

AD03 —ADC0 channel 3 analog input. (P89LPC935/936)P2.1 —Port2 bit1.

OCD —Output Compare D. (P89LPC935/936)

AD02 —ADC0 channel 2 analog input. (P89LPC935/936)P2.2 —Port2 bit2.

MOSI —SPI master out slave in. When conﬁgured as master, this pin isoutput; when conﬁgured as slave, this pin is input.P2.3 —Port2 bit3.

MISO —Whenconﬁguredasmaster,thispinisinput,whenconﬁguredasslave, this pin is output.P2.4 —Port2 bit4.SS —SPI Slave select.P2.5 —Port2 bit5.

SPICLK —SPIclock.Whenconﬁguredasmaster,thispinisoutput;whenconﬁgured as slave, this pin is input.P2.6 —Port2 bit6.

OCA —Output Compare A. (P89LPC935/936)P2.7 —Port2 bit7.

ICA —Input Capture A. (P89LPC935/936)

P2.1/OCD/AD02

226I/OOI

P2.2/MOSI139I/OI/O

P2.3/MISO1410I/OI/O

P2.4/SSP2.5/SPICLKP2.6/OCAP2.7/ICA

1516

1112

I/OII/OI/O

2728

2324

I/OOI/OI

Product data sheetRev. 07 — 26 November 20089 of 75

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P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

Table 4.SymbolPin description …continuedPinTSSOP28,HVQFN28PLCC28TypeDescriptionP3.0 to P3.1I/OPort3: Port3 is a 2-bit I/O port with a user-conﬁgurable output type.DuringresetPort3latchesareconﬁguredintheinputonlymodewiththeinternal pull-up disabled. The operation of Port3 pins as inputs andoutputs depends upon the port conﬁguration selected. Each port pin isconﬁgured independently. Refer toSection 8.13.1 “Port conﬁgurations”andTable 11 “Static characteristics” for details.All pins have Schmitt trigger inputs.

Port3 also provides various special functions as described below:

P3.0/XTAL2/CLKOUT

95I/OOO

P3.0 —Port3 bit0.

XTAL2 —Output from the oscillator ampliﬁer (when a crystal oscillatoroption is selected via the ﬂash conﬁguration.

CLKOUT —CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6). It can be used if the CPU clock is the internal RC oscillator,

watchdogoscillatororexternalclockinput,exceptwhenXTAL1/XTAL2areused to generate clock source for the RTC/system timer.P3.1 —Port3 bit1.

XTAL1 —Inputtotheoscillatorcircuitandinternalclockgeneratorcircuits(when selected via the ﬂash conﬁguration). It can be a port pin if internalRCoscillatororwatchdogoscillatorisusedastheCPUclocksource,andif XTAL1/XTAL2 are not used to generate the clock for the RTC/systemtimer.

Ground: 0V reference.

Power supply: This is the power supply voltage for normal operation aswell as Idle and Power-down modes.

P3.1/XTAL184I/OI

VSSVDD

[1]

721

317

Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.

Product data sheetRev. 07 — 26 November 200810 of 75

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P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

7.Logic symbols

VDDVSSDAC1AD10AD11AD12AD13KBI0KBI1KBI2KBI3KBI4KBI5KBI6KBI7CLKOUTCMP2CIN2BCIN2ACIN1BCIN1ACMPREFCMP1T1XTAL2XTAL1PORT 0PORT 1TXDRXDT0INT0INT1RSTSCLSDAP89LPC933P89LPC934PORT 3PORT 2DAC0MOSIMISOSSSPICLK002aab077 Fig 6. P89LPC933/934 logic symbolVDDVSSDAC1AD01AD10AD11AD12AD13KBI0KBI1KBI2KBI3KBI4KBI5KBI6KBI7CLKOUTCMP2CIN2BCIN2ACIN1BCIN1ACMPREFCMP1T1XTAL2XTAL1PORT 0PORT 1P89LPC935P89LPC936PORT 3PORT 2TXDRXDT0INT0INT1RSTOCBOCCICBOCDMOSIMISOSSSPICLKOCAICASCLSDAAD00AD03AD02DAC0002aab078 Fig 7.P89LPC935/936 logic symbolP89LPC933_934_935_936_7© NXP B.V. 2008. All rights reserved.

Product data sheetRev. 07 — 26 November 200811 of 75

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P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.Functional description

Remark:Please refer to theP89LPC933/934/935/936 User manualfor a more detailedfunctional description.

8.1Special function registers

Remark:SFR accesses are restricted in the following ways:

•User mustnot attempt to access any SFR locations not deﬁned.

•AccessestoanydeﬁnedSFRlocationsmustbestrictlyforthefunctionsfortheSFRs.•SFR bits labeled ‘-’, logic 0 or logic 1 canonly be written and read as follows:

–‘-’ Unless otherwise speciﬁed,must be written with logic 0, but can return anyvaluewhenread(evenifitwaswrittenwithlogic0).Itisareservedbitandmaybeused in future derivatives.–Logic 0must be written with logic 0, and will return a logic 0 when read.–Logic 1must be written with logic 1, and will return a logic 1 when read.

Product data sheetRev. 07 — 26 November 200812 of 75

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx元器件交易网www.cecb2b.comxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxProduct data sheetP89LPC933_934_935_936_7Table 5.Special function registers - P89LPC933/934* indicates SFRs that are bit addressable.NameDescriptionSFRBit functions and addressesReset valueaddr.MSBLSBHexBinaryBit addressE7E6E5E4E3E2E1E0ACC*AccumulatorE0H0000000000ADCON0A/D control register08EH-----ENADC0--0000000000ADCON1A/D control register197HENBI1ENADCITMM1EDGE1ADCI1ENADC1ADCS11ADCS1000000000001ADINSA/D input selectA3HADI13ADI12ADI11ADI10----0000000000ADMODAA/D mode registerAC0HBNDI1BURST1SCC1SCAN1----0000000000ADMODBA/D mode registerBA1HCLK2CLK1CLK0-ENDAC1ENDAC0BSA1-00000x0000AD0DAT3A/D_0 data register3F4H0000000000Rev. 07 — 26 November 2008AD1BHA/D_1 boundary high registerC4HFF11111111AD1BLA/D_1 boundary low registerBCH0000000000AD1DAT0A/D_1 data register0D5H0000000000AD1DAT1A/D_1 data register1D6H0000000000AD1DAT2A/D_1 data register2D7H0000000000AD1DAT3A/D_1 data register3F5H0000000000AUXR1Auxiliary function registerA2HCLKLPEBRRENT1ENT0SRST0-DPS00[1]000000x0Bit addressF7F6F5F4F3F2F1F0B*B registerF0H0000000000BRGR0Baud rate generator rate lowBEH00[2]00000000BRGR1Baud rate generator rate highBFH00[1][2]00000000BRGCONBaud rate generator controlBDH------SBRGSBRGEN00[2]xxxxxx00CMP1Comparator1 control registerACH--CE1CP1CN1OE1CO1CMF100[1]xx000000CMP2Comparator2 control registerADH--CE2CP2CN2OE2CO2CMF200[1]xx000000DIVMCPU clock divide-by-M95H0000000000© NXP B.VcontrolDPTRData pointer (2bytes)13 of 75. 2008. All rights reserved.DPHData pointer high83H0000000000DPLData pointer low82H0000000000FMADRHProgram ﬂash address highE7H0000000000NXP SemiconductorsP89LPC933/934/935/9368-bit microcontroller with accelerated two-clock 80C51 corexxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx元器件交易网www.cecb2b.comxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxProduct data sheetP89LPC933_934_935_936_7Table 5.Special function registers - P89LPC933/934 …continued* indicates SFRs that are bit addressable.NameDescriptionSFRBit functions and addressesReset valueaddr.MSBLSBHexBinaryFMADRLProgram ﬂash address lowE6H0000000000FMCONProgram ﬂash control (Read)E4HBUSY---HVAHVESVOI7001110000Program ﬂash control (Write)E4HFMCMD.FMCMD.FMCMD.FMCMD.FMCMD.FMCMD.FMCMD.FMCMD.76543210FMDATAProgram ﬂash dataE5H0000000000I2ADRI2C slave address registerDBHI2ADR.6I2ADR.5I2ADR.4I2ADR.3I2ADR.2I2ADR.1I2ADR.0GC0000000000Bit addressDFDEDDDCDBDAD9D8I2CON*I2C control registerD8H-I2ENSTASTOSIAA-CRSEL00x00000x0I2DATI2C data registerDAHRev. 07 — 26 November 2008I2SCLHSerial clock generator/SCLDDH0000000000duty cycle register highI2SCLLSerial clock generator/SCLDCH0000000000duty cycle register lowI2STATI2C status registerD9HSTA.4STA.3STA.2STA.1STA.0000F811111000ICRAHInput capture A register highABH0000000000ICRALInput capture A register lowAAH0000000000ICRBHInput capture B register highAFH0000000000ICRBLInput capture B register lowAEH0000000000Bit addressAFAEADACABAAA9A8IEN0*Interrupt enable 0A8HEAEWDRTEBOES/ESRET1EX1ET0EX00000000000Bit addressEFEEEDECEBEAE9E8IEN1*Interrupt enable 1E8HEADEST--ESPIECEKBIEI2C00[3]00x00000Bit addressBFBEBDBCBBBAB9B8IP0*Interrupt priority 0B8H-PWDRTPBOPS/PSRPT1PX1PT0PX000[3]x0000000IP0HInterrupt priority 0 highB7H-PWDRTPBOHPSH/PT1HPX1HPT0HPX0H00[3]x0000000© NXP B.VHPSRHBit addressFFFEFDFCFBFAF9F8IP1*Interrupt priority 1F8HPADPST--PSPIPCPKBIPI2C00[3]00x0000014 of 75. 2008. All rights reserved.IP1HInterrupt priority 1 highF7HPADHPSTH--PSPIHPCHPKBIHPI2CH00[3]00x00000NXP SemiconductorsP89LPC933/934/935/9368-bit microcontroller with accelerated two-clock 80C51 corexxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx元器件交易网www.cecb2b.comxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxProduct data sheetP89LPC933_934_935_936_7Table 5.Special function registers - P89LPC933/934 …continued* indicates SFRs that are bit addressable.NameDescriptionSFRBit functions and addressesReset valueaddr.MSBLSBHexBinaryKBCONKeypad control register94H------PATNKBIF00[3]xxxxxx00_SELKBMASKKeypad interrupt mask86H0000000000registerKBPATNKeypad pattern register93HFF11111111Bit address8786858483828180P0*Port080HT1/KB7CMP1CMPREFCIN1ACIN1BCIN2ACIN2BCMP2[3]/KB6/KB5/KB4/KB3/KB2/KB1/KB0Bit address9796959493929190P1*Port190H--RSTINT1INT0/T0/SCLRXDTXD[3]Rev. 07 — 26 November 2008SDABit addressA7A6A5A4A3A2A1A0P2*Port2A0H--SPICLKSSMISOMOSI--[3]Bit addressB7B6B5B4B3B2B1B0P3*Port3B0H------XTAL1XTAL2[3]P0M1Port0 output mode184H(P0M1.7)(P0M1.6)(P0M1.5)(P0M1.4)(P0M1.3)(P0M1.2)(P0M1.1)(P0M1.0)FF[3]11111111P0M2Port0 output mode285H(P0M2.7)(P0M2.6)(P0M2.5)(P0M2.4)(P0M2.3)(P0M2.2)(P0M2.1)(P0M2.0)00[3]00000000P1M1Port1 output mode191H(P1M1.7)(P1M1.6)-(P1M1.4)(P1M1.3)(P1M1.2)(P1M1.1)(P1M1.0)D3[3]11x1xx11P1M2Port1 output mode292H(P1M2.7)(P1M2.6)-(P1M2.4)(P1M2.3)(P1M2.2)(P1M2.1)(P1M2.0)00[3]00x0xx00P2M1Port2 output mode1A4H(P2M1.7)(P2M1.6)(P2M1.5)(P2M1.4)(P2M1.3)(P2M1.2)(P2M1.1)(P2M1.0)FF[3]11111111P2M2Port2 output mode2A5H(P2M2.7)(P2M2.6)(P2M2.5)(P2M2.4)(P2M2.3)(P2M2.2)(P2M2.1)(P2M2.0)00[3]00000000P3M1Port3 output mode1B1H------(P3M1.1)(P3M1.0)03[3]xxxxxx11P3M2Port3 output mode2B2H------(P3M2.1)(P3M2.0)00[3]xxxxxx00PCONPower control register87HSMOD1SMOD0BOPDBOIGF1GF0PMOD1PMOD00000000000PCONAPower control register AB5HRTCPD-VCPDADPDI2PDSPPDSPD-00[3]00000000© NXP B.VBit addressD7D6D5D4D3D2D1D0PSW*Program status wordD0HCYACF0RS1RS0OVF1P0000000000PT0ADPort0 digital input disableF6H--PT0AD.5PT0AD.4PT0AD.3PT0AD.2PT0AD.1-00xx00000x15 of 75. 2008. All rights reserved.RSTSRCReset source registerDFH--BOFPOFR_BKR_WDR_SFR_EX[4]RTCCONReal-time clock controlD1HRTCFRTCS1RTCS0---ERTCRTCEN60[3][5]011xxx00NXP SemiconductorsP89LPC933/934/935/9368-bit microcontroller with accelerated two-clock 80C51 corexxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx元器件交易网www.cecb2b.comxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxProduct data sheetP89LPC933_934_935_936_7Table 5.Special function registers - P89LPC933/934 …continued* indicates SFRs that are bit addressable.NameDescriptionSFRBit functions and addressesReset valueaddr.MSBLSBHexBinaryRTCHReal-time clock register highD2H00[5]00000000RTCLReal-time clock register lowD3H00[5]00000000SADDRSerial port address registerA9H0000000000SADENSerial port address enableB9H0000000000SBUFSerialPortdatabufferregister99HxxxxxxxxxxBit address9F9E9D9C9B9A9998SCON*Serial port control98HSM0/FESM1SM2RENTB8RB8TIRI0000000000SSTATSerial port extended statusBAHDBMODINTLOCIDISDBISELFEBROESTINT0000000000registerRev. 07 — 26 November 2008SPStack pointer81H0700000111SPCTLSPI control registerE2HSSIGSPENDORDMSTRCPOLCPHASPR1SPR00400000100SPSTATSPI status registerE1HSPIFWCOL------0000xxxxxxSPDATSPI data registerE3H0000000000TAMODTimer0 and 1 auxiliary mode8FH---T1M2---T0M200xxx0xxx0Bit address8F8E8D8C8B8A8988TCON*Timer0 and 1 control88HTF1TR1TF0TR0IE1IT1IE0IT00000000000TH0Timer0 high8CH0000000000TH1Timer1 high8DH0000000000TL0Timer0 low8AH0000000000TL1Timer1 low8BH0000000000TMODTimer0 and 1 mode89HT1GATET1C/TT1M1T1M0T0GATET0C/TT0M1T0M00000000000TRIMInternal oscillator trim register96HRCCLKENCLKTRIM.5TRIM.4TRIM.3TRIM.2TRIM.1TRIM.0[6][5]WDCONWatchdog control registerA7HPRE2PRE1PRE0--WDRUNWDTOFWDCLK[7][5]© NXP B.V16 of 75. 2008. All rights reserved.NXP SemiconductorsP89LPC933/934/935/9368-bit microcontroller with accelerated two-clock 80C51 corexxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx元器件交易网www.cecb2b.comxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxProduct data sheetP89LPC933_934_935_936_7Table 5.Special function registers - P89LPC933/934 …continued* indicates SFRs that are bit addressable.NameDescriptionSFRBit functions and addressesReset valueaddr.MSBLSBHexBinaryWDLWatchdog loadC1HFF11111111WFEED1Watchdog feed1C2HWFEED2Watchdog feed2C3H[1]Unimplemented bits in SFRs (labeled’-’) are X (unknown) at all times. Unless otherwise speciﬁed, ones should not be written to these bits since they may be used for other

purposes in future derivatives. The reset values shown for these bits arelogic0s although they are unknown when read.

[2]BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN=1, the result is unpredictable.[3]All ports are in input only (high-impedance) state after power-up.

[4]TheRSTSRCregisterreﬂectsthecauseoftheP89LPC933/934/935/936reset.Uponapower-upreset,allresetsourceﬂagsareclearedexceptPOFandBOF;thepower-onresetvalue is xx110000.

[5]

The only reset source that affects these SFRs is power-on reset.

Rev. 07 — 26 November 2008[6]On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[7]

Afterreset,thevalueis111001x1,i.e.,PRE2toPRE0arealllogic1,WDRUN=1andWDCLK=1.WDTOFbitislogic1afterwatchdogresetandislogic0afterpower-onreset.Other resets will not affect WDTOF.

© NXP B.V17 of 75. 2008. All rights reserved.NXP SemiconductorsP89LPC933/934/935/9368-bit microcontroller with accelerated two-clock 80C51 corexxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx元器件交易网www.cecb2b.comxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxProduct data sheetP89LPC933_934_935_936_7Table 6.Special function registers - P89LPC935/936* indicates SFRs that are bit addressable.NameDescriptionSFRBit functions and addressesReset valueaddr.MSBLSBHexBinaryBit addressE7E6E5E4E3E2E1E0ACC*AccumulatorE0H0000000000ADCON0A/D control register08EHENBI0ENADCITMM0EDGE0ADCI0ENADC0ADCS01ADCS0000000000000ADCON1A/D control register197HENBI1ENADCITMM1EDGE1ADCI1ENADC1ADCS11ADCS1000000000001ADINSA/D input selectA3HADI13ADI12ADI11ADI10ADI03ADI02ADI01ADI000000000000ADMODAA/D mode registerAC0HBNDI1BURST1SCC1SCAN1BNDI0BURST0SCC0SCAN00000000000ADMODBA/D mode registerBA1HCLK2CLK1CLK0-ENDAC1ENDAC0BSA1BSA000000x0000Rev. 07 — 26 November 2008AD0BHA/D_0 boundary high registerBBHFF11111111AD0BLA/D_0 boundary low registerA6H0000000000AD0DAT0A/D_0 data register0C5H0000000000AD0DAT1A/D_0 data register1C6H0000000000AD0DAT2A/D_0 data register2C7H0000000000AD0DAT3A/D_0 data register3F4H0000000000AD1BHA/D_1 boundary high registerC4HFF11111111AD1BLA/D_1 boundary low registerBCH0000000000AD1DAT0A/D_1 data register0D5H0000000000AD1DAT1A/D_1 data register1D6H0000000000AD1DAT2A/D_1 data register2D7H0000000000AD1DAT3A/D_1 data register3F5H0000000000AUXR1Auxiliary function registerA2HCLKLPEBRRENT1ENT0SRST0-DPS00000000x0Bit addressF7F6F5F4F3F2F1F0B*B registerF0H0000000000© NXP B.VBRGR0[2]Baud rate generator rate lowBEH0000000000BRGR1[2]Baud rate generator rate highBFH0000000000. 2008. All rights reserved.BRGCONBaud rate generator controlBDH------SBRGSBRGEN00[2]xxxxxx00CCCRACapture compare A controlEAHICECA2ICECA1ICECA0ICESAICNFAFCOAOCMA1OCMA0000000000018 of 75registerNXP SemiconductorsP89LPC933/934/935/9368-bit microcontroller with accelerated two-clock 80C51 corexxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx元器件交易网www.cecb2b.comxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxProduct data sheetP89LPC933_934_935_936_7Table 6.Special function registers - P89LPC935/936 …continued* indicates SFRs that are bit addressable.NameDescriptionSFRBit functions and addressesReset valueaddr.MSBLSBHexBinaryCCCRBCapture compare B controlEBHICECB2ICECB1ICECB0ICESBICNFBFCOBOCMB1OCMB00000000000registerCCCRCCapture compare C controlECH-----FCOCOCMC1OCMC000xxxxx000registerCCCRDCapture compare D controlEDH-----FCODOCMD1OCMD000xxxxx000registerCMP1Comparator1 control registerACH--CE1CP1CN1OE1CO1CMF100[3]xx000000CMP2Comparator2 control registerADH--CE2CP2CN2OE2CO2CMF200[3]xx000000DEECONData EEPROM controlF1HEEIFHVERRECTL1ECTL0---EADR80E00001110registerRev. 07 — 26 November 2008DEEDATData EEPROM data registerF2H0000000000DEEADRData EEPROM addressF3H0000000000registerDIVMCPU clock divide-by-M95H0000000000controlDPTRData pointer (2bytes)DPHData pointer high83H0000000000DPLData pointer low82H0000000000FMADRHProgram ﬂash address highE7H0000000000FMADRLProgram ﬂash address lowE6H0000000000FMCONProgram ﬂash control (Read)E4HBUSY---HVAHVESVOI7001110000Program ﬂash control (Write)E4HFMCMD.FMCMD.FMCMD.FMCMD.FMCMD.FMCMD.FMCMD.FMCMD.76543210FMDATAProgram ﬂash dataE5H0000000000I2ADRI2C slave address registerDBHI2ADR.6I2ADR.5I2ADR.4I2ADR.3I2ADR.2I2ADR.1I2ADR.0GC0000000000Bit addressDFDEDDDCDBDAD9D8© NXP B.VI2CON*I2C control registerD8H-I2ENSTASTOSIAA-CRSEL00x00000x0I2DATI2C data registerDAHI2SCLHSerial clock generator/SCLDDH000000000019 of 75. 2008. All rights reserved.duty cycle register highNXP SemiconductorsP89LPC933/934/935/9368-bit microcontroller with accelerated two-clock 80C51 corexxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx元器件交易网www.cecb2b.comxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxProduct data sheetP89LPC933_934_935_936_7Table 6.Special function registers - P89LPC935/936 …continued* indicates SFRs that are bit addressable.NameDescriptionSFRBit functions and addressesReset valueaddr.MSBLSBHexBinaryI2SCLLSerial clock generator/SCLDCH0000000000duty cycle register lowI2STATI2C status registerD9HSTA.4STA.3STA.2STA.1STA.0000F811111000ICRAHInput capture A register highABH0000000000ICRALInput capture A register lowAAH0000000000ICRBHInput capture B register highAFH0000000000ICRBLInput capture B register lowAEH0000000000Bit addressAFAEADACABAAA9A8IEN0*Interrupt enable 0A8HEAEWDRTEBOES/ESRET1EX1ET0EX00000000000Rev. 07 — 26 November 2008Bit addressEFEEEDECEBEAE9E8IEN1*Interrupt enable 1E8HEADEEEST-ECCUESPIECEKBIEI2C00[3]00x00000Bit addressBFBEBDBCBBBAB9B8IP0*Interrupt priority 0B8H-PWDRTPBOPS/PSRPT1PX1PT0PX000[3]x0000000IP0HInterrupt priority 0 highB7H-PWDRTPBOHPSH/PT1HPX1HPT0HPX0H00[3]x0000000HPSRHBit addressFFFEFDFCFBFAF9F8IP1*Interrupt priority 1F8HPADEEPST-PCCUPSPIPCPKBIPI2C00[3]00x00000IP1HInterrupt priority 1 highF7HPAEEHPSTH-PCCUHPSPIHPCHPKBIHPI2CH00[3]00x00000KBCONKeypad control register94H------PATNKBIF00[3]xxxxxx00_SELKBMASKKeypad interrupt mask86H0000000000registerKBPATNKeypad pattern register93HFF11111111OCRAHOutput compare A registerEFH0000000000high© NXP B.VOCRALOutput compare A registerEEH0000000000lowOCRBHOutput compare B registerFBH0000000000high20 of 75. 2008. All rights reserved.OCRBLOutput compare B registerFAH0000000000lowNXP SemiconductorsP89LPC933/934/935/9368-bit microcontroller with accelerated two-clock 80C51 corexxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx元器件交易网www.cecb2b.comxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxProduct data sheetP89LPC933_934_935_936_7Table 6.Special function registers - P89LPC935/936 …continued* indicates SFRs that are bit addressable.NameDescriptionSFRBit functions and addressesReset valueaddr.MSBLSBHexBinaryOCRCHOutput compare C registerFDH0000000000highOCRCLOutput compare C registerFCH0000000000lowOCRDHOutput compare D registerFFH0000000000highOCRDLOutput compare D registerFEH0000000000lowBit address8786858483828180P0*Port080HT1/KB7CMP1CMPREFCIN1ACIN1BCIN2ACIN2BCMP2[3]Rev. 07 — 26 November 2008/KB6/KB5/KB4/KB3/KB2/KB1/KB0Bit address9796959493929190P1*Port190HOCCOCBRSTINT1INT0/T0/SCLRXDTXD[3]SDABit addressA7A6A5A4A3A2A1A0P2*Port2A0HICAOCASPICLKSSMISOMOSIOCDICB[3]Bit addressB7B6B5B4B3B2B1B0P3*Port3B0H------XTAL1XTAL2[3]P0M1Port0 output mode184H(P0M1.7)(P0M1.6)(P0M1.5)(P0M1.4)(P0M1.3)(P0M1.2)(P0M1.1)(P0M1.0)FF[3]11111111P0M2Port0 output mode285H(P0M2.7)(P0M2.6)(P0M2.5)(P0M2.4)(P0M2.3)(P0M2.2)(P0M2.1)(P0M2.0)00[3]00000000P1M1Port1 output mode191H(P1M1.7)(P1M1.6)-(P1M1.4)(P1M1.3)(P1M1.2)(P1M1.1)(P1M1.0)D3[3]11x1xx11P1M2Port1 output mode292H(P1M2.7)(P1M2.6)-(P1M2.4)(P1M2.3)(P1M2.2)(P1M2.1)(P1M2.0)00[3]00x0xx00P2M1Port2 output mode1A4H(P2M1.7)(P2M1.6)(P2M1.5)(P2M1.4)(P2M1.3)(P2M1.2)(P2M1.1)(P2M1.0)FF[3]11111111P2M2Port2 output mode2A5H(P2M2.7)(P2M2.6)(P2M2.5)(P2M2.4)(P2M2.3)(P2M2.2)(P2M2.1)(P2M2.0)00[3]00000000P3M1Port3 output mode1B1H------(P3M1.1)(P3M1.0)03[3]xxxxxx11© NXP B.VP3M2Port3 output mode2B2H------(P3M2.1)(P3M2.0)00[3]xxxxxx00PCONPower control register87HSMOD1SMOD0BOPDBOIGF1GF0PMOD1PMOD00000000000PCONAPower control register AB5HRTCPDDEEPDVCPDADPDI2PDSPPDSPDCCUPD00[3]00000000Bit addressD7D6D5D4D3D2D1D021 of 75. 2008. All rights reserved.PSW*Program status wordD0HCYACF0RS1RS0OVF1P0000000000PT0ADPort0 digital input disableF6H--PT0AD.5PT0AD.4PT0AD.3PT0AD.2PT0AD.1-00xx00000xNXP SemiconductorsP89LPC933/934/935/9368-bit microcontroller with accelerated two-clock 80C51 corexxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx元器件交易网www.cecb2b.comxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxProduct data sheetP89LPC933_934_935_936_7Table 6.Special function registers - P89LPC935/936 …continued* indicates SFRs that are bit addressable.NameDescriptionSFRBit functions and addressesReset valueaddr.MSBLSBHexBinaryRSTSRCReset source registerDFH--BOFPOFR_BKR_WDR_SFR_EX[4]RTCCONReal-time clock controlD1HRTCFRTCS1RTCS0---ERTCRTCEN60[3][5]011xxx00RTCHReal-time clock register highD2H00[5]00000000RTCLReal-time clock register lowD3H00[5]00000000SADDRSerial port address registerA9H0000000000SADENSerial port address enableB9H0000000000SBUFSerialPortdatabufferregister99HxxxxxxxxxxBit address9F9E9D9C9B9A9998SCON*Serial port control98HSM0/FESM1SM2RENTB8RB8TIRI0000000000Rev. 07 — 26 November 2008SSTATSerial port extended statusBAHDBMODINTLOCIDISDBISELFEBROESTINT0000000000registerSPStack pointer81H0700000111SPCTLSPI control registerE2HSSIGSPENDORDMSTRCPOLCPHASPR1SPR00400000100SPSTATSPI status registerE1HSPIFWCOL------0000xxxxxxSPDATSPI data registerE3H0000000000TAMODTimer0 and 1 auxiliary mode8FH---T1M2---T0M200xxx0xxx0Bit address8F8E8D8C8B8A8988TCON*Timer0 and 1 control88HTF1TR1TF0TR0IE1IT1IE0IT00000000000TCR20*CCU control register 0C8HPLEENHLTRNHLTENALTCDALTABTDIR2TMOD21TMOD200000000000TCR21CCU control register 1F9HTCOU2---PLLDV.3PLLDV.2PLLDV.1PLLDV.0000xxx0000TH0Timer0 high8CH0000000000TH1Timer1 high8DH0000000000TH2CCU timer highCDH0000000000TICR2CCU interrupt control registerC9HTOIE2TOCIE2TOCIE2TOCIE2BTOCIE2A-TICIE2BTICIE2A0000000x00© NXP B.VDCTIFR2CCU interrupt ﬂag registerE9HTOIF2TOCF2DTOCF2CTOCF2BTOCF2A-TICF2BTICF2A0000000x00TISE2CCU interrupt status encodeDEH-----ENCINT.ENCINT.ENCINT.00xxxxx000register21022 of 75. 2008. All rights reserved.TL0Timer0 low8AH0000000000TL1Timer1 low8BH0000000000NXP SemiconductorsP89LPC933/934/935/9368-bit microcontroller with accelerated two-clock 80C51 corexxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx元器件交易网www.cecb2b.comxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxProduct data sheetP89LPC933_934_935_936_7Table 6.Special function registers - P89LPC935/936 …continued* indicates SFRs that are bit addressable.NameDescriptionSFRBit functions and addressesReset valueaddr.MSBLSBHexBinaryTL2CCU timer lowCCH0000000000TMODTimer0 and 1 mode89HT1GATET1C/TT1M1T1M0T0GATET0C/TT0M1T0M00000000000TOR2HCCU reload register highCFH0000000000TOR2LCCU reload register lowCEH0000000000TPCR2HPrescalercontrolregisterhighCBH------TPCR2H.TPCR2H.00xxxxxx0010TPCR2LPrescaler control register lowCAHTPCR2L.TPCR2L.TPCR2L.TPCR2L.TPCR2L.TPCR2L.TPCR2L.TPCR2L.000000000076543210TRIMInternal oscillator trim register96HRCCLKENCLKTRIM.5TRIM.4TRIM.3TRIM.2TRIM.1TRIM.0[6][5]WDCONWatchdog control registerA7HPRE2PRE1PRE0--WDRUNWDTOFWDCLK[7][5]Rev. 07 — 26 November 2008WDLWatchdog loadC1HFF11111111WFEED1Watchdog feed1C2HWFEED2Watchdog feed2C3H[1]Unimplemented bits in SFRs (labeled’-’) are X (unknown) at all times. Unless otherwise speciﬁed, ones should not be written to these bits since they may be used for other

purposes in future derivatives. The reset values shown for these bits arelogic0s although they are unknown when read.[2]All ports are in input only (high-impedance) state after power-up.

[3]BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN=1, the result is unpredictable.

[4]TheRSTSRCregisterreﬂectsthecauseoftheP89LPC933/934/935/936reset.Uponapower-upreset,allresetsourceﬂagsareclearedexceptPOFandBOF;thepower-onresetvalue is xx110000.

[5]Afterreset,thevalueis111001x1,i.e.,PRE2toPRE0arealllogic1,WDRUN=1andWDCLK=1.WDTOFbitislogic1afterwatchdogresetandislogic0afterpower-onreset.Other resets will not affect WDTOF.

[6]On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.[7]

The only reset source that affects these SFRs is power-on reset.

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P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.2Enhanced CPU

TheP89LPC933/934/935/936usesanenhanced80C51CPUwhichrunsatsixtimesthespeedofstandard80C51devices.AmachinecycleconsistsoftwoCPUclockcycles,andmost instructions execute in one or two machine cycles.

8.3Clocks

8.3.1Clock deﬁnitions

TheP89LPC933/934/935/936 device has several internal clocks as deﬁned below:OSCCLK —Input to the DIVM clock divider. OSCCLK is selected from one of four clocksources (seeFigure8) and can also be optionally divided to a slower frequency (seeSection 8.8 “CCLK modiﬁcation: DIVM register”).Remark:fosc is deﬁned as the OSCCLK frequency.

CCLK —CPUclock;outputoftheclockdivider.TherearetwoCCLKcyclespermachinecycle,andmostinstructionsareexecutedinonetotwomachinecycles(twoorfourCCLKcycles).

RCCLK —The internal 7.373MHz RC oscillator output.PCLK —Clock for the various peripheral devices and isCCLK⁄2.

8.3.2CPU clock (OSCCLK)

TheP89LPC933/934/935/936 provides several user-selectable oscillator options ingenerating the CPU clock. This allows optimization for a range of needs from highprecision to lowest possible cost. These options are conﬁgured when the ﬂash is

programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, anoscillator using an external crystal, or an external clock source. The crystal oscillator canbeoptimizedforlow,medium,orhighfrequencycrystalscoveringarangefrom20kHzto18MHz.

8.3.3Low speed oscillator option

This option supports an external crystal in the range of 20kHz to 100kHz. Ceramicresonators are also supported in this conﬁguration.

8.3.4Medium speed oscillator option

This option supports an external crystal in the range of 100kHz to 4MHz. Ceramicresonators are also supported in this conﬁguration.

8.3.5High speed oscillator option

This option supports an external crystal in the range of 4MHz to 18MHz. Ceramicresonators are also supported in this conﬁguration.

8.3.6Clock output

The P89LPC933/934/935/936 supports a user-selectable clock output function on theXTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs ifanother clock source has been selected (on-chip RC oscillator, watchdog oscillator,

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external clock input on X1) and if the RTC is not using the crystal oscillator as its clocksource.ThisallowsexternaldevicestosynchronizetotheP89LPC933/934/935/936.Thisoutput is enabled by the ENCLK bit in the TRIM register.

Thefrequencyofthisclockoutputis1⁄2thatoftheCCLK.Iftheclockoutputisnotneededin Idle mode, it may be turned off prior to entering Idle, saving additional power.

8.4On-chip RC oscillator option

TheP89LPC933/934/935/936 has a 6-bit TRIM register that can be used to tune thefrequency of the RC oscillator. During reset, the TRIM value is initialized to a factorypreprogrammed value to adjust the oscillator frequency to 7.373MHz±1% at roomtemperature. End-user applications can write to the TRIM register to adjust the on-chipRC oscillator to other frequencies.

8.5Watchdog oscillator option

Thewatchdoghasaseparateoscillatorwhichhasafrequencyof400kHz.Thisoscillatorcan be used to save power when a high clock frequency is not needed.

8.6External clock input option

In this conﬁguration, the processor clock is derived from an external source driving theP3.1/XTAL1 pin. The rate may be from 0Hz up to 18MHz. The P3.0/XTAL2 pin may beused as a standard port pin or a clock output.When using an oscillator frequency

above 12MHz, the reset input function of P1.5 must be enabled. An external circuitis required to hold the device in reset at power-up until VDD has reached its

speciﬁed level. When system power is removed VDD will fall below the minimumspeciﬁed operating voltage. When using an oscillator frequency above 12MHz, insome applications, an external brownout detect circuit may be required to hold thedevice in reset when VDD falls below the minimum speciﬁed operating voltage.

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XTAL1XTAL2HIGH FREQUENCYMEDIUM FREQUENCYLOW FREQUENCYRTCADC1ADC0(P89LPC935/936)OSCCLKRCOSCILLATOR(7.3728 MHz ±1 %)WATCHDOGOSCILLATOR(400 kHz +30 % −20 %)TIMER 0 ANDTIMER 1PCLKRCCLKDIVMCCLK÷2PCLKCPUWDT32 × PLLCCU(P89LPC935/936)002aab079I2C-BUSSPIUARTFig 8.Block diagram of oscillator controlP89LPC933_934_935_936_7© NXP B.V. 2008. All rights reserved.

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8.7CCLK wake-up delay

TheP89LPC933/934/935/936 has an internal wake-up timer that delays the clock until itstabilizes depending on the clock source used. If the clock source is any of the threecrystal selections (low, medium and high frequencies) the delay is 992OSCCLK cyclesplus 60µsto100µs. If the clock source is either the internal RC oscillator, watchdogoscillator, or external clock, the delay is 224OSCCLK cycles plus 60µsto100µs.

8.8CCLK modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510times by conﬁguring a dividingregister, DIVM, to generate CCLK. This feature makes it possible to temporarily run theCPU at a lower rate, reducing power consumption. By dividing the clock, the CPU canretaintheabilitytorespondtoeventsthatwouldnotexitIdlemodebyexecutingitsnormalprogramatalowerrate.Thiscanalsoallowbypassingtheoscillatorstart-uptimeincaseswhere Power-down mode would otherwise be used. The value of DIVM may be changedby the program at any time without interrupting code execution.

8.9Low power select

TheP89LPC933/934/935/936 is designed to run at 18 MHz (CCLK) maximum. However,if CCLK is 8MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lowerthe power consumption further. On any reset, CLKLP is logic 0 allowing highest

performance access. This bit can then be set in software if CCLK is running at 8MHz orslower.

8.10Memory organization

The variousP89LPC933/934/935/936 memory spaces are as follows:

•DATA

128bytes of internal data memory space (00H:7FH) accessed via direct or indirectaddressing, using instructions other than MOVX and MOVC. All or part of the Stackmay be in this area.

•IDATA

Indirect Data. 256bytes of internal data memory space (00H:FFH) accessed viaindirect addressing using instructions other than MOVX and MOVC. All or part of theStack may be in this area. This area includes the DATA area and the 128bytesimmediately above it.

•SFR

Selected CPU registers and peripheral control and status registers, accessible onlyvia direct addressing.

•XDATA (P89LPC935/936)

‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64kB memory spaceaddressed via the MOVX instruction using the SPTR, R0, or R1. All or part of thisspace could be implemented on-chip. The P89LPC935/936 has 512bytes of on-chipXDATA memory.

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•CODE

64kB of code memory space, accessed as part of program execution and via theMOVC instruction. The P89LPC933/934/935/936 have 4 KB/8kB/16 kB of on-chipCode memory.

The P89LPC935/936 also has 512bytes of on-chip data EEPROM that is accessed viaSFRs (seeSection 8.27 “Data EEPROM (P89LPC935/936)”).

8.11Data RAM arrangement

The 768bytes of on-chip RAM are organized as shown inTable7.

Table 7.TypeDATAIDATAXDATA

On-chip data memory usages

Data RAMMemory that can be addressed directly and indirectlyMemory that can be addressed indirectly

Auxiliary (‘External Data’) on-chip memory that is accessedusing the MOVX instructions (P89LPC935/936)

Size (bytes)128256512

8.12Interrupts

TheP89LPC933/934/935/936 uses a four priority level interrupt structure. This allowsgreat ﬂexibility in controlling the handling of the many interrupt sources. The

P89LPC933/934/935/936 supports 15interrupt sources: external interrupts 0 and 1,

timers0and1,serialportTx,serialportRx,combinedserialportRx/Tx,brownoutdetect,watchdog/Real-Time clock, I2C-bus, keyboard, comparators 1 and 2, SPI, CCU, dataEEPROM write/ADC completion.

Eachinterruptsourcecanbeindividuallyenabledordisabledbysettingorclearingabitinthe interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a globaldisable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels bysetting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. Aninterrupt service routine in progress can be interrupted by a higher priority interrupt, butnotbyanotherinterruptofthesameorlowerpriority.Thehighestpriorityinterruptservicecannot be interrupted by any other interrupt source. If two requests of different prioritylevels are pending at the start of an instruction, the request of higher priority level isserviced.

If requests of the same priority level are pending at the start of an instruction, an internalpolling sequence determines which request is serviced. This is called the arbitrationranking.

Remark:The arbitration ranking is only used to resolve pending requests of the samepriority level.

8.12.1External interrupt inputs

TheP89LPC933/934/935/936 has two external interrupt inputs as well as the KeypadInterrupt function. The two interrupt inputs are identical to those present on the standard80C51 microcontrollers.

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These external interrupts can be programmed to be level-triggered or edge-triggered bysetting or clearing bit IT1 or IT0 in register TCON.

In edge-triggered mode, if successive samples of theINTn pin show a HIGH in one cycleand a LOW in the next cycle, the interrupt request ﬂag IEn in TCON is set, causing aninterrupt request.

If an external interrupt is enabled when theP89LPC933/934/935/936 is put into

Power-down or Idle mode, the interrupt will cause the processor to wake-up and resumeoperation. Refer toSection 8.15 “Power reduction modes” for details.

IE0EX0IE1EX1BOFEBORTCFERTC(RTCCON.1)WDOVFKBIFEKBIEWDRTCMF2CMF1ECEA (IE0.7)TF0ET0TF1ET1TI & RI/RIES/ESRTIESTSIEI2CSPIFESPIany CCU interrupt(1)ECCUEEIF(2)ENADCI0(2)ADCI0(2)ENADCI1ADCI1ENBI0(2)BNDI0(2)ENBI1BNDI1EADEE (P89LPC935)EAD (P89LPC933/934)wake-up(if in power-down)interruptto CPU002aab081 (1)SeeSection 8.19 “CCU (P89LPC935/936)”(2)P89LPC935/936Fig 9.Interrupt sources, interrupt enables, and power-down wake-up sourcesP89LPC933_934_935_936_7© NXP B.V. 2008. All rights reserved.

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8.13I/O ports

TheP89LPC933/934/935/936 has four I/O ports: Port0, Port1, Port2, and Port3.Ports0, 1 and 2 are 8-bit ports, and Port3 is a 2-bit port. The exact number of I/O pinsavailable depends upon the clock and reset options chosen, as shown inTable8.

Table 8.

Number of I/O pins available

Reset optionNo external reset (except duringpower-up)

ExternalRST pin supportedExternal clock input

No external reset (except duringpower-up)

ExternalRST pin supported[1]Low/medium/high speed oscillator(externalcrystal or resonator)

No external reset (except duringpower-up)

ExternalRST pin supported[1][1]

Required for operation above 12 MHz.

Clock sourceOn-chip oscillator or watchdogoscillator

Number of I/O pins(28-pin package)2625252424238.13.1Port conﬁgurations

AllbutthreeI/OportpinsontheP89LPC933/934/935/936maybeconﬁguredbysoftwareto one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51port outputs), push-pull, open drain, and input-only. Two conﬁguration registers for eachport select the output type for each port pin.

1.P1.5 (RST) can only be an input and cannot be conﬁgured.2.P1.2(SCL/T0)andP1.3(SDA/INT0)mayonlybeconﬁguredtobeeitherinput-onlyoropen-drain.

8.13.1.1

Quasi-bidirectional output conﬁguration

Quasi-bidirectionaloutputtypecanbeusedasbothaninputandoutputwithouttheneedto reconﬁgure the port. This is possible because when the port outputs a logic HIGH, it isweakly driven, allowing an external device to pull the pin LOW. When the pin is drivenLOW, it is driven strongly and able to sink a fairly large current. These features are

somewhatsimilartoanopen-drainoutputexceptthattherearethreepull-uptransistorsinthe quasi-bidirectional output that serve different purposes.

TheP89LPC933/934/935/936 is a 3V device, but the pins are 5V-tolerant. In

quasi-bidirectional mode, if a user applies 5V on the pin, there will be a current ﬂowingfrom the pin to VDD, causing extra power consumption. Therefore, applying 5V inquasi-bidirectional mode is discouraged.

Aquasi-bidirectionalportpinhasaSchmitttriggerinputthatalsohasaglitchsuppressioncircuit.

8.13.1.2

Open-drain output conﬁguration

The open-drain output conﬁguration turns off all pull-ups and only drives the pull-downtransistor of the port driver when the port latch contains a logic0. To be used as a logicoutput,aportconﬁguredinthismannermusthaveanexternalpull-up,typicallyaresistortied to VDD.

P89LPC933_934_935_936_7

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An open-drain port pin has a Schmitt trigger input that also has a glitch suppressioncircuit.

8.13.1.3

Input-only conﬁguration

The input-only port conﬁguration has no output drivers. It is a Schmitt trigger input thatalso has a glitch suppression circuit.

8.13.1.4

Push-pull output conﬁguration

The push-pull output conﬁguration has the same pull-down structure as both the

open-drain and the quasi-bidirectional output modes, but provides a continuous strongpull-up when the port latch contains a logic1. The push-pull mode may be used whenmore source current is needed from a port output. A push-pull port pin has a Schmitttrigger input that also has a glitch suppression circuit.

8.13.2Port0 analog functions

TheP89LPC933/934/935/936 incorporates two Analog Comparators. In order to give thebestanalogfunctionperformanceandtominimizepowerconsumption,pinsthatarebeingused for analog functions must have the digital outputs and digital inputs disabled.Digital outputs are disabled by putting the port output into the Input-Only(high-impedance) mode.

Digital inputs on Port0 may be disabled through the use of the PT0AD register, bits1:5.On any reset, PT0AD[1:5] defaults to logic 0s to enable digital functions.

8.13.3Additional port features

After power-up, all pins are in Input-Only mode.

Remark:Please note that this is different from the LPC76x series of devices.

•After power-up, all I/O pins except P1.5, may be conﬁgured by software.

•PinP1.5isinputonly.PinsP1.2andP1.3andareconﬁgurableforeitherinput-onlyor

open-drain.

Every output on theP89LPC933/934/935/936 has been designed to sink typical LEDdrive current. However, there is a maximum total output current for all ports which mustnot be exceeded. Please refer toTable 11 “Static characteristics” for detailedspeciﬁcations.

Allportspinsthatcanfunctionasanoutputhaveslewratecontrolledoutputstolimitnoisegenerated by quickly switching output signals. The slew rate is factory-set toapproximately 10ns rise and fall times.

8.14Power monitoring functions

TheP89LPC933/934/935/936 incorporates power monitoring functions designed toprevent incorrect operation during initial power-up and power loss or reduction duringoperation. This is accomplished with two hardware functions: Power-on detect andbrownout detect.

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8.14.1Brownout detection

The brownout detect function determines if the power supply voltage drops below a

certainlevel.Thedefaultoperationisforabrownoutdetectiontocauseaprocessorreset,however it may alternatively be conﬁgured to generate an interrupt.Brownout detection may be enabled or disabled in software.

If brownout detection is enabled the brownout condition occurs when VDD falls below thebrownouttripvoltage,Vbo(seeTable11“Staticcharacteristics”),andisnegatedwhenVDDrises above Vbo. If theP89LPC933/934/935/936 device is to operate with a power supplythatcanbebelow2.7V,BOEshouldbeleftintheunprogrammedstatesothatthedevicecan operate at 2.4V, otherwise continuous brownout reset may prevent the device fromoperating.

For correct activation of brownout detect, the VDD rise and fall times must be observed.Please seeTable 11 “Static characteristics” for speciﬁcations.

8.14.2Power-on detection

Thepower-ondetecthasafunctionsimilartothebrownoutdetect,butisdesignedtoworkas power comes up initially, before the power supply voltage reaches a level wherebrownout detect can work. The POF ﬂag in the RSTSRC register is set to indicate aninitial power-up condition. The POF ﬂag will remain set until cleared by software.

8.15Power reduction modes

TheP89LPC933/934/935/936 supports three different power reduction modes. Thesemodes are Idle mode, Power-down mode, and total Power-down mode.

8.15.1Idle mode

Idle mode leaves peripherals running in order to allow them to activate the processorwhen an interrupt is generated. Any enabled interrupt source or reset may terminate Idlemode.

8.15.2Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption. TheP89LPC933/934/935/936 exits Power-down mode via any reset, or certain interrupts. InPower-down mode, the power supply voltage may be reduced to the RAM keep-alivevoltage VRAM. This retains the RAM contents at the point where Power-down mode wasentered.SFRcontentsarenotguaranteedafterVDDhasbeenloweredtoVDDR,thereforeit is highly recommended to wake-up the processor via reset in this case. VDD must beraised to within the operating range before the Power-down mode is exited.

Some chip functions continue to operate and draw power during Power-down mode,increasing the total power used during power-down. These include: brownout detect,watchdog timer, Comparators (note that Comparators can be powered-down separately),andRTC/systemtimer.TheinternalRCoscillatorisdisabledunlessboththeRCoscillatorhas been selected as the system clock and the RTC is enabled.

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8.15.3Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry andthe voltage comparators are also disabled to conserve additional power. The internal RCoscillatorisdisabledunlessboththeRCoscillatorhasbeenselectedasthesystemclockand the RTC is enabled. If the internal RC oscillator is used to clock the RTC during

power-down,therewillbehighpowerconsumption.Pleaseuseanexternallowfrequencyclock to achieve low power with the RTC running during power-down.

8.16Reset

The P1.5/RST pin can function as either a LOW-active reset input or as a digital input,P1.5.TheResetPinEnable(RPE)bitinUCFG1,whensettologic1,enablestheexternalreset input function on P1.5. When cleared, P1.5 may be used as an input pin.

Remark:During a power-up sequence, the RPE selection is overridden and this pin willalwaysfunctionsasaresetinput.AnexternalcircuitconnectedtothispinshouldnotholdthispinLOWduringapower-onsequenceasthiswillkeepthedeviceinreset.After power-up this input will function either as an external reset input or as a digital inputas deﬁned by the RPE bit. Only a power-up reset will temporarily override the selectiondeﬁned by RPE bit. Other sources of reset will not override the RPE bit.Reset can be triggered from the following sources:

••••••

External reset pin (during power-up or if user conﬁgured via UCFG1).Power-on detect.Brownout detect.Watchdog timer.Software reset.

UART break character detect reset.

For every reset source, there is a ﬂag in the reset register, RSTSRC. The user can readthis register to determine the most recent reset source. These ﬂag bits can be cleared insoftware by writing a logic 0 to the corresponding bit. More than one ﬂag bit may be set:

•During a power-on reset, both POF and BOF are set but the other ﬂag bits are

cleared.

•Foranyotherreset,previouslysetﬂagbitsthathavenotbeenclearedwillremainset.

8.16.1Reset vector

Following reset, theP89LPC933/934/935/936 will fetch instructions from either address0000H or the boot address. The boot address is formed by using the boot vector as thehigh byte of the address and the low byte of the address=00H.

The boot address will be used if a UART break reset occurs, or the non-volatile boot

status bit (BOOTSTAT.0)=1, or the device is forced into ISP mode during power-on (seeP89LPC933/934/935/936 User manual). Otherwise, instructions will be fetched fromaddress 0000H.

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8.17Timers/counters 0 and 1

TheP89LPC933/934/935/936 has two general purpose counter/timers which are upwardcompatible with the standard 80C51 Timer0 and Timer1. Both can be conﬁgured tooperate either as timers or event counter. An option to automatically toggle the T0 and/orT1 pins upon timer overﬂow has been added.

In the ‘timer’ function, the register is incremented every machine cycle.

Inthe‘counter’function,theregisterisincrementedinresponsetoa1-to-0transitionatitscorresponding external input pin, T0 or T1. In this function, the external input is sampledonce during every machine cycle.

Timer0 and Timer1 have ﬁve operating modes (modes 0, 1, 2, 3 and 6). Modes 0, 1, 2and 6 are the same for both timers/counters. Mode3 is different.

8.17.1Mode0

PuttingeithertimerintoMode0makesitlooklikean8048timer,whichisan8-bitcounterwith a divide-by-32 prescaler. In this mode, the timer register is conﬁgured as a 13-bitregister. Mode0 operation is the same for Timer0 and Timer1.

8.17.2Mode1

Mode1 is the same as Mode0, except that all 16bits of the timer register are used.

8.17.3Mode2

Mode2 conﬁgures the timer register as an 8-bit counter with automatic reload. Mode2operation is the same for Timer0 and Timer1.

8.17.4Mode3

When Timer1 is in Mode3 it is stopped. Timer0 in Mode3 forms two separate 8-bit

countersandisprovidedforapplicationsthatrequireanextra8-bittimer.WhenTimer1isin Mode3 it can still be used by the serial port as a baud rate generator.

8.17.5Mode6

In this mode, the corresponding timer can be changed to a PWM with a full period of256timerclocks.

8.17.6Timer overﬂow toggle output

Timers0 and 1 can be conﬁgured to automatically toggle a port output whenever a timeroverﬂow occurs. The same device pins that are used for the T0 and T1 count inputs arealso used for the timer toggle outputs. The port outputs will be a logic1 prior to the ﬁrsttimer overﬂow when this mode is turned on.

8.18RTC/system timer

TheP89LPC933/934/935/936hasasimpleRTCthatallowsausertocontinuerunninganaccurate timer while the rest of the device is powered-down. The RTC can be a wake-upor an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescalerand a 16-bit loadable down counter. When it reaches all logic 0s, the counter will bereloaded again and the RTCF ﬂag will be set. The clock source for this counter can beeithertheCPUclock(CCLK)ortheXTALoscillator,providedthattheXTALoscillatorisnot

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being used as the CPU clock. If the XTAL oscillator is used as the CPU clock, then theRTC will use CCLK as its clock source. Only power-on reset will reset the RTC and itsassociated SFRs to the default state.

8.19CCU (P89LPC935/936)

This unit features:

•A 16-bit timer with 16-bit reload on overﬂow.

•Selectable clock, with prescaler to divide clock source by any integral number

between 1 and 1024.

••••

Four compare/PWM outputs with selectable polarity.Symmetrical/asymmetrical PWM selection.

Two capture inputs with event counter and digital noise rejection ﬁlter.Seven interrupts with common interrupt vector (oneoverﬂow, twocapture,fourcompare).

•Safe 16-bit read/write via shadow registers.

8.19.1CCU clock

TheCCUrunsontheCCUCLK,whichiseitherPCLKinbasictimermode,ortheoutputofaPhase-LockedLoop(PLL).ThePLLisdesignedtouseaclocksourcebetween0.5MHzto 1MHz that is multiplied by 32 to produce a CCUCLK between 16MHz and 32MHz inPWMmode(asymmetricalorsymmetrical).ThePLLcontainsa4-bitdividertohelpdividePCLK into a frequency between 0.5MHz and 1MHz.

8.19.2CCUCLK prescaling

This CCUCLK can further be divided down by a prescaler. The prescaler is implementedas a 10-bit free-running counter with programmable reload at overﬂow.

8.19.3Basic timer operation

The timer is a free-running up/down counter with a direction control bit. If the timercounting direction is changed while the counter is running, the count sequence will bereversed. The timer can be written or read at any time.

Whenareloadoccurs,theCCUTimerOverﬂowInterruptFlagwillbeset,andaninterruptgenerated if enabled. The 16-bit CCU timer may also be used as an 8-bit up/down timer.

8.19.4Output compare

There are four output compare channels A, B, C and D. Each output compare channelneeds to be enabled in order to operate and the user will have to set the associated I/Opintothedesiredoutputmodetoconnectthepin.Whenthecontentsofthetimermatchesthat of a capture compare control register, the Timer Output Compare Interrupt Flag(TOCFx) becomes set. An interrupt will occur if enabled.

8.19.5Input capture

Inputcaptureisalwaysenabled.Eachtimeacaptureeventoccursononeofthetwoinputcapture pins, the contents of the timer is transferred to the corresponding 16-bit inputcapture register. The capture event can be programmed to be either rising or falling edgetriggered. A simple noise ﬁlter can be enabled on the input capture by enabling the Input

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CaptureNoiseFilterbit.Ifset,thecapturelogicneedstoseefourconsecutivesamplesofthesamevalueinordertorecognizeanedgeasacaptureevent.Aneventcountercanbeset to delay a capture by a number of capture events.

8.19.6PWM operation

PWM operation has two main modes, symmetrical and asymmetrical.

In asymmetrical PWM operation the CCU timer operates in down-counting moderegardless of the direction control bit.

In symmetrical mode, the timer counts up/down alternately. The main difference frombasic timer operation is the operation of the compare module, which in PWM mode isused for PWM waveform generation.

As with basic timer operation, when the PWM (compare) pins are connected to thecompare logic, their logic state remains unchanged. However, since bit FCO is used tohold the halt value, only a compare event can change the state of the pin.

TOR2compare valuetimer value0x0000non-invertedinverted002aaa893Fig 10.Asymmetrical PWM, down-counting modeTOR2compare valuetimer value0non-invertedinverted002aaa894Fig 11.Symmetrical PWMP89LPC933_934_935_936_7© NXP B.V. 2008. All rights reserved.

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8.19.7Alternating output mode

In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternatingpairs for bridge drive control. In this mode the output of these PWM channels arealternately gated on every counter cycle.

TOR2COMPARE VALUE A (or C)COMPARE VALUE B (or D)TIMER VALUE0PWM OUTPUT (OCA or OCC)PWM OUTPUT (OCB or OCD)002aaa895Fig 12.Alternate output mode8.19.8PLL operation

The PWM module features a PLL that can be used to generate a CCUCLK frequencybetween 16MHz and 32MHz. At this frequency the PWM module provides ultrasonicPWM frequency with 10-bit resolution provided that the crystal frequency is 1MHz orhigher. The PLL is fed an input signal from 0.5MHz to 1MHz and generates an outputsignal of 32times the input frequency. This signal is used to clock the timer. The user willhavetosetadividerthatscalesPCLKbyafactorfrom1to16.ThisdividerisfoundintheSFR register TCR21. The PLL frequency can be expressed as shown inEquation1.PCLK

PLL frequency=------------------(N+1)

Where: N is the value of PLLDV.3 to PLLDV.0.

(1)

Since N ranges from 0to15, the CCLK frequency can be in the range of PCLK toPCLK⁄16.

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8.19.9CCU interrupts

There are seven interrupt sources on the CCU which share a common interrupt vector.

EA (IEN0.7)ECCU (IEN1.4)TOIE2 (TICR2.7)TOIF2 (TIFR2.7)TICIE2A (TICR2.0)TICF2A (TIFR2.0)TICIE2B (TICR2.1)TICF2B (TIFR2.1)TOCIE2A (TICR2.3)TOCF2A (TIFR2.3)TOCIE2B (TICR2.4)TOCF2B (TIFR2.4)TOCIE2C (TICR2.5)TOCF2C (TIFR2.5)TOCIE2D (TICR2.6)TOCF2D (TIFR2.6)interrupt toCPUotherinterruptsourcesENCINT.0PRIORITYENCODERENCINT.1ENCINT.2002aaa896Fig 13.Capture/compare unit interrupts8.20UART

TheP89LPC933/934/935/936 has an enhanced UART that is compatible with the

conventional 80C51 UART except that Timer2 overﬂow cannot be used as a baud ratesource. TheP89LPC933/934/935/936 does include an independent baud rate generator.The baud rate can be selected from the oscillator (divided by a constant), Timer1

overﬂow, or the independent baud rate generator. In addition to the baud rate generation,enhancements over the standard 80C51 UART include Framing Error detection,

automatic address recognition, selectable double buffering and several interrupt options.TheUARTcanbeoperatedinfourmodes:shiftregister,8-bitUART,9-bitUART,andCPUclock⁄ or CPUclock⁄.3216

8.20.1Mode0

Serial data enters and exits through RXD. TXD outputs the shift clock. 8bits aretransmitted or received, LSB ﬁrst. The baud rate is ﬁxed at1⁄16 of the CPU clockfrequency.

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8.20.2Mode1

10bits are transmitted (through TXD) or received (through RXD): a start bit (logic0),

8databits(LSBﬁrst),andastopbit(logic1).Whendataisreceived,thestopbitisstoredin RB8 in special function register SCON. The baud rate is variable and is determined bythe Timer1 overﬂow rate or the baud rate generator (described inSection 8.20.5 “Baudrate generator and selection”).

8.20.3Mode2

11bitsaretransmitted(throughTXD)orreceived(throughRXD):startbit(logic0),8databits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logic1). When data is

transmitted,the9thdatabit(TB8inSCON)canbeassignedthevalueoflogic0orlogic1.Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data isreceived, the 9th data bit goes into RB8 in special function register SCON, while the stopbit is not saved. The baud rate is programmable to either1⁄16 or1⁄32 of the CPU clockfrequency, as determined by the SMOD1 bit in PCON.

8.20.4Mode3

11bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8databits(LSBﬁrst),aprogrammable9thdatabit,andastopbit(logic1).Infact,Mode3isthesameasMode2inallrespectsexceptbaudrate.ThebaudrateinMode3isvariableand is determined by the Timer1 overﬂow rate or the baud rate generator (described inSection 8.20.5 “Baud rate generator and selection”).

8.20.5Baud rate generator and selection

TheP89LPC933/934/935/936 enhanced UART has an independent baud rate generator.Thebaudrateisdeterminedbyabaud-ratepreprogrammedintotheBRGR1andBRGR0SFRs which together form a 16-bit baud rate divisor value that works in a similar manneras Timer1 but is much more accurate. If the baud rate generator is used, Timer1 can beused for other timing functions.

TheUARTcanuseeitherTimer1orthebaudrategeneratoroutput(seeFigure14).Notethat TimerT1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. Theindependent baud rate generator uses CCLK.

timer 1 overflow(PCLK-based)÷2baud rate generator(CCLK-based)SMOD1 = 1SMOD1 = 0SBRGS = 0baud rate modes 1 and 3SBRGS = 1002aaa897Fig 14.Baud rate sources for UART (Modes1,3)8.20.6Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)is logic1, framing errors can be made available in SCON.7 respectively. If SMOD0 islogic0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set upwhen SMOD0 is logic 0.

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8.20.7Break detect

Break detect is reported in the status register (SSTAT). A break is detected when

11consecutive bits are sensed LOW. The break detect can be used to reset the deviceand force the device into ISP mode.

8.20.8Double buffering

The UART has a transmit double buffer that allows buffering of the next character to bewritten to SBUF while the ﬁrst character is being transmitted. Double buffering allowstransmission of a string of characters with only one stop bit between any two characters,as long as the next character is written between the start bit and the stop bit of theprevious character.

Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7=0), the UART iscompatible with the conventional 80C51 UART. If enabled, the UART allows writing toSnBUF while the previous data is being shifted out. Double buffering is only allowed inModes1,2 and 3. When operated in Mode0, double buffering must be disabled(DBMOD=0).

8.20.9Transmit interrupts with double buffering enabled (modes1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the Tx interrupt is generatedwhen the double buffer is ready to receive new data.

8.20.10The 9th bit (bit8) in double buffering (modes1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as longasTB8isupdatedsometimebeforethatbitisshiftedout.TB8mustnotbechangeduntilthe bit is shifted out, as indicated by the Tx interrupt.

If double buffering is enabled, TB8must be updated before SBUF is written, as TB8 willbe double-buffered together with SBUF data.

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8.21I2C-bus serial interface

The I2C-bus uses two wires (SDA and SCL) to transfer information between devicesconnected to the bus, and it has the following features:

•Bidirectional data transfer between masters and slaves•Multi master bus (no central master)

•Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus

•Serialclocksynchronizationallowsdeviceswithdifferentbitratestocommunicatevia

one serial bus

•Serialclocksynchronizationcanbeusedasahandshakemechanismtosuspendand

resume serial transfer

•The I2C-bus may be used for test and diagnostic purposes.

A typical I2C-bus conﬁguration is shown inFigure15. TheP89LPC933/934/935/936device provides a byte-oriented I2C-bus interface that supports data transfers up to400kHz.

RPRPSDAI2C-busSCLP1.3/SDAP1.2/SCLOTHER DEVICEWITH I2C-BUSINTERFACEOTHER DEVICEWITH I2C-BUSINTERFACE002aab082P89LPC935Fig 15.I2C-bus conﬁgurationP89LPC933_934_935_936_7© NXP B.V. 2008. All rights reserved.

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8ADDRESS REGISTERP1.3I2ADRCOMPARATORINPUTFILTERP1.3/SDAOUTPUTSTAGESHIFT REGISTER8ACKI2DATINPUTFILTERP1.2/SCLOUTPUTSTAGEtimer 1overflowP1.2I2CONI2SCLHI2SCLLSERIAL CLOCKGENERATORTIMINGANDCONTROLLOGICinterruptCONTROL REGISTERS ANDSCL DUTY CYCLE REGISTERS8status busSTATUSDECODERI2STATSTATUS REGISTER8002aaa899Fig 16.I2C-bus serial interface block diagramP89LPC933_934_935_936_7© NXP B.V. 2008. All rights reserved.

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8.22SPI

TheP89LPC933/934/935/936 provides another high-speed serial communication

interface—theSPIinterface.SPIisafull-duplex,high-speed,synchronouscommunicationbus with two operation modes: Master mode and Slave mode. Up to 3Mbit/s can besupported in Master mode or up to 2Mbit/s in Slave mode. It has a Transfer CompletionFlag and Write Collision Flag Protection.

SPI clock (master)SELECTSPR1SPR0clockCLOCK LOGICSMMSTRDORDMSTRCPHASPENCPOLSPR1SPI CONTROL REGISTERinternaldatabusSPI CONTROLWCOLSPIFMSTRSPENSPR0SSIGSPIinterruptrequestSPI STATUS REGISTERFig 17.SPI block diagramThe SPI interface has four pins: SPICLK, MOSI, MISO andSS:•SPICLK, MOSI and MISO are typically tied together between two or more SPI

devices.DataﬂowsfrommastertoslaveonMOSI(MasterOutSlaveIn)pinandﬂowsfromslavetomasteronMISO(MasterInSlaveOut)pin.TheSPICLKsignalisoutputin the master mode and is input in the slave mode. If the SPI system is disabled, i.e.,SPEN (SPCTL.6)=0 (reset value), these pins are conﬁgured for port functions.

•SS is the optional slave select pin. In a typical conﬁguration, an SPI master assertsoneofitsportpinstoselectoneSPIdeviceasthecurrentslave.AnSPIslavedeviceuses itsSS pin to determine whether it is selected.Typical connections are shown inFigure18throughFigure20.

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8.22.1Typical SPI conﬁgurations

masterMISO8-BIT SHIFTREGISTERMOSIMISOMOSIslave8-BIT SHIFTREGISTERSPICLKSPI CLOCKGENERATORPORTSPICLKSS002aaa901Fig 18.SPI single master single slave conﬁgurationmasterMISO8-BIT SHIFTREGISTERMOSIMISOMOSIslave8-BIT SHIFTREGISTERSPICLKSPI CLOCKGENERATORSSSPICLKSSSPI CLOCKGENERATOR002aaa902Fig 19.SPI dual device conﬁguration, where either can be a master or a slaveP89LPC933_934_935_936_7© NXP B.V. 2008. All rights reserved.

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masterMISO8-BIT SHIFTREGISTERMOSIMISOMOSIslave8-BIT SHIFTREGISTERSPICLKSPI CLOCKGENERATORportSPICLKSSslaveMISOMOSI8-BIT SHIFTREGISTERSPICLKportSS002aaa903Fig 20.SPI single master multiple slaves conﬁgurationP89LPC933_934_935_936_7© NXP B.V. 2008. All rights reserved.

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8.23Analog comparators

Two analog comparators are provided on theP89LPC933/934/935/936. Input and outputoptions allow use of the comparators in a number of different conﬁgurations. Comparatoroperationissuchthattheoutputisalogic1(whichmaybereadinaregisterand/orroutedto a pin) when the positive input (one of two selectable pins) is greater than the negativeinput (selectable from a pin or an internal reference voltage). Otherwise the output is azero. Each comparator may be conﬁgured to cause an interrupt when the output valuechanges.

The overall connections to both comparators are shown inFigure21. The comparatorsfunction to VDD=2.4V.

When each comparator is ﬁrst enabled, the comparator output and interrupt ﬂag are notguaranteed to be stable for 10microseconds. The corresponding comparator interruptshouldnotbeenabledduringthattime,andthecomparatorinterruptﬂagmustbeclearedbefore the interrupt is enabled in order to prevent an immediate interrupt service.When a comparator is disabled the comparator’s output, COn, goes HIGH. If thecomparator output was LOW and then is disabled, the resulting transition of the

comparatoroutputfromaLOWtoHIGHstatewillsetthecomparatorﬂag,CMFn.Thiswillcause an interrupt if the comparator interrupt is enabled. The user should thereforedisable the comparator interrupt prior to disabling the comparator. Additionally, the usershould clear the comparator ﬂag, CMFn, after disabling the comparator.

CP1(P0.4) CIN1A(P0.3) CIN1B(P0.5) CMPREFVref(bg)CN1change detectCMF1comparator 1CO1OE1CMP1 (P0.6)interruptCP2(P0.2) CIN2A(P0.1) CIN2BCO2OE2CN2002aaa904change detectCMF2comparator 2CMP2 (P0.0)ECFig 21.Comparator input and output connections8.23.1Internal reference voltage

An internal reference voltage generator may supply a default reference when a singlecomparator input pin is used. The value of the internal reference voltage, referred to asVref(bg), is 1.23V±10%.

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8.23.2Comparator interrupt

Each comparator has an interrupt ﬂag contained in its conﬁguration register. This ﬂag issetwheneverthecomparatoroutputchangesstate.Theﬂagmaybepolledbysoftwareormay be used to generate an interrupt. The two comparators use one common interruptvector. If both comparators enable interrupts, after entering the interrupt service routine,the user needs to read the ﬂags to determine which comparator caused the interrupt.

8.23.3Comparators and power reduction modes

Either or both comparators may remain enabled when Power-down or Idle mode isactivated, but both comparators are disabled automatically in Total Power-down mode.If a comparator interrupt is enabled (except in Total Power-down mode), a change of thecomparator output state will generate an interrupt and wake-up the processor. If the

comparatoroutputtoapinisenabled,thepinshouldbeconﬁguredinthepush-pullmodein order to obtain fast switching times while in Power-down mode. The reason is that withtheoscillatorstopped,thetemporarystrongpull-upthatnormallyoccursduringswitchingon a quasi-bidirectional port pin does not take place.

Comparators consume power in Power-down and Idle modes, as well as in the normaloperatingmode.Thisfactshouldbetakenintoaccountwhensystempowerconsumptionis an issue. To minimize power consumption, the user can disable the comparators viaPCONA.5, or put the device in Total Power-down mode.

8.24Keypad interrupt

The Keypad Interrupt (KBI) function is intended primarily to allow a single interrupt to begenerated when Port0 is equal to or not equal to a certain pattern. This function can beused for bus address recognition or keypad recognition. The user can conﬁgure the portvia SFRs for different tasks.

The Keypad Interrupt Mask register (KBMASK) is used to deﬁne which input pins

connected to Port0 can trigger the interrupt. The Keypad Pattern register (KBPATN) isusedtodeﬁneapatternthatiscomparedtothevalueofPort0.TheKeypadInterruptFlag(KBIF) in the Keypad Interrupt Control register (KBCON) is set when the condition ismatched while the Keypad Interrupt function is active. An interrupt will be generated ifenabled. The PATN_SEL bit in the Keypad Interrupt Control register (KBCON) is used todeﬁne equal or not-equal for the comparison.

In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series,the user needs to set KBPATN=0FFH and PATN_SEL=1 (not equal), then any key

connected to Port0 which is enabled by the KBMASK register will cause the hardware toset KBIF and generate an interrupt if it has been enabled. The interrupt may be used towake-up the CPU from Idle or Power-down modes. This feature is particularly useful inhandheld, battery-powered systems that need to carefully manage power consumptionyet also need to be convenient to use.

In order to set the ﬂag and cause an interrupt, the pattern on Port0 must be held longerthan sixCCLKs.

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8.25Watchdog timer

The watchdog timer causes a system reset when it underﬂows as a result of a failure tofeedthetimerpriortothetimerreachingitsterminalcount.Itconsistsofaprogrammable12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a taptaken from the prescaler. The clock source for the prescaler is either the PCLK or thenominal 400kHz watchdog oscillator. The watchdog timer can only be reset by a

power-onreset.Whenthewatchdogfeatureisdisabled,itcanbeusedasanintervaltimerand may generate an interrupt.Figure22 shows the watchdog timer in Watchdog mode.Feedingthewatchdogrequiresatwo-bytesequence.IfPCLKisselectedasthewatchdogclockandtheCPUispowered-down,thewatchdogisdisabled.Thewatchdogtimerhasatime-out period that ranges from a fewµs to a few seconds. Please refer to theP89LPC933/934/935/936 User manual for more details.

WDL (C1H)MOV WFEED1, #0A5HMOV WFEED2, #05AHwatchdogoscillatorPCLK÷32PRESCALER8-BIT DOWN COUNTERreset(1)SHADOW REGISTERWDCON (A7H)PRE2PRE1PRE0--WDRUNWDTOFWDCLK002aaa905(1)Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feedsequence.Fig 22.Watchdog timer in Watchdog mode (WDTE=1)8.26Additional features

8.26.1Software reset

TheSRSTbitinAUXR1givessoftwaretheopportunitytoresettheprocessorcompletely,asifanexternalresetorwatchdogresethadoccurred.Careshouldbetakenwhenwritingto AUXR1 to avoid accidental software resets.

8.26.2Dual data pointers

ThedualDataPointers(DPTR)providestwodifferentDataPointerstospecifytheaddressused with certain instructions. The DPS bit in the AUXR1 register selects one of the twoData Pointers. Bit2 of AUXR1 is permanently wired as a logic0 so that the DPS bit maybe toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,without the possibility of inadvertently altering other bits in the register.

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8.27Data EEPROM (P89LPC935/936)

The P89LPC935/936 has 512bytes of on-chip Data EEPROM. The Data EEPROM isSFR based, byte readable, byte writable, and erasable (via row ﬁll and sector ﬁll). Theuser can read, write and ﬁll the memory via SFRs and one interrupt. This Data EEPROMprovides 100,000 minimum erase/program cycles for each byte.

•Byte mode: In this mode, data can be read and written one byte at a time.

•Row ﬁll: In this mode, the addressed row (64bytes) is ﬁlled with a single value. The

entire row can be erased by writing 00H.

•Sector ﬁll: In this mode, all 512bytes are ﬁlled with a single value. The entire sector

can be erased by writing 00H.

After the operation ﬁnishes, the hardware will set the EEIF bit, which if enabled willgenerate an interrupt. The ﬂag is cleared by software.

8.28Flash program memory

8.28.1General description

TheP89LPC933/934/935/936 ﬂash memory provides in-circuit electrical erasure andprogramming. The ﬂash can be erased, read, and written as bytes. The Sector and PageErase functions can erase any ﬂash sector (1kB or 2 kB depending on the device) orpage (64bytes). The Chip Erase operation will erase the entire program memory. ICPusing standard commercial programmers is available. In addition, IAP and byte-eraseallows code memory to be used for non-volatile data storage. On-chip erase and writetiming generation contribute to a user-friendly programming interface. The

P89LPC933/934/935/936ﬂashreliablystoresmemorycontentsevenafter100,000eraseand program cycles. The cell is designed to optimize the erase and programming

mechanisms. TheP89LPC933/934/935/936 uses VDD as the supply voltage to performthe Program/Erase algorithms.

8.28.2Features

•••••

Programming and erase over the full operating voltage range.Byte erase allows code memory to be used for data storage.Read/Programming/Erase using ISP/IAP/ICP.

Internal ﬁxed boot ROM, containing low-level IAP routines available to user code.Default loader providing ISP via the serial port, located in upper end of user programmemory.

memory space, providing ﬂexibility to the user.

•Boot vector allows user-provided ﬂash loader code to reside anywhere in the ﬂash•••••

Any ﬂash program/erase operation in 2ms.

Programming with industry-standard commercial programmers.Programmable security for the code in the ﬂash for each sector.100,000 typical erase/program cycles for each byte.10year minimum data retention.

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8.28.3Flash organization

Theprogrammemoryconsistsofeight2kBsectorsontheP89LPC936device,eight1kBsectorsontheP89LPC934/935devices,andfour1kBsectorsontheP89LPC933device.Each sector can be further divided into 64-byte pages. In addition to sector erase, pageerase,andbyteerase,a64-bytepageregisterisincludedwhichallowsfrom1to64bytesof a given page to be programmed at the same time, substantially reducing overallprogramming time.

8.28.4Using ﬂash as data storage

The ﬂash code memory array of this device supports individual byte erasing andprogramming. Any byte in the code memory array may be read using the MOVC

instruction, provided that the sector containing the byte has not been secured (a MOVCinstruction is not allowed to read code memory contents of a secured sector). Thus anybyte in a non-secured sector may be used for non-volatile data storage.

8.28.5Flash programming and erasing

Fourdifferentmethodsoferasingorprogrammingoftheﬂashareavailable.Theﬂashmaybe programmed or erased in the end-user application (IAP) under control of the

application’s ﬁrmware. Another option is to use the ICP mechanism. This ICP systemprovides for programming through a serial clock - serial data interface. As shipped fromthefactory,theupper512bytesofusercodespacecontainsaserialISProutineallowingthe device to be programmed in circuit through the serial port. The ﬂash may also beprogrammed or erased using a commercially available EPROM programmer which

supports this device. This device does not provide for direct veriﬁcation of code memorycontents.Instead,thisdeviceprovidesa32-bitCRCresultoneitherasectorortheentireuser code space.

8.28.6In-circuit programming

ICP is performed without removing the microcontroller from the system. The ICP facilityconsists of internal hardware resources to facilitate remote programming of the

P89LPC933/934/935/936 through a two-wire serial interface. The Philips ICP facility hasmade ICP in an embedded application—using commercially available

programmers—possible with a minimum of additional expense in components and circuitboardarea.TheICPfunctionusesﬁvepins.Onlyasmallconnectorneedstobeavailableto interface your application to a commercial programmer in order to use this feature.Additional details may be found in theP89LPC933/934/935/936 User manual.

8.28.7In-application programming

IAPisperformedintheapplicationunderthecontrolofthemicrocontroller’sﬁrmware.TheIAPfacilityconsistsofinternalhardwareresourcestofacilitateprogramminganderasing.The Philips IAP has made IAP in an embedded application possible without additionalcomponents. Two methods are available to accomplish IAP. A set of predeﬁned IAPfunctions are provided in a bootROM and can be called through a common interface,PGM_MTP. Several IAP calls are available for use by an application program to permitselective erasing and programming of ﬂash sectors, pages, security bits, conﬁgurationbytes, and device ID. These functions are selected by setting up the microcontroller’sregisters before making a call to PGM_MTP at FF03H. The bootROM occupies theprogram memory space at the top of the address space from FF00H to FFEFH, therebynot conﬂicting with the user program memory space.

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In addition, IAP operations can be accomplished through the use of four SFRs consistingof a control/status register, a data register, and two address registers. Additional detailsmay be found in theP89LPC933/934/935/936 User manual.

8.28.8ISP

ISP is performed without removing the microcontroller from the system. The ISP facilityconsists of a series of internal hardware resources coupled with internal ﬁrmware tofacilitate remote programming of theP89LPC933/934/935/936 through the serial port.ThisﬁrmwareisprovidedbyPhilipsandembeddedwithineachP89LPC933/934/935/936device. The Philips ISP facility has made ISP in an embedded application possible with aminimum of additional expense in components and circuit board area. The ISP functionuses ﬁve pins (VDD, VSS, TXD, RXD, andRST). Only a small connector needs to beavailable to interface your application to an external circuit in order to use this feature.

8.28.9Power-on reset code execution

TheP89LPC933/934/935/936 contains two special ﬂash elements: the boot vector andthe boot status bit. Following reset, theP89LPC933/934/935/936 examines the contentsof the boot status bit. If the boot status bit is set to zero, power-up execution starts atlocation 0000H, which is the normal start address of the user’s application code. Whenthe boot status bit is set to a value other than zero, the contents of the boot vector areused as the high byte of the execution address and the low byte is set to 00H.Table9 shows the factory default bootvector settings for these devices.

Remark:These settings are different than the original P89LPC932. Tools designed tosupport theP89LPC933/934/935/936 should be used to program this device, such asFlash Magic version 1.98, or later.

A factory-provided boot loader is preprogrammed into the address space indicated anduses the indicated bootloader entry point to perform ISP functions. This code can beerased by the user.

Remark:Users who wish to use this loader should take precautions to avoid erasing thesector that contains this bootloader. Instead, the page erase function can be used toerase the pages located in this sector which are not used by the boot loader.

A custom boot loader can be written with the bootvector set to the custom bootloader, ifdesired.

Table 9.DeviceDefault boot vector values and ISP entry points

Defaultbootvector0FH1FH1FH3FH

Defaultbootloaderentry point0F00H1F00H1F00H3F00H

DefaultbootloaderBoot sectorcode rangerange0E00H to 0FFFH1E00H to 1FFFH1E00H to 1FFFH3E00H to 3FFFH

0C00H to 0FFFH1C00H to 1FFFH1C00H to 1FFFH3C00H to 3FFFH

P89LPC933P89LPC934P89LPC935P89LPC936

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8.28.10Hardware activation of the boot loader

The boot loader can also be executed by forcing the device into ISP mode during apower-on sequence (see theP89LPC933/934/935/936 User manual for speciﬁc

information). This has the same effect as having a non-zero status byte. This allows anapplicationtobebuiltthatwillnormallyexecuteusercodebutcanbemanuallyforcedintoISP operation. If the factory default setting for the boot vector is changed, it will no longerpoint to the factory preprogrammed ISP boot loader code. After programming the ﬂash,the status byte should be programmed to zero in order to allow execution of the user’sapplication code beginning at address 0000H.

8.29User conﬁguration bytes

Some user-conﬁgurable features of theP89LPC933/934/935/936 must be deﬁned atpower-up and therefore cannot be set by the program after start of execution. Thesefeatures are conﬁgured through the use of the ﬂash byte UCFG1. Please see theP89LPC933/934/935/936 User manual for additional details.

8.30User sector security bytes

ThereareeightUserSectorSecurityBytesontheP89LPC933/934/935/936device.Eachbytecorrespondstoonesector.PleaseseetheP89LPC933/934/935/936Usermanualforadditional details.

9.A/D converter

9.1General description

The P89LPC935/936 have two 8-bit, 4-channel multiplexed successive approximationanalog-to-digital converter modules sharing common control logic. The P89LPC933/934have a single 8-bit, 4-channel multiplexed analog-to-digital converter and an additionalDAC module. Ablock diagram of the A/D converter is shown inFigure23. Each A/D

consists of a 4-input multiplexer which feeds a sample-and-hold circuit providing an inputsignal to one of two comparator inputs. The control logic in combination with the SARdrives a digital-to-analog converter which provides the other input to the comparator. Theoutput of the comparator is fed to the SAR.

9.2Features

ITwo (P89LPC935/936) 8-bit, 4-channel multiplexed input, successive approximationA/D converters with common control logic (one A/D on the P89LPC933/934).IFour result registers for each A/D.ISix operating modes:

NFixed channel, single conversion mode.

NFixed channel, continuous conversion mode.NAuto scan, single conversion mode.

NAuto scan, continuous conversion mode.NDual channel, continuous conversion mode.NSingle step mode.

IFour conversion start modes:

NTimer triggered start.

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IIIIII

NStart immediately.NEdge triggered.

NDual start immediately (P89LPC935/936).

8-bit conversion time of≥3.9µs at an A/D clock of 3.3 MHz.Interrupt or polled operation.Boundary limits interrupt.

DAC output to a port pin with high output impedance.Clock divider.

Power-down mode.

9.3Block diagram

compINPUTMUX+SAR–DAC18compINPUTMUX+SAR–CONTROLLOGICDAC08CCLK002aab080Fig 23.ADC block diagram9.4A/D operating modes

9.4.1Fixed channel, single conversion mode

A single input channel can be selected for conversion. A single conversion will be

performed and the result placed in the result register which corresponds to the selectedinput channel. An interrupt, if enabled, will be generated after the conversion completes.

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9.4.2Fixed channel, continuous conversion mode

A single input channel can be selected for continuous conversion. The results of the

conversionswillbesequentiallyplacedinthefourresultregisters.Aninterrupt,ifenabled,will be generated after every four conversions. Additional conversion results will againcycle through the four result registers, overwriting the previous results. Continuousconversions continue until terminated by the user.

9.4.3Auto scan, single conversion mode

Any combination of the four input channels can be selected for conversion. A singleconversion of each selected input will be performed and the result placed in the resultregister which corresponds to the selected input channel. An interrupt, if enabled, will begenerated after all selected channels have been converted. If only a single channel isselected this is equivalent to single channel, single conversion mode.

9.4.4Auto scan, continuous conversion mode

Any combination of the four input channels can be selected for conversion. A conversionof each selected input will be performed and the result placed in the result register whichcorrespondstotheselectedinputchannel.Aninterrupt,ifenabled,willbegeneratedafterall selected channels have been converted. The process will repeat starting with the ﬁrstselected channel. Additional conversion results will again cycle through the four resultregisters,overwritingthepreviousresults.Continousconversionscontinueuntilterminatedby the user.

9.4.5Dual channel, continuous conversion mode

Thisisavariationoftheautoscancontinuousconversionmodewhereconversionoccursontwouser-selectableinputs.Theresultoftheconversionoftheﬁrstchannelisplacedinresult register, ADxDAT0. The result of the conversion of the second channel is placed inresult register, ADxDAT1. The ﬁrst channel is again converted and its result stored inADxDAT2. The second channel is again converted and its result placed in ADxDAT3. Aninterruptisgenerated,ifenabled,aftereverysetoffourconversions(twoconversionsperchannel).

9.4.6Single step mode

This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any

combinationofthefourinputchannelscanbeselectedforconversion.Aftereachchannelis converted, an interrupt is generated, if enabled, and the A/D waits for the next startcondition. May be used with any of the start modes.

9.5Conversion start modes

9.5.1Timer triggered start

An A/D conversion is started by the overﬂow of Timer0. Once a conversion has started,additional Timer0 triggers are ignored until the conversion has completed. The Timertriggered start mode is available in all A/D operating modes.

9.5.2Start immediately

Programmingthismodeimmediatelystartsaconversion.ThisstartmodeisavailableinallA/D operating modes.

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9.5.3Edge triggered

An A/D conversion is started by rising or falling edge of P1.4. Once a conversion hasstarted,additionaledgetriggersareignoreduntiltheconversionhascompleted.Theedgetriggered start mode is available in all A/D operating modes.

9.5.4Dual start immediately (P89LPC935/936)

Programming this mode starts a synchronized conversion of both A/D converters.Thisstart mode is available in all A/D operating modes. Both A/D converters must be in thesame operating mode. In the continuous conversion modes, both A/D converters mustselect an identical number of channels. Any trigger of either A/D will start a simultaneousconversion of both A/Ds.

9.6Boundary limits interrupt

Each of the A/D converters has both a high and low boundary limit register. After the fourMSBs have been converted, these four bits are compared with the four MSBs of theboundary high and low registers. If the four MSBs of the conversion are outside the limitan interrupt will be generated, if enabled. If the conversion result is within the limits, theboundary limits will again be compared after all 8bits have been converted. An interruptwillbegenerated,ifenabled,iftheresultisoutsidetheboundarylimits.Theboundarylimitmay be disabled by clearing the boundary limit interrupt enable.

9.7DAC output to a port pin with high output impedance

Each A/D converter’s DAC block can be output to a port pin. In this mode, the ADxDAT3registerisusedtoholdthevaluefedtotheDAC.AfteravaluehasbeenwrittentotheDAC(written to ADxDAT3), the DAC output will appear on the channel3 pin.

9.8Clock divider

The A/D converter requires that its internal clock source be in the range of 500kHz to3.3MHz to maintain accuracy. A programmable clock divider that divides the clockfrom1to8 is provided for this purpose.

9.9Power-down and Idle mode

In Idle mode the A/C converter, if enabled, will continue to function and can cause thedevice to exit Idle mode when the conversion is completed if the A/D interrupt is enabled.In Power-down mode or Total Power-down mode, the A/D does not function. If the A/D isenabled, it will consume power. Power can be reduced by disabling the A/D.

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10.Limiting values

Table 10.Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]SymbolTamb(bias)TstgIOH(I/O)IOL(I/O)II/O(tot)(max)VnPtot(pack)

Parameteroperating bias ambient temperaturestorage temperature range

HIGH-level output current per I/O pinLOW-level output current per I/O pinmaximum total I/O currentvoltage on any pin (except VSS)total power dissipation per package

with respect to VDDbased on package heattransfer, not device powerconsumptionConditionsMin−55−65-----Max+125+15020201003.51.5

Unit°C°CmAmAmAVW

[1]

The following applies toTable10:

a)This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessivestaticcharge.Nonetheless,itissuggestedthatconventionalprecautionsbetakentoavoidapplyinggreaterthantheratedmaximum.b)Parameters are valid over ambient temperature range unless otherwise speciﬁed. All voltages are with respect to VSS unlessotherwise noted.

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11.Static characteristics

Table 11.Static characteristics

VDD=2.4Vto3.6V unless otherwise speciﬁed.Tamb=−40°Cto+85°C for industrial,−40°Cto+125°C for extended, unless otherwise speciﬁed.SymbolIDD(oper)IDD(idle)IDD(pd)

Parameteroperating supply currentIdle mode supply currentpower supply current,

Power-down mode, voltagecomparators powered-downtotal Power-down mode supplycurrent

ConditionsVDD = 3.6V; fosc=12MHzVDD = 3.6V; fosc=18MHzVDD = 3.6V; fosc=12MHzVDD = 3.6V; fosc=18MHzVDD=3.6V

[2][2][2][2][2]

Min-----

Typ[1]11143.25555

Max18235780

UnitmAmAmAmAµA

IDD(tpd)

all devices exceptP89LPC933HDH;VDD=3.6V

P89LPC933HDH only;VDD=3.6V

[3]

-15µA

[3]

---1.50.22VDD−0.5-0.7VDD-

----0.4VDD-0.6VDD-0.2VDD0.6

25250--0.3VDD0.7VDD5.5-1.0

µAmV/µsmV/µsVVVVVVV

(dV/dt)r(dV/dt)fVDDRVth(HL)VILVth(LH)VIHVhysVOL

rise ratefall rate

data retention voltageHIGH-LOW threshold voltageLOW-level input voltageLOW-HIGH threshold voltageHIGH-level input voltagehysteresis voltageLOW-level output voltage

of VDDof VDD

except SCL, SDASCL, SDA onlyexcept SCL, SDASCL, SDA onlyport1

IOL=20mA;

VDD=2.4Vto 3.6V

allports, all modes excepthigh-Z

IOL=3.2mA; VDD=2.4Vto3.6Vallports,allmodesexcept high-Z

[4]

-0.20.3V

VOH

HIGH-level output voltage

IOH=−20µA;

VDD=2.4Vto 3.6V;allports,

quasi-bidirectionalmodeIOH=−3.2mA;

VDD=2.4Vto 3.6V;allports, push-pullmodeIOH=−10mA;VDD=3.6V;allports, push-pullmode

VDD−0.3VDD−0.2-V

VDD−0.7VDD−0.4-V

-−0.5

[5]

3.2-----

-+4.0+5.515−80±10

VVVpFµAµA

VxtalVnCissIILILI

voltage on XTAL1, XTAL2 pinsvoltage on any pin (exceptXTAL1, XTAL2, VDD)input capacitancelogical0 input currentinput leakage current

with respect to VSSwith respect to VSS

−0.5---

[6]

VI=0.4V

VI=VIL,VIH orVth(HL)

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Table 11.Static characteristics …continuedVDD=2.4Vto3.6V unless otherwise speciﬁed.Tamb=−40°Cto+85°C for industrial,−40°Cto+125°C for extended, unless otherwise speciﬁed.SymbolITLRRST(int)VboVref(bg)TCbg

[1][2][3][4][5]

Parameterlogical1-to-0 transition current,all ports

internal pull-up resistance onpinRSTbrownout trip voltageband gap reference voltageband gap temperaturecoefﬁcient

ConditionsVI=1.5V at VDD=3.6V[9]Min−3010

Typ[1]---1.2310

Max−450302.701.3420

UnitµAkΩVVppm/°C

2.4V2.401.11-

Typical ratings are not guaranteed. The values listed are at room temperature, 3V.

TheIDD(oper),IDD(idle),andIDD(pd)speciﬁcationsaremeasuredusinganexternalclockwiththefollowingfunctionsdisabled:comparators,real-time clock, and watchdog timer.

The IDD(tpd) speciﬁcation is measured using an external clock with the following functions disabled: comparators, real-time clock,brownout detect, and watchdog timer.

SeeSection 10 “Limiting values” for steady state (non-transient) limits on IOL or IOH. If IOL/IOH exceeds the test condition, VOL/VOH mayexceed the related speciﬁcation.

This speciﬁcation can be applied to pins which have A/D input or analog comparator input functions when the pin is not being used forthoseanalogfunctions.Whenthepinisbeingusedasananaloginputpin,themaximumvoltageonthepinmustbelimitedto4.0Vwithrespect to VSS.

Pin capacitance is characterized but not tested.Measured with port in quasi-bidirectional mode.Measured with port in high-impedance mode.

Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current ishighest when VI is approximately 2V.

[6][7][8][9]

11.1IOH as a function of VOH

40IOH30152010105002aab09825IOH20002aab09900123VOH40012VOH3a.Tamb = 25°C; VDD=3.6V; push-pull modeFig 24.IOH as a function of VOH (typical values)P89LPC933_934_935_936_7

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12.Dynamic characteristics

Table 12.Dynamic characteristics (12 MHz)VDD=2.4Vto3.6V unless otherwise speciﬁed.Tamb=−40°Cto+85°C for industrial,−40°Cto+125°C for extended, unless otherwise speciﬁed.[1][2]Symbolfosc(RC)fosc(WD)foscTcy(CLK)fCLKLPGlitch ﬁltertgr

glitch rejectionP1.5/RST pinany pin exceptP1.5/RSTtsa

signal acceptanceP1.5/RST pinany pin exceptP1.5/RSTExternal clocktCHCXtCLCXtCLCHtCHCLTXLXLtQVXHtXHQXtXHDXtXHDV

clock HIGH timeclock LOW timeclock rise timeclock fall timeserial port clock cycle timeoutput data setup to clock risingedge time

output data hold after clockrising edge time

input data hold after clock risingedge time

input data valid to clock risingedge time

SPI operating frequencyslavemaster

TSPICYC

SPI cycle timeslavemaster

tSPILEADtSPILAG

SPI enable lead time (slave)SPI enable lag time (slave)seeFigure29,30seeFigure29,30seeFigure26,28,29,30

0-6⁄CCLK4⁄CCLK

CCLK⁄CCLK⁄

Parameterinternal RC oscillator frequencyinternal watchdog oscillator

frequency

oscillator frequencyclock cycle timelow power select clockfrequency

ConditionsVariable clockMin7.1893200

Max7.55752012-8fosc=12MHzMin7.189320---MaxUnit7.557MHz520---kHzMHznsMHzseeFigure27830--12550

5015--

--12550

5015--

nsnsnsns

seeFigure27seeFigure27seeFigure27seeFigure27seeFigure25seeFigure25seeFigure25seeFigure25seeFigure25

3333--16Tcy(CLK)13Tcy(CLK)

--150

Tcy(CLK)−tCLCXTcy(CLK)−tCHCX88--Tcy(CLK)+20

3333--13331083--150

--88--1030-

nsnsnsnsnsnsnsnsns

Shift register (UART mode0)SPI interfacefSPI

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Table 12.Dynamic characteristics (12 MHz) …continuedVDD=2.4Vto3.6V unless otherwise speciﬁed.Tamb=−40°Cto+85°C for industrial,−40°Cto+125°C for extended, unless otherwise speciﬁed.[1][2]SymboltSPICLKH

ParameterSPICLK HIGH timemasterslave

tSPICLKL

SPICLK LOW timemasterslave

tSPIDSUtSPIDHtSPIAtSPIDIStSPIDV

SPI data setup time (master orslave)SPI data hold time (master orslave)SPI access time (slave)SPI disable time (slave)SPI enable to output data validtimeslavemaster

tSPIOHtSPIR

SPI output data hold timeSPI rise timeSPI outputs

(SPICLK,MOSI,MISO)SPI inputs

(SPICLK,MOSI,MISO,SS)tSPIF

SPI fall time

SPI outputs

(SPICLK,MOSI,MISO)SPI inputs

(SPICLK,MOSI,MISO,SS)[1][2]

ConditionsseeFigure26,28,29,30

Variable clockMin2⁄CCLK3⁄CCLK

fosc=12MHzMin1652501652501001000-Max------120240UnitMax------120240nsnsnsnsnsnsnsnsseeFigure26,28,

29,30

2⁄CCLK3⁄CCLK

seeFigure26,28,

29,30seeFigure26,28,29,30seeFigure29,30seeFigure29,30seeFigure26,28,29,30

10010000--seeFigure26,28,29,30seeFigure26,28,29,30

240167-

--0

240167-

nsnsns

1002000

nsns

seeFigure26,28,29,30

1002000

nsns

Parameters are valid over ambient temperature range unless otherwise speciﬁed.Parts are tested to 2MHz, but are guaranteed to operate down to 0Hz.

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Table 13.Dynamic characteristics (18 MHz)VDD=3.0Vto3.6V unless otherwise speciﬁed.Tamb=−40°Cto+85°C for industrial,−40°Cto+125°C for extended, unless otherwise speciﬁed.[1][2]Symbolfosc(RC)fosc(WD)foscTcy(CLK)fCLKLPGlitch ﬁltertgr

glitch rejectionP1.5/RST pinany pin exceptP1.5/RSTtsa

signal acceptanceP1.5/RST pinany pin exceptP1.5/RSTExternal clocktCHCXtCLCXtCLCHtCHCLTXLXLtQVXHtXHQXtXHDXtXHDV

clock HIGH timeclock LOW timeclock rise timeclock fall timeserial port clock cycle timeseeFigure27seeFigure27seeFigure27seeFigure27seeFigure252222--16Tcy(CLK)13Tcy(CLK)

--150

Tcy(CLK)−tCLCXTcy(CLK)−tCHCX55--Tcy(CLK)+20

0-2222--888722--150

--55--750-nsnsnsnsnsnsnsnsns

--12550

5015----12550

5015--nsnsnsns

Parameterinternal RC oscillator frequencyinternal watchdog oscillatorfrequency

oscillator frequencyclock cyclelow power select clockfrequency

seeFigure27ConditionsVariable clockMin7.1893200550Max7.55752018-8fosc=18MHzUnitMin7.189320---Max7.557MHz520---kHzMHznsMHzShift register (UART mode0)outputdatasetuptoclockrisingseeFigure25edge time

output data hold after clockrising edge time

seeFigure25

inputdataholdafterclockrisingseeFigure25edge time

input data valid to clock risingedge time

SPI operating frequencyslavemaster

seeFigure25

SPI interfacefSPI

0-seeFigure26,28,29,30

6⁄4⁄

CCLK⁄6CCLK⁄4

0-3332222502503.04.5----MHzMHznsnsnsnsTSPICYC

SPI cycle timeslavemaster

CCLKCCLK

----tSPILEADtSPILAG

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Table 13.Dynamic characteristics (18 MHz) …continuedVDD=3.0Vto3.6V unless otherwise speciﬁed.Tamb=−40°Cto+85°C for industrial,−40°Cto+125°C for extended, unless otherwise speciﬁed.[1][2]SymboltSPICLKH

ParameterSPICLK HIGH timemasterslave

tSPICLKL

SPICLK LOW timemasterslave

tSPIDSUtSPIDHtSPIAtSPIDIStSPIDV

SPI data setup time (master orslave)SPI data hold time (master orslave)SPI access time (slave)SPI disable time (slave)SPI enable to output data validtimeslavemaster

tSPIOHtSPIR

SPI output data hold timeSPI rise timeSPI outputs

(SPICLK,MOSI,MISO)SPI inputs

(SPICLK,MOSI,MISO,SS)tSPIF

SPI fall time

SPI outputs

(SPICLK,MOSI,MISO)SPI inputs

(SPICLK,MOSI,MISO,SS)[1][2]

Parameters are valid over ambient temperature range unless otherwise speciﬁed.Parts are tested to 2MHz, but are guaranteed to operate down to 0Hz.

ConditionsseeFigure26,28,29,30

Variable clockMin2⁄3⁄

fosc=18MHzUnitMin1111671111671001000-Max------80160nsnsnsnsnsnsnsnsMax------80160CCLKCCLK

seeFigure26,28,29,30

2⁄3⁄

CCLKCCLK

seeFigure26,28,29,30seeFigure26,28,29,30seeFigure29,30seeFigure29,30seeFigure26,28,29,30

10010000--seeFigure26,28,29,30seeFigure26,28,29,30

160111-

--0

160111-

nsnsns

1002000

nsns

seeFigure26,28,29,30

1002000

nsns

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12.1Waveforms

TXLXLclocktQVXHoutput data0write to SBUFinput dataclear RIset RI002aaa906tXHQX1tXHDXvalidvalidvalidvalidvalidvalidvalid234567set TIvalidtXHDVFig 25.Shift register mode timingSSTSPICYCtSPICLKLtSPIFSPICLK(CPOL = 0)(output)tSPIFtSPIRtSPICLKHtSPICLKLtSPIRtSPICLKHSPICLK(CPOL = 1)(output)tSPIDSUMISO(input)tSPIDHLSB/MSB intSPIOHtSPIDVtSPIRMSB/LSB intSPIDVMOSI(output)tSPIFmaster MSB/LSB outmaster LSB/MSB out002aaa908Fig 26.SPI master timing (CPHA=0)tCHCLtCLCXTcy(clk)tCHCXtCLCH002aaa907Fig 27.External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)P89LPC933_934_935_936_7

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SSTSPICYCtSPIFtSPICLKLtSPIRtSPICLKHSPICLK(CPOL = 0)(output)tSPIFSPICLK(CPOL = 1)(output)tSPICLKHtSPICLKLtSPIRtSPIDSUMISO(input)tSPIDHLSB/MSB intSPIOHtSPIDVtSPIDVtSPIRMSB/LSB intSPIDVMOSI(output)tSPIFmaster MSB/LSB outmaster LSB/MSB out002aaa909Fig 28.SPI master timing (CPHA=1)SStSPIRtSPILEADSPICLK(CPOL = 0)(input)tSPIFSPICLK(CPOL = 1)(input)tSPIAtSPIOHtSPIDVMISO(output)tSPIFTSPICYCtSPICLKHtSPICLKLtSPIRtSPILAGtSPIRtSPICLKLtSPIRtSPICLKHtSPIOHtSPIDVtSPIOHtSPIDISslave MSB/LSB outslave LSB/MSB outnot definedtSPIDSUMOSI(input)tSPIDHtSPIDSUtSPIDSUtSPIDHMSB/LSB inLSB/MSB in002aaa910Fig 29.SPI slave timing (CPHA=0)P89LPC933_934_935_936_7© NXP B.V. 2008. All rights reserved.

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SStSPIRtSPILEADSPICLK(CPOL = 0)(input)tSPIFtSPICLKHtSPIRtSPIRtSPILAGTSPICYC tSPICLKLtSPIFtSPICLKLtSPIRtSPICLKHSPICLK(CPOL = 1)(input)tSPIOHtSPIAMISO(output)tSPIDVnot definedtSPIOHtSPIDVslave MSB/LSB outtSPIOHtSPIDVslave LSB/MSB outtSPIDIStSPIDSUMOSI(input)tSPIDHtSPIDSUtSPIDSUtSPIDHMSB/LSB inLSB/MSB in002aaa911Fig 30.SPI slave timing (CPHA=1)12.2ISP entry mode

Table 14.Dynamic characteristics, ISP entry modeVDD=2.4Vto3.6V, unless otherwise speciﬁed.Tamb=−40°Cto+85°C for industrial,−40°Cto+125°C for extended, unless otherwise speciﬁed.SymboltVRtRHtRL

ParameterRST delay from VDD active timeRST HIGH timeRST LOW timeConditionsMin5011Typ---Max-32-UnitµsµsµsVDDtVRRSTtRL002aaa912tRHFig 31.ISP entry timingP89LPC933_934_935_936_7© NXP B.V. 2008. All rights reserved.

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13.Other characteristics

13.1Comparator electrical characteristics

Table 15.Comparator electrical characteristicsVDD=2.4Vto3.6V, unless otherwise speciﬁed.Tamb=−40°Cto+85°C for industrial,−40°Cto+125°C for extended, unless otherwise speciﬁed.SymbolVIOVICCMRRtres(tot)t(CE-OV)ILI

[1]

Parameteroffset voltage input voltagecommon mode input voltagecommon mode rejection ratiototal response time

comparator enable to output valid timeinput leakage current

ConditionsMin-0

[1]

Typ---250--

Max±20VDD−0.3−5050010±10

UnitmVVdBnsµsµA

---

This parameter is characterized, but not tested in production.

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13.2ADC electrical characteristics

Table 16.ADC electrical characteristicsVDD=2.4Vto3.6V, unless otherwise speciﬁed.Tamb=−40°Cto+85°C for industrial,−40°Cto+125°C for extended, unless otherwise speciﬁed.All limits valid for an external source impedance of less than 10kΩ.SymbolVIACissEDEL(adj)EOEGEu(tot)MCTCαct(port)SRinTcy(ADC)tADC

Parameteranalog input voltageanalog input capacitancedifferential non-linearityintegral non-linearityoffset errorgain error

total unadjusted errorchannel-to-channel matchingcrosstalk between port inputsinput slew rateADC clock cycleconversion time

A/D enabled0kHz to 100kHzConditionsMin---------111-Typ-----------MaxVSS+0.215±1±1±2±1±2±1−60100200013Tcy(ADC)

UnitVpFLSBLSBLSB%LSBLSBdBV/msnsns

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14.Package outline

PLCC28: plastic leaded chip carrier; 28 leads

SOT261-2

eDyXeE251918ZEAbpb1wM26281pin 1 indexeβk5eDHD11ZDB412EHEAA4A1(A )3Lpdetail XvMAvMB05scale10 mmDIMENSIONS (mm dimensions are derived from the original inch dimensions)A4A1b1D(1)E(1)bpA3eDeEeHDUNITAmax.min.mminches4.574.190.510.250.013.050.120.530.330.810.66HEkLp1.441.02v0.18w0.18y0.1ZD(1)ZE(1)max.max.2.162.16β10.9210.9212.5712.571.2211.5811.581.279.919.9112.3212.321.0711.4311.430.430.390.430.390.1800.020.1650.0210.0320.4560.4560.050.0130.0260.4500.4500.4950.4950.0480.0570.0070.0070.0040.0850.0850.4850.4850.0420.04045oNote1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINEVERSIONSOT261-2 REFERENCES IEC112E08 JEDECMS-018 JEITAEDR-7319EUROPEANPROJECTIONISSUE DATE99-12-2701-11-15Fig 32.Package outline SOT261-2 (PLCC28)

P89LPC933_934_935_936_7

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TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mmSOT361-1

DEAXcyHEvMAZ2815QA2pin 1 indexA1(A )3AθLpLdetail X1ebp14wM02.5scale5 mmDIMENSIONS (mm are the original dimensions)UNITmmAmax.1.1A10.150.05A20.950.80A30.25bp0.300.19c0.20.1D(1)9.89.6E(2)4.54.3e0.65HE6.66.2L1Lp0.750.50Q0.40.3v0.2w0.13y0.1Z(1)0.80.5θ8o0oNotes1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINEVERSION SOT361-1 REFERENCES IEC JEDEC MO-153 JEITAEUROPEANPROJECTIONISSUE DATE99-12-2703-02-19Fig 33.Package outline SOT361-1 (TSSOP28)

P89LPC933_934_935_936_7

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HVQFN28: plastic thermal enhanced very thin quad flat package; no leads;28 terminals; body 6 x 6 x 0.85 mm

DBASOT788-1

terminal 1index areaAEA1cdetail Xe1e8L715b14vMCABwMCy1CCyeEhe21terminal 1index area28Dh0DIMENSIONS (mm are the original dimensions)UNITmmA(1)max.1A10.050.00b0.350.25c0.2D(1)6.15.9Dh4.253.95E(1)6.15.9Eh4.253.95e0.652122X2.5scalee13.9e23.9L0.750.50v0.1w0.05y0.05y10.15 mmNote1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINEVERSION SOT788-1 REFERENCES IEC- - - JEDECMO-220 JEITA- - -EUROPEANPROJECTIONISSUE DATE02-10-22Fig 34.Package outline SOT788-1 (HVQFN28)

P89LPC933_934_935_936_7

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15.Abbreviations

Table 17.AcronymA/DCPUDACEPROMEEPROMEMILEDPWMRAMRCRTCSARSFRSPIUART

Acronym list

DescriptionAnalog to DigitalCentral Processing UnitDigital to Analog Converter

Erasable Programmable Read-Only Memory

Electrically Erasable Programmable Read-Only MemoryElectro-Magnetic InterferenceLight Emitting DiodePulse Width ModulatorRandom Access MemoryResistance-CapacitanceReal-Time Clock

Successive Approximation RegisterSpecial Function RegisterSerial Peripheral Interface

Universal Asynchronous Receiver/Transmitter

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16.Revision history

Table 18.

Revision history

Release date20081126

Data sheet statusProduct data sheet

Change notice-SupersedesP89LPC933_934_935_936_6

Document IDP89LPC933_934_935_936_7Modiﬁcations:

•••

Theformatofthisdatasheethasbeenredesignedtocomplywiththe new identity guidelines of NXP Semiconductors.

Legaltextshavebeenadaptedtothenewcompanynamewhereappropriate.

Added extended temperature device P89LPC933HDH.

Product data sheetProduct data sheetObjective data

---P89LPC933_934_935_936_5P89LPC933_934_935-04

P89LPC933_934_935-03

P89LPC933_934_935_936_6P89LPC933_934_935_936_5P89LPC933_934_935-04

200506202004110320040209

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17.Legal information

17.1Data sheet status

Document status[1][2]Objective [short] data sheetPreliminary [short] data sheetProduct [short] data sheet

[1][2][3]

Product status[3]DevelopmentQualiﬁcationProduction

DeﬁnitionThis document contains data from the objective speciﬁcation for product development.This document contains data from the preliminary speciﬁcation.This document contains the product speciﬁcation.

Please consult the most recently issued document before initiating or completing a design.The term ‘short data sheet’ is explained in section “Deﬁnitions”.

Theproductstatusofdevice(s)describedinthisdocumentmayhavechangedsincethisdocumentwaspublishedandmaydifferincaseofmultipledevices.Thelatestproductstatusinformation is available on the Internet at URLhttp://www.nxp.com.

17.2Deﬁnitions

Draft —The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result inmodiﬁcations or additions. NXP Semiconductors does not give anyrepresentations or warranties as to the accuracy or completeness of

informationincludedhereinandshallhavenoliabilityfortheconsequencesofuse of such information.

Short data sheet —A short data sheet is an extract from a full data sheetwiththesameproducttypenumber(s)andtitle.Ashortdatasheetisintendedforquickreferenceonlyandshouldnotbereliedupontocontaindetailedandfull information. For detailed and full information see the relevant full datasheet, which is available on request via the local NXP Semiconductors salesofﬁce. In case of any inconsistency or conﬂict with the short data sheet, thefull data sheet shall prevail.

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use ofNXP Semiconductors products in such equipment or applications andtherefore such inclusion and/or use is at the customer’s own risk.

Applications —Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for thespeciﬁed use without further testing or modiﬁcation.

Limiting values —Stress above one or more limiting values (as deﬁned intheAbsoluteMaximumRatingsSystemofIEC60134)maycausepermanentdamagetothedevice.Limitingvaluesarestressratingsonlyandoperationofthe device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limitingvalues for extended periods may affect device reliability.

Terms and conditions of sale —NXP Semiconductors products are soldsubjecttothegeneraltermsandconditionsofcommercialsale,aspublishedathttp://www.nxp.com/proﬁle/terms, including those pertaining to warranty,intellectual property rights infringement and limitation of liability, unlessexplicitly otherwise agreed to in writing by NXP Semiconductors. In case ofany inconsistency or conﬂict between information in this document and suchterms and conditions, the latter will prevail.

No offer to sell or license —Nothing in this document may be interpretedor construed as an offer to sell products that is open for acceptance or thegrant,conveyanceorimplicationofanylicenseunderanycopyrights,patentsor other industrial or intellectual property rights.

17.3Disclaimers

General —Information in this document is believed to be accurate and

reliable.However,NXPSemiconductorsdoesnotgiveanyrepresentationsorwarranties,expressedorimplied,astotheaccuracyorcompletenessofsuchinformation and shall have no liability for the consequences of use of suchinformation.

Right to make changes —NXPSemiconductorsreservestherighttomakechanges to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and withoutnotice.Thisdocumentsupersedesandreplacesallinformationsuppliedpriorto the publication hereof.

Suitability for use —NXP Semiconductors products are not designed,authorized or warranted to be suitable for use in medical, military, aircraft,space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

17.4Trademarks

Notice:Allreferencedbrands,productnames,servicenamesandtrademarksare the property of their respective owners.I2C-bus —logois a trademark of NXP B.V.

18.Contact information

For more information, please visit:http://www.nxp.com

For sales ofﬁce addresses, please send an email to:salesaddresses@nxp.com

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19.Contents

1General description. . . . . . . . . . . . . . . . . . . . . . 12Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1Principal features . . . . . . . . . . . . . . . . . . . . . . . 12.2Additional features . . . . . . . . . . . . . . . . . . . . . . 23Product comparison overview. . . . . . . . . . . . . 34Ordering information. . . . . . . . . . . . . . . . . . . . . 34.1Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 35Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 46Pinning information. . . . . . . . . . . . . . . . . . . . . . 56.1Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56.2Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 77Logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . 118Functional description . . . . . . . . . . . . . . . . . . 128.1Special function registers . . . . . . . . . . . . . . . . 128.2Enhanced CPU. . . . . . . . . . . . . . . . . . . . . . . . 248.3Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248.3.1Clock deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . 248.3.2CPU clock (OSCCLK). . . . . . . . . . . . . . . . . . . 248.3.3Low speed oscillator option . . . . . . . . . . . . . . 248.3.4Medium speed oscillator option . . . . . . . . . . . 248.3.5High speed oscillator option . . . . . . . . . . . . . . 248.3.6Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 248.4On-chip RC oscillator option. . . . . . . . . . . . . . 258.5Watchdog oscillator option . . . . . . . . . . . . . . . 258.6External clock input option . . . . . . . . . . . . . . . 258.7CCLK wake-up delay . . . . . . . . . . . . . . . . . . . 278.8CCLK modiﬁcation: DIVM register . . . . . . . . . 278.9Low power select . . . . . . . . . . . . . . . . . . . . . . 278.10Memory organization . . . . . . . . . . . . . . . . . . . 278.11Data RAM arrangement . . . . . . . . . . . . . . . . . 288.12Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288.12.1External interrupt inputs . . . . . . . . . . . . . . . . . 288.13I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308.13.1Port conﬁgurations . . . . . . . . . . . . . . . . . . . . . 308.13.1.1Quasi-bidirectional output conﬁguration. . . . . 308.13.1.2Open-drain output conﬁguration. . . . . . . . . . . 308.13.1.3Input-only conﬁguration . . . . . . . . . . . . . . . . . 318.13.1.4Push-pull output conﬁguration . . . . . . . . . . . . 318.13.2Port0 analog functions. . . . . . . . . . . . . . . . . . 318.13.3Additional port features. . . . . . . . . . . . . . . . . . 318.14Power monitoring functions. . . . . . . . . . . . . . . 318.14.1Brownout detection. . . . . . . . . . . . . . . . . . . . . 328.14.2Power-on detection. . . . . . . . . . . . . . . . . . . . . 328.15Power reduction modes . . . . . . . . . . . . . . . . . 328.15.1Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328.15.2Power-down mode . . . . . . . . . . . . . . . . . . . . . 32

8.15.3

8.168.16.18.178.17.18.17.28.17.38.17.48.17.58.17.68.188.198.19.18.19.28.19.38.19.48.19.58.19.68.19.78.19.88.19.98.208.20.18.20.28.20.38.20.48.20.58.20.68.20.78.20.88.20.98.20.108.218.228.22.18.238.23.18.23.28.23.38.248.258.268.26.18.26.28.278.28

Total Power-down mode. . . . . . . . . . . . . . . . .Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Reset vector. . . . . . . . . . . . . . . . . . . . . . . . . .Timers/counters 0 and 1 . . . . . . . . . . . . . . . .Mode0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Mode1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Mode2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Mode3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Mode6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Timer overﬂow toggle output . . . . . . . . . . . . .RTC/system timer. . . . . . . . . . . . . . . . . . . . . .CCU (P89LPC935/936) . . . . . . . . . . . . . . . . .CCU clock . . . . . . . . . . . . . . . . . . . . . . . . . . .CCUCLK prescaling. . . . . . . . . . . . . . . . . . . .Basic timer operation. . . . . . . . . . . . . . . . . . .Output compare. . . . . . . . . . . . . . . . . . . . . . .Input capture . . . . . . . . . . . . . . . . . . . . . . . . .PWM operation . . . . . . . . . . . . . . . . . . . . . . .Alternating output mode. . . . . . . . . . . . . . . . .PLL operation. . . . . . . . . . . . . . . . . . . . . . . . .CCU interrupts. . . . . . . . . . . . . . . . . . . . . . . .UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Mode0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Mode1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Mode2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Mode3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Baud rate generator and selection. . . . . . . . .Framing error . . . . . . . . . . . . . . . . . . . . . . . . .Break detect. . . . . . . . . . . . . . . . . . . . . . . . . .Double buffering. . . . . . . . . . . . . . . . . . . . . . .Transmit interrupts with double buffering

enabled (modes1, 2 and 3). . . . . . . . . . . . . .The 9th bit (bit8) in double buffering

(modes1, 2 and 3). . . . . . . . . . . . . . . . . . . . .I2C-bus serial interface. . . . . . . . . . . . . . . . . .SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Typical SPI conﬁgurations . . . . . . . . . . . . . . .Analog comparators. . . . . . . . . . . . . . . . . . . .Internal reference voltage. . . . . . . . . . . . . . . .Comparator interrupt . . . . . . . . . . . . . . . . . . .Comparators and power reduction modes. . .Keypad interrupt. . . . . . . . . . . . . . . . . . . . . . .Watchdog timer . . . . . . . . . . . . . . . . . . . . . . .Additional features . . . . . . . . . . . . . . . . . . . . .Software reset . . . . . . . . . . . . . . . . . . . . . . . .Dual data pointers . . . . . . . . . . . . . . . . . . . . .Data EEPROM (P89LPC935/936). . . . . . . . .Flash program memory . . . . . . . . . . . . . . . . .

33 33 33 34 34 34 34 34 34 34 34 35 35 35 35 35 35 36 37 37 38 38 38 39 39 39 39 39 40 40 40 40 41 43 44 46 46 47 47 47 48 48 48 48 49 49

continued >>

Product data sheetRev. 07 — 26 November 200874 of 75

元器件交易网www.cecb2b.com

NXP Semiconductors

P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.28.1General description. . . . . . . . . . . . . . . . . . . . . 498.28.2Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498.28.3Flash organization . . . . . . . . . . . . . . . . . . . . . 508.28.4Using ﬂash as data storage . . . . . . . . . . . . . . 508.28.5Flash programming and erasing. . . . . . . . . . . 508.28.6In-circuit programming . . . . . . . . . . . . . . . . . . 508.28.7In-application programming . . . . . . . . . . . . . . 508.28.8ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518.28.9Power-on reset code execution. . . . . . . . . . . . 518.28.10Hardware activation of the boot loader. . . . . . 528.29User conﬁguration bytes. . . . . . . . . . . . . . . . . 528.30User sector security bytes . . . . . . . . . . . . . . . 529A/D converter. . . . . . . . . . . . . . . . . . . . . . . . . . 529.1General description. . . . . . . . . . . . . . . . . . . . . 529.2Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529.3Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . 539.4A/D operating modes . . . . . . . . . . . . . . . . . . . 539.4.1Fixed channel, single conversion mode . . . . . 539.4.2Fixed channel, continuous conversion mode . 549.4.3Auto scan, single conversion mode . . . . . . . . 549.4.4Auto scan, continuous conversion mode . . . . 549.4.5Dual channel, continuous conversion mode. . 549.4.6Single step mode . . . . . . . . . . . . . . . . . . . . . . 549.5Conversion start modes . . . . . . . . . . . . . . . . . 549.5.1Timer triggered start. . . . . . . . . . . . . . . . . . . . 549.5.2Start immediately . . . . . . . . . . . . . . . . . . . . . . 549.5.3Edge triggered . . . . . . . . . . . . . . . . . . . . . . . . 559.5.4Dual start immediately (P89LPC935/936) . . . 559.6Boundary limits interrupt. . . . . . . . . . . . . . . . . 559.7DAC output to a port pin with high output

impedance . . . . . . . . . . . . . . . . . . . . . . . . . . .

559.8Clock divider. . . . . . . . . . . . . . . . . . . . . . . . . . 559.9Power-down and Idle mode . . . . . . . . . . . . . . 5510Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 5611Static characteristics. . . . . . . . . . . . . . . . . . . . 5711.1IOH as a function of VOH . . . . . . . . . . . . . . . . . 5812Dynamic characteristics . . . . . . . . . . . . . . . . . 5912.1Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 6312.2ISP entry mode. . . . . . . . . . . . . . . . . . . . . . . . 6513Other characteristics. . . . . . . . . . . . . . . . . . . . 6613.1Comparator electrical characteristics . . . . . . . 6613.2ADC electrical characteristics. . . . . . . . . . . . . 6714Package outline . . . . . . . . . . . . . . . . . . . . . . . . 6815Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 7116Revision history. . . . . . . . . . . . . . . . . . . . . . . . 7217Legal information. . . . . . . . . . . . . . . . . . . . . . . 7317.1Data sheet status . . . . . . . . . . . . . . . . . . . . . . 7317.2Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7317.3Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . .

17.4Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 7318Contact information . . . . . . . . . . . . . . . . . . . . 7319

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Pleasebeawarethatimportantnoticesconcerningthisdocumentandtheproduct(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 26 November 2008

Document identifier: P89LPC933_934_935_936_7

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