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arm实验例题

2020-01-11 来源:步旅网


arm实验例题

例4.1 简单分支程序。寄存器r0和r1中有两个正整数,求这两个数的最大公约数,结果存储在r0中。 程序代码:

AREA example1,CODE ENTRY

MOV r0, #15 MOV r1, #9 start

CMP r0, r1 SUBLT r1, r1, r0 SUBGT r0, r0, r1 BNE start stop

B stop END

例4.2 复杂分支程序。寄存器R0、R1和R2中有三个数,求其中最大的一个,结果存储在R3中。

程序代码:

AREA example2, CODE ENTRY

MOV R0,#10 MOV R1,#30 MOV R2,#20 start

CMP R0,R1 BLE lbl_a CMP R0,R2 MOVGT R3,R0 MOVLE R3,R2 B lbl_b lbl_a

CMP R1,R2 MOVGT R3,R1 MOVLE R3,R2 lbl_b

case0:

arithfunc = DoAdd; R0=arithfunc (R1,R2); break; case1:

arithfunc = DoSub; R0=arithfunc (R1,R2); break; default: break; }

while (1); }

汇编.S文件

AREA example3, CODE,READONLY; num EQU 2 ENTRY Start

MOV R0,#0 MOV R1,#3 MOV R2,#2 BL function

B . function

CMP R0,#num MOVHS PC,LR ADR R3,JumpTable LDR PC,[R3,R0,LSL #2] ; ; JumpTable

DCD FuncAdd DCD FuncSub FuncAdd

ADD R0,R1,R2 MOV PC,LR FuncSub

SUB R0,R1,R2 MOV PC,LR END

例4.4 中断向量表

AREA example4,CODE,READONLY LDR PC,Reset_Addr

LDR PC,Undefined_Addr LDR PC,SWI_Addr LDR PC,Prefetch_Addr LDR PC,Abort_Addr NOP

LDR PC,IRQ_Addr LDR PC,FIQ_Addr

Reset_Addr DCD Reset_Handler Undefined_Addr DCD Undefined_Handler SWI_Addr DCD SWI_Handler Prefetch_Addr DCD Prefetch_Handler Abort_Addr DCD Abort_Handler DCD 0

IRQ_Addr DCD IRQ_Handler FIQ_Addr DCD FIQ_Handler IMPORT __main Reset_Handler B __main Undefined_Handler mov pc, lr SWI_Handler mov pc, lr

Prefetch_Handler mov pc, lr Abort_Handler mov pc, lr IRQ_Handler mov pc, lr FIQ_Handler mov pc, lr END

例4.5数据块复制。编程实现将从地址src开始的num个字的数据复制到地址dst去。 汇编代码:

AREA example5, CODE,READONLY num EQU 25 ENTRY Start

LDR R0,=src LDR R1,=dst mov R2,#num Blockcopy

MOVS R3,R2,LSR#3 BEQ wordcopy STMFD SP!, {R4-R11} copy

LDMIA R0!,{R4-R11} STMIA R1!,{R4-R11} SUBS R3,R3, #1 BNE copy wordcopy

ANDS R2,R2, #7 BEQ Stop CopyLoop

LDR R3,[R0], #4 STR R3,[R1], #4 SUBS R2,R2, #1 BNE CopyLoop

Stop B .

AREA oriData,DATA,READWRITE src ,1,2,3,4

dst SPACE 25*4 END

例4.6多重循环,对n个数进行从小到大排序。 汇编代码:

AREA example6, CODE,READONLY num EQU 10 ENTRY start

LDR R0,=src MOV R2,#num-1 LOOP1

DCD

0,1,2,3,4,5,6,7,8,9,0,1,2,3,4,5,6,7,8,9,0

LDR R4,[R0,R2,LSL #2] SUBS R3,R2,#1 LOOP2

LDRPL R5,[R0,R3,LSL #2] CMP R5,R4

STRGT R4,[R0,R3,LSL #2] STRGT R5,[R0,R2,LSL #2] MOVGT R4,R5 SUBS R3,R3,#1 BPL LOOP2 SUBS R2,R2,#1 BHI LOOP1 B .

AREA DataArea, DATA,READWRITE src DCD 6,1,9,8,4,5,0,7,3,2 END

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