HIP7010ADVANCE INFORMATION
August 1996
J1850 Byte Level Interface Circuit
DescriptionThe Intersil HIP7010, J1850 Byte Level Interface Circuit, is amember of the Intersil family of low-cost multiplexed wiringICs. The integrated functions of the HIP7010 provide thesystem designer with components key to building a “Class B”multiplexed communications network interface, which fullyconforms to the VPW Multiplexed Wiring protocol specifiedinthe SAE J1850 Standard. The HIP7010 is designed tointerface with a wide variety of Host microcontrollers via astandard three wire, high-speed (1MHz), synchronous, serialinterface. The HIP7010 automatically produces properlyframed VPW messages,prepending the Start of Frame(SOF) symbol and calculating and appending the CRCcheck byte. All circuitry needed to decode incoming mes-sages, to validate CRC bytes, and to detect Breaks, End ofData (EOD), Idle bus, and illegal symbols is included. In-Frame Responses (IFRs) are fully supported for Type 1,Type 2, and Type 3 messages, with the appropriate Normal-ization Bit automatically generated. The HCMOS designallows proper opeSration at various input frequencies from2MHz to 12MHz. Connection to the J1850 Bus is via a Inter-sil HIP7020.Features•Fully Supports VPW (Variable Pulse Width) MessagingPractices of SAE J1850 Standard for Class B DataCommunications Network Interface-3-Wire, High-Speed, Synchronous, Serial Interface•Reduces Wiring Overhead•Directly Interfaces with 68HC05 and 68HC11 Style SPIPorts•1MHz, 8-Bit Transfers Between Host and HIP7010Minimize Host Service Requirements•Automatically Transmits Properly Framed Messages•Prepends SOF to First Byte and Appends CRC to LastByte•Fail-Safe Design Including, Slow Clock DetectionCircuitry, Prevents J1850 Bus Lockup Due to SystemErrors or Loss of Input Clock•Automatic Collision Detection•End of Data (EOD), Break, Idle Bus, and Invalid Symbol(Noise/Illegal Symbols) Detection•Supports In-Frame Responses with Generation ofNormalization Bits (NB) for Type 1, Type 2, and Type 3Messages•Wait-For-Idle Mode Reduces Host Overhead DuringNon-Applicable Messages•Status Register Flags Provide Information on CurrentStatus of J1850 Bus•Serial I/O Pins are Active Only During Transfers - BusAvailable for Other Devices 95% of the Time•TEST Pin Provides Built-in-Test Capabilities forIn-System Diagnostics and Factory Testing•High Speed (4X) Receive Mode for Production andDiagnostic Testing/Programming•Operates with Wide Range of Input Clock Frequencies•Power-Saving Power-Down Mode•Full -40oC to +125oC Operating Range•Single 3.0V to 6.0V SupplyOrdering InformationTEMP.PART NUMBERRANGE (oC)HIP7010PHIP7010B-40 +125-40 +125PACKAGE14 Lead Plastic DIP14 Lead Plastic SOIC (N)PKG. NO.E14.3M14.15PinoutHIP7010 (SOIC, PDIP)TOP VIEWIDLE1VPWIN2VPWOUT3VDD4RESET5TEST6SACTIVE714RDY13STAT12CLK11VSS10SIN9SOUT8SCKCAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.www.intersil.com or 407-727-9207|Copyright © Intersil Corporation 1999
File Number
3644.2
1
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HIP7010Block DiagramSIN10LSBABMUXCMSBOUTPUT DATA3DATA SHIFT REGISTERDECODED VPW INJ1850 VPW SYMBOLENCODER/DECODERVPWOUT2VPWINSOUT9AMUXBSTATUS/CONTROL BYTECRC GENERATOR/CHECKERSCKIDLERDYSTATCLKRESETTESTSACTIVE81141312567TIMINGGENERATORSTATE MACHINEAND CONTROL LOGICVDD 4VSS 11Pin DescriptionPIN NUMBER1234567891011121314PIN NAMEIDLEVPWINVPWOUTVDDRESETTESTSACTIVESCKSOUTSINVSSCLKSTATRDYIN/OUTOUTINOUT-ININOUTOUTOUTIN-INININCMOS OutputCMOS Schmitt (No VDD Diode)CMOS OutputPower SupplyCMOS Schmitt (No VDD Diode)CMOS Input with Pull-DownCMOS OutputThree-State with Pull-DownThree-State with Pull-DownCMOS Input with Pull-DownGroundCMOS Schmitt (No VDD Diode)CMOS Input with Pull-DownCMOS Input with Pull-DownPIN DESCRIPTION2
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HIP7010Absolute Maximum RatingsSupply Voltage (VDD). . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +7.0VInput or Output VoltagePins with VDD Diode. . . . . . . . . . . . . . . . . . . .-0.3V to VDD+0.3VPins without VDD Diode . . . . . . . . . . . . . . . . . . . .-0.3V to +10.0VESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 2Gate Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+2500 GatesThermal InformationThermal ResistanceθJAPlastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . .+100oC/WSOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+120oC/WMaximum Package Power Dissipation at +125oCDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250mWSOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200mWOperating Temperature Range (TA) . . . . . . . . . . .-40oC to +125oCStorage Temperature Range (TSTG). . . . . . . . . . .-65oC to +150oCJunction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150oCLead Temperature (Soldering, 10s). . . . . . . . . . . . . . . . . . . .+265oCCAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationof the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.Operating ConditionsOperating Voltage Range. . . . . . . . . . . . . . . . . . . . .+3.0V to +5.5VOperating Temperature Range. . . . . . . . . . . . . . . .-40oC to +125oCInput Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8VInput High Voltage. . . . . . . . . . . . . . . . . . . . . . . . ..(0.8VDD) to VDDInput Rise and Fall TimeCMOS Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100ns MaxCMOS Schmitt Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .UnlimitedElectrical SpecificationsSupply CurrentOperating CurrentPower-Down Mode (Note 1)Clock Stopped (Note 2)Input High VoltageTA = -40oC to +125oC, VDD = 5VDC±10%, Unless Otherwise SpecifiedSYMBOLCONDITIONSMINTYPMAXUNITSPARAMETERSIOPIPDISTOPVIHCLK = 2.0 MHzPD = 1CLK = VSS or VDD---1.0505.05.015050mAµAµACMOS Level (SIN, STAT, RDY, TEST)Schmitt Trigger (RESET, CLK,VPWIN)Input Low VoltageCMOS Level (SIN, STAT, RDY, TEST)Schmitt Trigger (RESET, CLK,VPWIN)High Level Input Current(CLK,VPWIN,RESET)Input Buffer with Pull-Down (SIN, TEST, STAT, RDY)Low Level Input Current(CLK,VPWIN,RESET)Input Buffer with Pull-Down (SIN, TEST, STAT, RDY)Output High Voltage(SCK, SOUT, VPWOUT,IDLE,SACTIVE)Output Low Voltage(SCK, SOUT, VPWOUT,IDLE,SACTIVE)High Impedance Leakage CurrentThree-State with Pull-Down (SCK, SOUT)0.7VDD0.8VDD--VDDVDD0.3VDD0.2VDD1500VVVILVSSVSS--VVIIHVIN = VDD-11000.001200µAµAIILVIN = VSS-1-10-0.001-0.01110µAµAVOHVOLIOZVHYSILOAD = 0.8 mAILOAD = -1.6 mAVOUT = VDDVOUT = VSSVDD-0.8---V-0.4V100-100.220050010µAµAVSchmitt Trigger Hysteresis Voltage(RESET, CLK,VPWIN)NOTES:0.52.01.SIN, STAT, RDY, and TEST = VSS;SACTIVE, SCK, and SOUT unconnected;VPWIN = VDD; CLK = 10MHz.2.SIN, STAT, RDY, and TEST = VSS;SACTIVE, SCK, and SOUT unconnected;VPWIN = VDD; PD = 1.3
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HIP7010Serial Interface TimingNUMBER--(1)(2)SYMBOL-- tCYCtLEADOperating FrequencyInput CLK Duty CycleSCK Cycle TimeSACTIVE Lead TimeBefore Status/Control TransferBefore Data Transfer(3)tLAGSACTIVE Lag Time After Status/Control Transfer After Data Transfer(4)(5)(6)(7)(8)(9)tSCKHtSCKLtDVSCKtSCKDXtDZDAtDADZtDVSCKtDXSCKtRISEtFALL tSTATHtRDYHtRESETL(16)tSACTIVEClock (SCK) HIGH TimeClock (SCK) LOW TimeRequired Data In Setup Time (SIN to SCK)Required Data In Hold Time (SIN after SCK)Data Active from High Impedance Delay (SACTIVE to SOUT Active)Data Active to High Impedance Delay (SACTIVE to SOUT HighImpedance)Data Out Setup Time (SOUT to SCK)Data Out Hold Time (SOUT after SCK)Output Rise Time (0.3VDD to 0.7VDD, CL = 100pF)Output Fall Time (0.7VDD to 0.3VDD, CL = 100pF)Required STAT Pulse WidthRequired RDY Pulse WidthRequiredRESET Pulse WidthSACTIVE Delay from RDY (IDLE = VSS)SACTIVE Delay from STAT (FTU = 0)(17)(18)(19)tRDYSCKtSCKRDYtRECfSLOWNOTE:1.All parameters are specifications of the HIP7010 component not of a system. Parameters specified as “Required” (i.e., tSTATH) refer tothe requirements of the HIP7010. If a “Required” pulse width is specified as 75ns maximum, that implies that 75ns is the maximum widththat any HIP7010 device will require. Therefore, a system that provides aminimum pulse width of 75ns will satisfy thismaximumrequirement.Required RDY Removal Time Prior to Last SCK for Short RDYRequired RDY Hold Time after Last SCK for Long RDYRequired SERIAL Recovery Time (Minimum Time afterSACTIVEUntil Next RDY/STAT)Slow clock detect frequency limit6501250450450---10-750130050050010-10101085014005505505040-40nsnsnsnsnsnsnsns450115075012258501300nsns(See Figure 1- Figure 7) TA = -40oC to +125oC, VDD = 5VDC±10%, Unless Otherwise SpecifiedPARAMETERSMIN240-TYP8501.0MAX1260-UNITSMHz%MHz(10)(11)(12)(13)(14)(15)375375157---11505---47547575252020201750285250675--150757575752450900100100750nsnsnsnsnsnsnsnsnsnsnsns2080200KHz4
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HIP7010STAT(INPUT)(14)RDY (SHORT)(INPUT)(15)RDY (LONG)(INPUT)SACTIVE(OUTPUT)(16)(17)(18)(19)(2)(1)(13)(12)(3)SCK(OUTPUT)(4)(5)D7OD6OD0O(9)SOUT(OUTPUT)(8)(10)(11)D7ID6ID0ISIN(INPUT)(6)(7)FIGURE 1.SERIAL INTERFACE TIMING DIAGRAMNOTES:1.Measurement points are from VDD/2, except 12 and 13 which are measured between VIL and VIH.2.All timings assume proper CLK frequency and Divide Select values to generate 1MHz SCK.Functional Pin DescriptionThis section provides a description of each of the 14 pins ofthe HIP7010 as shown in Figure 2.IDLE1VPWIN2VPWOUT3VDD4RESET5TEST6SACTIVE714RDY13STAT12CLK11VSS10SIN9SOUT8SCKCLK (Clock - Input)The Clock input (CLK) provides the basic time base refer-ence for all J1850 symbol detection and generation. SerialBus transfers between the HIP7010 and the Host microcon-troller are also timed based on the Clock input. Proper VPWsymbol detection and generation requires a 2MHz clockwhich is internally derived from the CLK input. Various CLKinput frequencies can be accommodated via the DivideSelect bits in the Status/Control Register (seeStatus/Con-trol Register for details).An internal Slow Clock Detect circuit monitors the CLK inputsignal and generates a HIP7010 reset if the clock is inactivefor more than1/fSLOW. This is a safety mechanism to preventblocking the J1850 and Serial busses in the event of a clockfailure. The Slow Clock Detect reset can also be intentionallyinvoked by externally inhibiting CLK input transitions.Power can be reduced under Host control via the PowerDownbit in the Status/Control Register (see Status/Control Regis-ter for details). Setting the Power-Down bit effectively stopsinternal clocking of the HIP7010.FIGURE 2.14 PIN DIP AND SO TERMINAL ASSIGNMENTSVDD and VSS (Power)Power is supplied to the HIP7010 using these two pins. VDDis connected to the positive supply and VSS is connected tothe negative supply.5
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HIP7010For enhanced noise immunity, the CLK input is a CMOS Schmitttrigger input. SeeElectrical Specifications for input levels.VPWOUT (Variable Pulse Width Out - Output),VPWIN (Variable Pulse Width In - Input)These two lines are used to interface to a J1850 bus trans-ceiver, such as the Intersil HIP7020. VPWOUT is the vari-able pulse width modulated output of the HIP7010’s symbolencoder circuit.VPWIN is the inverted input to the symboldecoder of the HIP7010.VPWIN is a Schmitt input.SIN (Serial In - Input),SOUT (Serial Out - Output),SCK (Serial Clock - Output),SACTIVE (Serial Bus Active - Output)These four lines constitute the synchronous Serial Interface(SERIAL) interface of the HIP7010. See theSerial Interface(SERIAL) System for details. SIN, SOUT, and SCK providethe three principal connections to the Host controller. SIN is aCMOS input. SOUT and SCK are three-state outputs whichare only activated during serial transfers. The SIN, SOUT, andSCK pins contain integrated pull-down load devices whichprovide termination on the bus whenever it is in a high imped-ance state. The SACTIVE pin is a CMOS output, which pullslow when the HIP7010 is communicating on the serial bus.SeeSerial Interface (SERIAL) System andApplicationsInformation for more details.RDY (Byte Ready - Input)The Byte Ready (RDY) line is a “handshaking” input from theHost. Each rising edge on the RDY pin signifies that the Hosthas loaded a byte into its SERIAL transmit register and theHIP7010 can retrieve it (by generating clocks on SCK) whenthe HIP7010 is ready for the data. SeeSerial Interface(SERIAL) SystemandApplications Information for moredetails.The RDY pin contains an integrated pull-down load devicewhich will hold the pin low if it is left unconnected.IDLE (Idle/Service Request - Output)TheIDLE output pin indicates that the J1850 Bus has beenin a passive state for at least275µs and is now idle. If thebus has been passive for a minimum of 239µs and anothernode initiates a new message,IDLE will pulse low for 1µs.In its role as a Service Request pin, a reset forcesIDLEhigh. Following the reset,IDLE remains high for 17 CLKcycles and is then driven low.IDLE will remain low until 40CLK cycles +1.5µs after completion of the first Status/Con-trol byte transfer. TheIDLE pin will then resume its normalrole, remaining high until a275µslull (or 239µs plus a pas-sive to active transition) has been detected on the J1850bus. This provides a handshake mechanism to ensure theHost will reinitialize the HIP7010 each time the HIP7010 isreset via POR,RESET, or Slow Clock Detect.IfIDLE is low when an echo failure causes the ERR bit to beset in the Status byte, theIDLE pin will pulse high for 2µsand then return low (see Status/Control Register).IfIDLE is low when the host sets the NXT bit in the controlbyte, theIDLE pin will pulse high for 2µs and then return low(see Status/Control Register).In general a Status/Control byte transfer should be performedeach time IDLE goes low. SeeEffects of Resets and Power-Down andApplications Information for more details.TheIDLE pin is an active low CMOS output. SeeOperationof the HIP7010 for more details.STAT (Request Status/Control - Input)The Request Status/Control (STAT) input pin is used by theHost microcontroller to initiate an exchange of the Host’s con-trol byte and the HIP7010’s status byte. A low to high transi-tion on the STAT input signals the HIP7010 that the Host hasplaced a control word in it’s SERIAL output register and isready to exchange it with the HIP7010’s status word. TheHIP7010 controls the exchange by generating the 8 SCKsrequired. SeeSerial Interface (SERIAL) Systemand Appli-cations Information for more details.The STAT pin contains an integrated pull-down load devicewhich will hold the pin low if it is left unconnected.RESET (Reset - Input)TheRESET input is a low level active input, which resets theHIP7010. Resetting the HIP7010 forcesSACTIVE high, dis-ables the SOUT and SCK pins, forces the VPWOUT outputlow, drivesIDLE high, and returns the internal state machineto its initial state. Following reset, the HIP7010 is inhibitedfrom transmitting or receiving J1850 messages until a Sta-tus/Control Register transfer has been completed (seeEffects Of Resets And Power-Down for more details).The HIP7010 is also reset during initial power-on, by aninternal power-on-reset (POR) circuit.Loss of a clock on the CLK input will cause a reset asdescribed previously underCLK.If not used, theRESET pin should be tied to VDD.For enhanced noise immunity, theRESET input is a CMOSSchmitt trigger input. SeeElectrical Specifications forinput levels.TEST (Test Mode - Input)The TEST input provides a convenient method to test theHIP7010 at the component level. Raising the TEST pin to ahigh level causes the HIP7010 to enter a special TEST mode.In the TEST mode, a special portion of the state machine isactivated which provides access to the Built-in-Test and diag-nostic capabilities of the HIP7010 (seeTest Mode for moredetails).The TEST pin contains an integrated pull-down load devicewhich will hold the pin low if it is left unconnected. In manyapplications the TEST pin will be left unconnected, to allowaccess via a board level ATE tester.6
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HIP7010J1850 VPW MessagingThis section provides an introduction to J1850 multiplexedcommunications. It is assumed that the user is or willbecome familiar with the appropriate documents publishedby the Society of Automotive Engineering (SAE). The follow-ing discussion is not comprehensive.Overview
TheSAE J1850 Standard(Note 1) (J1850) establishes therequirements for communications on a Class B multiplexedwiring network for automotive applications. The J1850 docu-ment details the requirements in a three layer descriptionwhich separately specifies the characteristics of thephysicallayer, thedata link layer, and theapplication layer. There areseveral options within each layer which allows vehicle manu-facturers to customize the network while still maintaining alevel of universality.
NOTE:
1.SAE J1850 Standard, Class B Data Communication NetworkInterface, May 1994, Society of Automotive Engineers Inc.
Anatomy of a J1850 VPW Message
All messages in a J1850 VPW system are sent along a singlewire, shared bus. At any given moment the bus can be ineither of two states:active (high) orpassive (low). Multiplenodes are connected to the bus as a “wired-OR” network inwhich the bus is high ifanyone (or more) node is generatingan active output. The bus is only low whennonodes are gen-erating active outputs. It follows that, when no communica-tions are taking place the bus will rest in the passive state. Amessage begins when the bus is first driven to the high state.Each succeeding state transition (i.e., a change from active topassive or passive to active) transfers one bit of information(symbol) until the message is complete and the bus onceagain rests at the passive state. The interpretation of eachsymbol in the message is dependent on its duration (andstate), hence, the descriptor Variable Pulse Width (VPW).Each message has a beginning and an end, the span ofwhich encompasses the entiremessage orframe (refer toFigure 3). A frame consists of an activestart of frame (SOF)symbol and a passiveend of frame (EOF) symbol sandwichedaround a series of byte sized (8-bit) groups of symbols. Thefirst byte of the frame contents is always aheader byte, fol-lowed by possibly additional header bytes, followed by one ormoredata bytes, followed by an integrity check byte (CRCbyte), followed by a passiveend of data (EOD) symbol, fol-lowed by possibly one or morein-frame-response(IFR) bytes.To keep waiting times low, messages are limited to 12 bytestotal (including header, data, check, and IFR bytes). All mes-sage bytes are transmitted most significant bit (MSB) first.VPW Symbol Definitions
Within the J1850 scheme, symbols are defined in terms of bothduration and state (passive or active). The duration is mea-sured as the time between successive transitions. There is onetransition per symbol and one symbol per transition. The end ofone symbol marks the beginning of the next. Since the bus ispassive when a message begins and must return to that samestate when the message completes, all frames have an evennumber of transitions and hence an even number of symbols.There are unique definitions for data bit symbols (all the sym-bols which occur within the header, data, and check bytes) andprotocol symbols (including SOF, EOD, and EOF). The durationof each symbol is expressed in terms of VPW Timing Pulses(TV values). Table 1 summarizes the TV definitions. Each TV isspecified in terms of anominal (or ideal) duration and amini-mum andmaximum duration. The span between the minimumand maximum limits accommodates system noise sourcessuch as node to node clock skew, ground offsets, clock jitter,and electromechanical noise. There are no dead zonesbetween the maximum of one TV and the minimum of the next.
The hardware of the Intersil HIP7010 provides featureswhich facilitate implementation of the 10.4Kbps VariablePulse Width Modulated (VPW) physical layer option ofJ1850. In combination with a bus transceiver, such as theIntersil J1850 Bus Transceiver HIP7020, and appropriatesoftware algorithms, the HIP7010 circuitry enables thedesigner to completely implement a 10.4Kbps VPW Class BCommunications Network Interface per J1850. Features ofsuch an implementation include:•••••••••
Single Wire 10.4Kbps CommunicationsBit-by-Bit Bus ArbitrationIndustry Standard Protocol
Message Acknowledgment (“In-Frame Response”) Capa-bilities
Exceptionally Tolerant of Clock Skew, System Noise, andGround Offsets
Meets CARB and EPA Diagnostic RequirementsSupports up to 32 NodesLow Error Rates
Excellent EMC Levels (when interfaced via Intersil J1850Bus Transceiver HIP7020)
In addition to the standard J1850 features, the HIP7010 hard-ware provides a high speed mode, (intended for receive onlyuse) which can significantly enhance vehicle maintenancecapabilities. The high speed mode provides a 41.6Kbps com-munications path to any node built with the HIP7010.
SOFHEADER
DATA1DATA2
CRCEODEOF
FIGURE 3.TYPICAL J1850 VPW MESSAGE FRAME
7
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HIP7010The termsshort andlong are often used to refer to pulses ofduration TV1 and TV2 respectively.TABLE 1.J1850 TV DEFINITIONSDURATION (ALL TIMES INµs)TV IDIllegalTV1TV2TV3TV4TV5TV6MINIMUM0>34>96>163>239>239>280NOMINALNA64128200280300300MAXIMUM≤34≤96≤163≤239NANANA0 Data1 DataSOF (Start of Frame)EOD (End of Data)EOF (End of Frame)IFS (Inter-Frame Separation)IDLE (Idle Bus)NB (Normalization Bit)BRK (Break)Table 2 summarizes the complete set of symbol definitionsbased on duration and state.TABLE 2. J1850 SYMBOL DEFINITIONSSYMBOLDEFINITIONPassive TV1 or Active TV2Active TV1 or Passive TV2Active TV3Passive TV3Passive TV4Passive TV6Passive >TV6 NominalActiveTV1 or Active TV2Active TV5VPW is a non-return-to-zero (NRZ) protocol in which eachtransition represents a complete bit of information. Accord-ingly, a0 data bit will sometimes be transmitted as a passivepulse and sometimes as an active pulse. Similarly, a1 databit will sometimes be transmitted as a passive pulse andsometimes as an active pulse. In order to accommodatearbitration (seeBus Arbitration) along active pulse repre-sents a 0 data bit and ashort active pulse represents a 1data bit. Complementing this fact, ashort passive pulse rep-resents a 0 and along passive pulse represents a 1. Startingfrom a transition to the active state, a 0 data bit will maintainthe active level longer than a 1. Similarly, starting from atransition to the passive state, a 0 data bit will return to theactive level quicker than a 1. These facts give rise to thedominance of 0’s over 1’s on the J1850 bus as depicted inFigure 4. SeeBus Arbitration for additional details.SYNCHRONIZEDIn Frame Response (IFR)The distinction between two of the passive symbols, EOD andEOF, is subtle but important (refer to Figure 5). The EOD (TV3)interval signifies that the originator of the message is donebroadcasting and any nodes which have been requested torespond (i.e., to acknowledge receipt of the message) can nowdo so. The EOD interval begins when the transmitting node hascompleted sending the eighth bit of the check byte. The trans-mitter simply releases the bus and allows it to revert to a pas-sive state. In the course of normal messaging, no node canseize the bus until an EOD time has been detected. Once anEOD has elapsed, any nodes which are scheduled to producean IFR will arbitrate for control of the bus (seeBus Arbitration)and respond appropriately. If no responses are forthcoming thebus remains in the passive state until an EOF (TV4) intervalhas elapsed. After the EOF has been generated, the frame isconsidered closed and the next communications on the bus willrepresent a totally new message.IFRs can consist of multiple bytes from a single respondent,one byte from a single respondent, or one byte from multiplerespondents. In all cases the first response byte must be pre-ceded by anormalization bit (NB) which serves as astart ofresponse symbol and places the bus in an active state so thatfollowing the IFR byte(s) the bus will be left in the passive state.The NB symbol is by definition active, but can be either TV1or TV2 in duration. The long variety (TV2) signifies the IFRcontains a CRC byte. The short variety (TV1) precedes anIFR without CRC.Message Types0DATABIT01DATABIT1LONGER ACTIVEPULSE (0)CONTROLS THE BUSJ1850BUS0FIGURE 4A.DOMINANCE OF ACTIVE 0 DATA BITSYNCHRONIZED0DATABIT0Messages are classified into one of fourTypes according towhether the message has an IFR and what kind of IFR it is.The definitions are:•Type 0 -No IFRSHORTER PASSIVEPULSE (0)CONTROLS THE BUS1DATABIT1J1850BUS0•Type 1 -One byte IFR from a single respondent(no CRC byte)•Type 2 -One byte IFRs from multiple respondents(no CRC byte)•Type 3 -Multiple byte IFR from a single respondent(CRC appended)FIGURE 4B.DOMINANCE OF PASSIVE 0 DATA BITFIGURE 4.8
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HIP7010Bus ArbitrationThe nature of multiplexed communications leads to contentionissues when two or more nodes attempt to transmit on the bussimultaneously. Within J1850 VPW systems, messages areassigned varying levels of priority which allows implementa-tion of an arbitration scheme to resolve potential contentions.The specified arbitration is performed on a symbol by symbolbasis throughout the duration of every message.Arbitration begins with the rising edge of the SOF pulse. Nonode should attempt to issue an SOF until anIdle bus hasbeen detected (i.e., anInter-Frame Separation (IFS) symbolwith a period of TV6 has been received). If multiple nodes areready to access the bus and are all waiting for an IFS toelapse, invariable skews in timing components will cause onearbitrary node to detect theIdle condition before all others andstart transmission first. For this reason, all nodes waiting foran IFS will consider an IFS to have occurred if either:1.An IFS nominal period has elapsedor2.An EOF minimum period has elapsedand a rising edgehas been detectedArbitrating devices will all be synchronized during the SOF.Beginning with the first data bit and continuing to the EOF,every transmitting device is responsible for verifying that thesymbol it sent was the symbol which appeared on the bus.Each transition, every transmitting node must decode thesymbol, verify the received symbol matches the one sent, andbegin timing of the next symbol. Since timing of the next sym-bol begins with the last transition detected on the bus, alltransmitters are re-synchronized each symbol. When thereceived symbol doesn’t match the symbol sent, a conflict (bitcollision) occurs. Any device detecting a collision will assumeit has lost arbitration and immediately relinquish the bus. Typi-cally, after losing arbitration, a device will attempt retransmis-sion of the message when the bus once again becomesidle.The definition of 1 and 0 data bits (see Table 2 and discussionunderVPW Symbol Definitions) leads to 0’s having priorityover 1’s in this arbitration scheme. Header bytes are generallyassigned such that arbitration is completed before the firstdata byte is transmitted. Because of the dominance of 0 bitsand the MSB first bit order, a header with the hexadecimalvalue $00 will have highest priority, then $01, $02, $03, etc.An example of two nodes arbitrating for control of the bus isshown in Figure 6.Arbitration also takes place during the IFR portion of a mes-sage, ifmore than one node is attempting to generate aresponse. Arbitration begins with the NB symbol, which fol-lows the EOD and precedes the first IFR byte.For Type 1 and Type 3 messages only, the respondent whichsuccessfully arbitrates for control of the bus produces an IFR.All other respondents abort their IFRs.For Type 2 messages,all respondents which lose arbitrationmust re-attempt transmission at the end of each byte. Eachnode, which successfully responds, eliminates itself from thesubsequent arbitration until all nodes have responded. Thisarbitration scheme limits each respondent to a single byte dur-ing a Type 2 IFR.BreakTo force a message to be aborted before EOF is reached, abreak (BRK) symbol can be transmitted by any node. TheBRK symbol is an active pulse of duration TV5. Reception of abreak causes all nodes to reset to aready-to-receive stateand to re-arbitrate for control following an IFS.HIP7010 Architectural OverviewThe HIP7010 consists of three major functional blocks: theSerial Interface System (SERIAL) block; the State Machine(STATE) block; and the Symbol Encoder/Decoder (SENDEC)block. Transfers between the Host and the HIP7010 are con-trolled by the SERIAL block, while transfers between theJ1850 bus and the HIP7010 are handled by the SENDECSOFHEADER....DATANCRCEODNBINFRAMERESPONSEEODEOFFIGURE 5.J1850 MESSAGE WITH IN-FRAME-RESPONSE0TRANSMITTERA0000010TRANSMITTERJ1850BBUS001COLLISION DETECTED BY BIFSSOFHEADERDATA1...DATANCRCEOFFIGURE 6.TWO NODES ARBITRATING FOR CONTROL OF J1850 BUS9
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HIP7010block. The STATE block controls the flow of all data betweenthe SERIAL and SENDEC blocks. The STATE block also con-trols Host/HIP7010 handshaking, automatic J1850 bus arbi-tration, break recognition, CRC checking, and many otherfeatures. In addition to the three major blocks the HIP7010includes CRC generator/checker hardware, a Status/ControlRegister, and a Timing generator.Most Host micros which include a synchronous serial inter-face, operate their interface in a manner compatible with theHIP7010s implementation. The result of each 8-bit SERIALtransfer is that the contents of the HIP7010s shift registerand the Host’s shift register have effectively been “swapped”.SERIAL Bus TimingThe SCK output of the HIP7010 is used to synchronize themovement of data both into and out of the device on its SINand SOUT lines. As stated above, the Host and the HIP7010are capable of exchanging a byte of information during asequence of eight clocks generated on the SCK pin. Therelationship between the clock signal on SCK and the dataon SIN and SOUT is shown in Figure 7.At least tLEAD prior to each series of eight clocks, the SAC-TIVE output of the HIP7010 is driven low. SACTIVE remainslow until a minimum oftLAG after the last clock transition.When interfacing to a CDP68HC05 SPI compatible Host, theSACTIVE output would normally be connected to the SS inputof the Host. The trailing edge of the SACTIVE signal can alsobe used as a flag to Hosts which don’t automatically recognizethe transfer of a serial byte.The quiescent state of SCK is low. Once a transfer is initi-ated, the rising edge of each SCK pulse places the next biton the SOUT line and the falling edge is used to latch the bitinput on SIN.The Host must adhere to this same timing, by meeting the inputsetup time requirements of SIN valid before the trailing edge ofSCK (seeElectrical Specification for details) and latchingthe SOUT data on the same edge. When interfacing theHIP7010 to a CDP68HC05 SPIcompatible Host, the SPI inter-face should be programmed with CPHA = 1 and CPOL = 0.At all times, other than during an actual SERIAL transferbetween the HIP7010 and its Host, the SCK and SOUT pinsare held in a high impedance state. This allows other devicesconnected to the Host via the SERIAL bus to be accessedwhen the HIP7010 is not transferring data. Utilization of theSERIAL bus by the HIP7010 is less than 5%, leaving signifi-cant bandwidth for other transfers. When held in the highimpedance state, a pair of integrated pull-down devices on theSCK and SOUT pull the pins to ground, if they are not drivenby another source. SeeApplications Information for adetailed discussion of SERIAL bus utilization.Timing GeneratorThe timing generator, as its name suggests, generates allinternal timing pulses required for the SERIAL, SENDEC,STATE, and CRC circuits. The CLK input pin is appropriatelydivided to produce an internal 2MHz clock which results in a1MHz SERIAL transfer rate and VPW J1850 symbol timingwith 1µs accuracy. The CLK pin of the HIP7010 can be drivenwith a variety of common microcontroller frequencies. Fre-quency selection is accomplished via three bits in the Sta-tus/Control register. SeeStatus/Control Register for moredetails.The Serial Interface (SERIAL) SystemOverviewThe SERIAL system handles all interface between the Hostmicrocontroller and the HIP7010. The SERIAL system isdesigned to interface directly with the Serial Peripheral Inter-face (SPI) systems of the Intersil CDP68HC05 family of micro-controllers. Identical interfaces are found on the 68HC11 andHC16 families. Compatible systems are found on most popu-lar microcontrollers.Serial data words are simultaneously transmitted andreceived over the SOUT/SIN lines, synchronized to the SCKclock stream. The word size is fixed at 8-bits. A series ofeight clocks is required to transfer one word. With the excep-tion of Status/Control Register transfers (described later), allSERIAL transfers use a single eight bit shift register withinthe HIP7010. The serial bits are “shifted out” on the SOUTpin, most significant bit (MSB) first, from the shift register. Aseach bit shifts out one end of the shift register, the data onthe SIN input pin is, usually, shifted into the other end of thesame shift register. After eight clocks, the original contents ofthe shift register have been entirely transmitted on the SOUTpin and replaced by the byte received on the SIN pin.SACTIVESCKSCKNORMALLYLOWMSB654321LSBINTERNALSTROBEFORLATCHINGDATAINHIP7010SOUTMSB654321LSBSINMSB654321LSBFIGURE 7.SERIAL BUS TIMING10
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HIP7010SERIAL Bus TransfersThe HIP7010 is always configured as a SERIAL “master”. Asa master, the HIP7010 generates the transfer-synchronizingclock on the SCK pin, transmits data on the SOUT pin, andreceives data on the SIN pin.Whenever the HIP7010 receives a complete byte from theJ1850 bus via theVPWIN line, it automatically initiates anunsolicited SERIAL transfer. The unsolicited transfer trans-mits the received (or reflected) byte to the Host and, if in themidst of transmitting a message, retrieves the next byte fromthe Host. While these unsolicited transfers are, strictlyspeaking, asynchronous to the Host’s activities, there arewell defined rules which govern the minimum time betweenunsolicited transfers (i.e., no two unsolicited transfers canoccur in less time than it takes to transfer one J1850 byte (8x 64 = 512µs). SeeApplications Information for moredetails.In addition to the unsolicited transfers which are based onreceipt of incoming J1850 messages, the Host can initiatecertain transfers in a more synchronous fashion.Handshak-ing between the Host and the HIP7010 is provided by theByte Ready (RDY) and Request Status (STAT) pins. Thesetwo pins are driven by the Host and trigger the HIP7010 toinitiate one of the two, unique,solicited SERIAL transfers.The Byte Ready (RDY) line is the first of two handshakinginputs from the Host. Each rising edge on the RDY pin signi-fies that the Host has loaded a byte into its serial transmitregister and the HIP7010 can retrieve it. If the J1850 bus isavailable (i.e., IFS has elapsed) the rising edge of RDY isinterpreted as signalling the first byte of a new message. TheHIP7010 immediately performs a solicited SERIAL transferto load the first byte. Prior to performing the transfer, theHIP7010 drives the J1850 bus high to initiate an SOF sym-bol. The SOF is then followed by the eight symbols whichrepresent the transferred byte. If a J1850 message isalready in progress, the rising edge of RDY is interpreted assignalling that the next byte of the message or of an IFR isready to be transferred from the Host. The HIP7010 will ini-tiate the transfer, as an unsolicited transfer, when conditionson the J1850 bus warrant the transfer (i.e., when the previ-ously retrieved byte has been completely transmitted on theJ1850 bus or after EOD for an IFR).While the rising edge of RDY is used to notify the HIP7010that the Host is ready to supply the next byte, the level ofRDY following the actual serial transfer provides additionalinformation. Figure 1 depicts the use of RDY. By driving theRDY line high and returning it low before the transfer hasbeen completed, the HIP7010 will detect a low. This isreferred to as ashort RDY. If the RDY line is brought highand held high until the transfer is complete, a high level isdetected by the HIP7010. This is referred to as a long RDY.A short RDY signals a normal transfer, but a long RDY hasspecial significance. A long RDY indicates that the byte cur-rently sitting within the Host is the last byte of a message or ofan IFR. When transmitting the body of a message or a Type 3IFR the HIP7010 will automatically append the CRC after thebyte for which the long RDY was used. When responding witha Type 1 or Type 2 IFR the response is a single byte, and assuch it is always the last byte. For sake of consistency theHIP7010 requires a long RDY for Type 1 and Type 2 IFRs.SeeStatus/Control Registerand Application Informationfor more details.The other handshaking input is the Request Status/Control(STAT) input pin. STAT is used by the Host microcontroller toinitiate an exchange of the Host’scontrol byte and theHIP7010’sstatus byte. A low to high transition on the STATinput signals the HIP7010 that the Host has placed a controlword in it’s serial output register and is ready to exchange itwith the HIP7010’s status word. The HIP7010 will generatethe eight SCKs for the solicited transfer as soon as feasible.To avoid confusion with the transfer of a received J1850byte, STAT should generally be pulsed shortly after receivingeach data byte from the HIP7010. This technique is safe,because once a J1850 message byte has been receivedfrom or sent to the HIP7010, another unsolicited transfer isguaranteed not to happen for at least 500µs. A Control/Sta-tus byte transfer should also be performed in response toeach high to low transition on theIDLE line. SeeApplica-tion Information for more details.Status/Control RegisterThe Status/Control Register is actually a pair of registers:the Status Register and the Control Register. When the Hostinitiates a Status/Control Register transfer by raising theSTAT input, the HIP7010 sends the contents of the StatusRegister to the Host and simultaneously loads the Controlregister with the byte received from the Host.Status RegisterThe Status Register contains eight, read-only, status bits.7EOD6MACK504FTU34X2CRC1ERR0BRKB7, EODWhen an EOD symbol has been received onVPWIN and an IFR byte is received from theJ1850 bus, the End-of-Data flag (EOD) is set, dur-ing the unsolicited transfer of the byte from theHIP7010 to the Host. EOD remains set, until theunsolicited transfer of the first byte of the nextframe.EOD can be used to distinguish the IFR portion ofa frame from the message portion.EOD is cleared by reset.B6, MACKIf MACK (Multi-byte ACKnowledge) is high, eitherthe MACK control bit has been set during a previ-ous Status/Control Register transfer or a long nor-malization bit has been received following an EOD.When both MACK is set and the EOD flag (see B7,EOD) is set, the most recent data byte transferredis part of a Type 3 IFR.The value of MACK is only relevant if EOD = 1.MACK remains set until the unsolicited transfer ofthe first byte of the next frame.MACK is cleared by reset.11
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HIP7010B5, 0B4, FTUBit 5 of the Status byte is not used and will alwaysread as a 0.When First Time Up (FTU) is high, it indicatesthat a reset has occurred since the last Sta-tus/Control Register transfer. FTU is high duringthe first Status/Control Register transfer after areset and low thereafter.FTU can be used to recognize that a Slow ClockDetect reset has occurred or to ensure that a Sta-tus/Control Register transfer has been success-fully completed since the last reset.B3, 4XThe 4X status flag indicates that the 4X mode bithas been set in the Control Register. This bitreflects the contents of the Control Register notthe current mode of the HIP7010’s SENDEC. TheSENDEC only changes modes synchronouslywith an edge detected on theVPWIN pin. Seedescription of the 4X control bit for details. 4X iscleared by reset and the trailing edge of a break.Control RegisterThe Control Register contains eight, write-only, control bits.The PD, NXT, MACK, and ACK bits can only be set high;they are cleared by hardware under specific conditions. Theother four bits can be both set and reset by the Host. All bitsin the Control Register are cleared by reset.7ACK6MACK5NXT4PD34X2DS21DS10DS0B7, ACKSetting the Acknowledgment (ACK) bit signals theHIP7010 that, following the EOD, an IFRresponse is to be sent. Once set, the ACK bit can-not be cleared by the Host. ACK is cleared uponsuccessful transmission of the IFR or at the nextIdle.The ACK bit can be set anytime prior to 135µsafter the final byte (the CRC) of a message. Thefirst IFR byte must be loaded into the Host’s serialoutput register, and the RDY line setafter theHIP7010 transfers the next-to-last byte to theHost, andbefore the HIP7010 transfers the lastbyte (CRC) of the J1850 message to the Host.When the CRC byte is sent to the Host from theHIP7010, the IFR byte will be simultaneouslyloaded into the HIP7010.To send a single byte (Type 1 or Type 2) IFR theHost must leave MACK (B6 of the Control Regis-ter) low and use the long RDY line format.When sending a single byte (Type 1 or Type 2)IFR, the possibility of losing arbitration exists. Inthe case of a Type 1 IFR no further action shouldbe taken. The standard protocol for handling lossof arbitration during a Type 2 IFR is to re-attemptthe transmission until successful. To ensureproper transmission of the IFR the Host mustrepeatedly load it’s serial output register with thedesired IFR byte, and set RDY (using the shortformat), until the IFR has been properly receivedback. There is no danger of inadvertently sendingthe IFR byte twice. The HIP7010 monitors thearbitration results and will transmit the IFR byteonly once. The ACK bit is automatically clearedupon the first successful transmission, thus pre-venting a second transmission. The Host controlswhen the ACK bit is set. During normal operationthe Host must only set ACK once per IFR.To send a Type 3 IFR the Host must set MACKhigh and use the short format of the RDY for allbytes except the last, when the long format isused. A CRC will automatically be appended tothe last byte of a Type 3 IFR. A Type 3 IFR, con-sisting of a single byte plus CRC, can be createdby setting MACK high and using the long RDY lineformat for loading the single data byte.When sending a Type 3 IFR, the possibility of los-ing arbitration during the IFR also exists. In thecase of Type 3 IFRs, once arbitration has beenB2, CRCThe CRC Error flag (CRC) is set when a CRCerror has been detected in the current frame.CRC is cleared by reset and at the conclusion ofthe Status/Control Register transfer.B1, ERRThe Error flag (ERR) is set when an illegal symbolor other, non-CRC error has been detected on theVPWIN pin. Following are some of the many errorswhich will cause ERR to be set:1. An illegal sym-bol, (i.e., a symbol other than a TV1, TV2, or Breakin the middle of a data byte); 2. Receipt of a trun-cated byte (i.e., less than 8 symbols); 3. The Hostattempting to initiate a message more than 96µsafter the IDLE line goes high; 4. An improperlyframed message (i.e., SOF not equal to TV3,wrong EOD, EOF, or NB widths); 5. Failure by theHost to use the long form of RDY to indicate thelast byte of a message; 6. An attempt by the Hostto transmit a single byte (Type 1 or Type 2) IFR bysetting ACK but without using the long form of RDYfor the byte transfer; 7. Setting the Host assertingSTAT during a data byte transfer; 8.A transitionhas occurred on the VPWOUT pin and thereflected transition has not been detected onVPWIN (echo fail).ERR is cleared by a reset and at the conclusionof the Status/Control Register transfer.B0, BRKThe break flag (BRK) is set on the first rising edgeofVPWIN after a BRK symbol has been detectedon the J1850 bus. If the Host was transmitting orhas a message to transmit, it should re-arbitratefor the bus following an IFS (IDLE goes low).BRK automatically clears the 4X mode of the SEN-DEC and resets the 4X bit in the Status byte.BRK is cleared by a reset or at the conclusion ofthe Status/Control Register transfer.12
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HIP7010lost the Host no longer needs to continue transmit-ting bytes. As in the case of Type 2 IFRs, the Hostcannot know arbitration has been lost until after thenext byte to transmit has been loaded. Again, thereis no danger of sending extra bytes because theHIP7010 automatically suspends transmissionsonce arbitration is lost.B6, MACKThe Multi-byte Acknowledge (MACK) bit, in con-junction with the ACK bit, signals the HIP7010 that,following the EOD, a Type 3 IFR with CRCresponse is to be sent. Once set, the MACK bitcannot be cleared by the Host. MACK is clearedupon detection of an Idle following the transmis-sion of the IFR. Setting MACK without also settingACK will result in no IFR being transmitted.The MACK bit can be set anytime prior to 135µsafter the final byte (the CRC) of a message. Thefirst IFR byte must be loaded into the Host’s serialoutput register, and the RDY line setafter theHIP7010 transfers the next-to-last byte to the Host,andbefore the HIP7010 transfers the last byte(CRC) of the J1850 message to the Host. Whenthe CRC byte is sent to the Host from theHIP7010, the first IFR byte will be simultaneouslyloaded into the HIP7010. To send a Type 3 IFR theHost uses the short format of the RDY for all bytesexcept the last, when the long format is used.Setting the MACK bit in the Control Register is notimmediately reflected in the MACK bit of the StatusRegister. The status bit is updated following eachdata transfer.B5, NXTIf the Wait for Next Idle (NXT) bit is asserted highduring a Status/Control Register transfer, theHIP7010 State Machine is re-initialized to a “waitfor Idle” state. The VPWOUT pin is driven low andtheIDLE pin is reset high. Activity on theVPWINpin is ignored until a valid Idle is detected. WhenNXT is asserted theIDLE pin will go high for a min-imum of 6µs. If the bus is Idle at the end of the 6µsperiod,IDLE will be driven low and the HIP7010will be ready to transmit or receive a J1850 mes-sage. If the bus is not Idle, current activity on theVPWIN pin is ignored until a new Idle is detected.The NXT bit enables the Host to ignore the bal-ance of the current message. Unsolicited transfersfrom the HIP7010 are guaranteed not to occur untilthe next Idle occurs. Transfers resume followingthe first byte of the next message.B4, PDThe Power-Down (PD) bit is used to halt internalclocks to the HIP7010 to minimize power. A lowlevel on theVPWIN, a low to high edge on theSTAT pin, or a high level on the RDY pin will clearthe PD bit and normal HIP7010 functions willresume.PD can only be set if the IDLE pin is low or duringthe first Status/Control Register transfer followinga reset. The CLK input is internally gated off atthe end of the Status/Control Register transfer.There are two situations which can cause the PDbit to be cleared prematurely: 1. The RDY input ishigh during the Status/Control Register transfer(since this is under control of the Host it should beavoided); 2. A noise pulse of less than7µs dura-tion occurs on theVPWIN line.If either of these situations occur, the PD will becleared, the HIP7010 will resume operating andlook for a valid edge onVPWIN, RDY, or STAT. Ifno valid edge has occurred the HIP7010 will recy-cle to the top of the State Machine, pulsingIDLEhigh for a minimum of 2µs. It is the responsibilityof the Host to monitor theIDLE pin after settingPD to ensure that the POWER-DOWN mode hasbeen successfully entered.SeeEffectsof Resets and Power-Down for adetailed discussion of the Power-Down mode.B3, 4XSetting the High Speed Mode (4X) bit causes theHIP7010’s SENDEC to decode symbols receivedon the J1850 bus at 0.25X the normal durations.The 4X mode is designed to allowed receipt of mes-sages at 4X the normal J1850 rate. It is intended formanufacturing and diagnostic use, not normal“down the road” vehicle communications. Transmis-sion is inhibited while the 4X bit is set.The 4X bit can only be written to when the IDLEpin is low or during the first Status/Control transferfollowing a reset. Setting 4X is inhibited during thefirst Status/Control after a Break. The SENDECbegins operating at the 4X rate upon receipt of thenext edge. The system must provide sufficient timefor all nodes to detect the Idle, interpret the “shift tohigh speed” message, and change their mode bitsbefore issuing a high speed SOF.4X is cleared by receipt of a Break symbol on theJ1850 bus and it can also be cleared by perform-ing a Status/Control Register transfer with the 4Xbit low. When cleared via a Status/Control Regis-ter transfer,IDLE must be low. The SENDECreverts to operating at the normal rate uponreceipt of the next edge.4X mode cannot be utilized for transmitting mes-sages.VPWOUT is disabled in hardware, but theState Machine will attempt to transmit if RDY isstrobed. It is the Host’s responsibility to refrainfrom transmitting in 4X mode.B2, DS2, B1, DSI, B0, DSIThe three Divide Select bits (DS2-DS0) are usedto match the internal clock divider with the inputfrequency on the CLK input to produce therequired 2MHz internal time base. Table 3 showsthe clock divide values and nominal input fre-quency for the eight combinations of DS2-DS0.13
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HIP7010During a HIP7010 reset caused by a POR, a SlowClock Detect, or a low on the RESET line, theClock Divider is inhibited and a fixed divide-by six-teen clock divider is activated. This is greater thanany selectable divide-by and guarantees properoperation of the SERIAL interface for all valid oper-ating frequencies (although the transfer rate will bebelow 1MHz). The CLK divide-by remains at six-teen and operation of the HIP7010 is suspendeduntil the Host performs a Status/Control Registertransfer to set the proper divide value. The StateMachine and SENDEC are held in a reset state(passive) until the first Status/Control Registertransfer has been completed. This ensures propersetting of the divide selects prior to generation orreceipt of any symbols.TABLE 3. DS2-DS0 CLOCK DIVIDER SELECTIONSCLK INPUTFREQ. (MHZ)24 (Note 1)1220 (Note 1)1016 (Note 1)842INTERNALHIP7010 CLKDIVIDE-BY1261058421pin and input, as a digital signal, on theVPWIN pin. Thesetwo lines must be connected through a bus transceiver (suchas the Intersil J1850 Bus Transceiver HIP7020) to the singlewire J1850 bus. The transceiver is responsible for generatingand receiving waveforms consistent with the physical layerspecifications of J1850. In addition, the transceiver is respon-sible for providing isolation from bus transients.Every symbol sent out on the VPWOUT is, in effect, invertedandreflected back on theVPWIN pin after some finite delaythrough the transceiver. In actuality, only active symbols areguaranteed to be reflected unchanged. If the transmittedsymbol is passive and another node is simultaneously send-ing an active symbol, the active symbol will dominate andpull the bus to a high level. The SENDEC circuitry includes a3-bit digital filter which effectively filters out noise pulses lessthan 7µs in duration.The STATE logic transfers data bits between the SERIALsystem and the SENDEC, and handles addition of requiredframe elements such as the SOF symbol and the CRC byte.When transmitting bytes, bits are taken from the SERIALshift register and translated into the required symbols, bit bybit.Timing of each symbol is calculated from the lasttransition on theVPWIN line which keeps all nodes on theJ1850 bus “in synch” during arbitration periods.Decoding of received symbols is automatically performed bythe SENDEC. The decoded symbol is translated to a 0 or 1value and transferred by the STATE logic into the SERIAL shiftregister. As each symbol is decoded, it is shifted into theSERIAL shift register and, if transmitting, the next bit to transmiton the J1850 bus is shifted out. Once an entire byte has beenloaded into the SERIAL shift register the STATE logic automati-cally generates an unsolicited transfer of the byte to the Host.Whenever the SENDEC is transmitting, it is simultaneouslymonitoring the “reflected” symbol on theVPWIN line. Ateach transition the reflected symbol is read and compared tothe sent one. If the reflected symbol doesn’t match the sym-bol sent, a collision has occurred and the HIP7010 automati-cally disables transmissions until the next Idle/IFR period. Ifthere was no collision, the HIP7010 continues transmittinguntil the entire byte has been sent. Once the byte has beensent, a full byte will also have been reflected and received bythe HIP7010. As discussed above, the HIP7010 initiates atransfer of the received byte to the Host, which allows theHost the opportunity to compare the sent and reflectedbytes, and to transfer the next byte of the message.In addition to features already discussed, the SENDECincludes, noise detection,Idle bus detection, a wake-up facil-ity, “no echo” detection, and a high speed receive mode. Sym-bol timing is based on the main CLK input. The programmableprescaler, controlled by the DS0-DS2 bits in the Control Reg-ister, allows proper SENDEC operation with a variety of CLKinput frequencies (seeDS2-DS0 underStatus/Control Reg-ister for prescaler details). The high speed mode is a J1850extension which allows production and/or maintenance equip-ment to transmit messages at 4X the normal 10.4Kbps rate(see4X under Status/Control Registerfor prescaler details).Software algorithms can be implemented in the Host to pro-vide message buffering and filtering and other needed fea-DS200001111NOTE:DS100110011DS0010101011.Invalid operating frequency.Once DS2-DS0 have been set following a reset,they must not be altered. Each Status/Control Reg-ister transfer must properly reassert the sameDS2-DS0 values to maintain proper clocking.Selecting a DS2-DS0 combination which is too lowfor the given CLK frequency can result in loss ofSERIAL communications, due to excessive clock-ing rates. In such instances the only recoverymechanism is to force a HIP7010 reset by pullingthe RESET input low, interrupting the CLK input, orperforming a power-on reset. A well behaved Hostwill avoid changes to DS2-DS0. System fault toler-ance can be maximized by using the lowest possiblefrequency at the CLK input.Power-down doesnot reset DS2-DS0, allowingrapid “wake-up” from the Power-down state.Symbol Encoder/Decoder (SENDEC)OperationThe Symbol Encoder/Decoder (SENDEC) hardware inte-grated in the HIP7010 handles generation and reception ofJ1850 messages on a symbol by symbol basis. Symbols areoutput from the SENDEC, as a digital signal, on the VPWOUT14
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HIP7010tures to create a complete J1850 VPW node. See theApplications Information section for typical algorithms.Detection of a Break on the J1850 bus causes an interruptinput to STATE which causes the HIP7010 to cease any cur-rent transmission and enter await forIDLE mode.The State Machine Logic (STATE)The State Machine Logic (STATE) of the HIP7010, is asequential state machine implementation of the J1850 VPWdata link layer. STATE controls data flows within the HIP7010and between the Host and the J1850 bus.When receiving messages, STATE monitors the input fromthe SENDEC, building byte sized chunks to send to the Host.As each byte is assembled, STATE transfers the result to theHost via the Serial interface, as an unsolicited transfer. Uponreceipt of a complete message (recognized by EOD), STATEverifies both the CRC and bit counts and sets appropriateStatus Register flags.When transmitting messages from the Host to the J1850bus, STATE waits for the first RDY input transition, afterwhich it retrieves the first byte from the Host and initiates themessage with an SOF. Each bit of the Host’s message byteis transferred to the J1850 bus via the SENDEC. When thetransfer of a byte is complete, STATE checks for a new RDY(if there is one), retrieves the associated byte, and againtransfers the byte via the SENDEC to the J1850 bus. Afterretrieving each byte from the Host, STATE checks to see ifthe long RDY format was used, which indicates this is theend of the Host’s message. If the message is complete,STATE transfers the final byte to the J1850 Bus and then,automatically, sends the computed CRC to the J1850 bus.Throughout the transmission of a message from the Host tothe J1850 bus, STATE monitors the symbols reflected backvia the SENDEC and handles all bus conditions such as lossof arbitration, illegal bits, Break, bad CRC, and missing bits.STATE also catches Host errors including failure to set theRDY line in time for the next byte transfer, attempting to ini-tiate a new message more than 96µs afterIDLE has goneaway, and inappropriate use of the STAT line (i.e., requestinga Status/Control Register transfer during an unsolicitedtransfer of the reflected data).In 4X mode VPWOUT is disabled in hardware, but STATEwill attempt to transmit if RDY is strobed. This results inSTATE clearingIDLE and waiting for the leading edge ofSOF. Since VPWOUT is blocked STATE will only recover ifanother node’s SOF is received or NXT is set. It is the Host’sresponsibility to refrain from transmitting in 4X mode.The Control Register bits influence STATE. If ACK is set,STATE handles sequencing of the requested IFR. The flowconsists of waiting for an EOD, sending the appropriate Nor-malization Bit (Type 1/2 vs Type 3 IFR), transferring the IFRbyte(s) from the Host to the J1850 bus, handling arbitration,and finally adding the CRC to Type 3 IFRs. As with normaltransmissions, STATE contains error handling to react appro-priately to all J1850 bus conditions.Detection of anIdle on the bus causes STATE to set theIDLEpin. STATE clears theIDLE pin upon receipt of a transition ontheVPWIN line or when the Host initiates a new message.Effects of Resets and Power-DownResetsA Power-On reset, a Slow Clock Detect reset, and a low ontheRESET pin all have an identical effect on the operation ofthe HIP7010. All resets are asynchronous andimmediatelydo the following:•VPWOUT is forced low.•The HIP7010 is set toRESTART mode.•The internal divide-by is set to sixteen and held at thatvalue until the RESTART mode ends.•SACTIVE is forced high and SCK and SOUT are set to ahigh impedance state.•The ACK, MACK, NXT, PD, and 4X bits are cleared in theControl Register.•All Status Register bits are cleared (except bit 4, FTU,which is set to a 1).•IDLE is forced high and held high for 17 CLKs after thesource of the reset is removed. After 17 CLKs,IDLE isforced low.IDLE Remains low until 40 CLKs +1.5µs afterthe first Status/Control Register transfer.•The SENDEC is reset, holding the symbol timer at a countof 0 and clearing the 3-bitVPWIN filter to all 0’s, until theRESTART mode ends.•STATE is held in a reset loop until the RESTART modeends. While STATE is in the reset loop, transitions on theRDY pin are ignored.The RESTART mode is entered by any reset and ends whenthe first Status/Control Register transfer has been com-pleted. Upon exiting the RESTART mode the HIP7010enters its normalRUN mode. This is reflected in the clearingof the FTU bit of the Status Register.When the RESTART mode ends and the RUN mode begins,the internal divide-by is set to the value programmed viaDS2-DS0 in the Control Register. TheIDLE pin is drivenhigh after 40 CLKs, the SENDECs counter andVPWIN filterbegin operating, and STATE begins monitoring the outputsof SENDEC looking for an Idle.The HIP7010 remains in RUN mode until another resetoccurs or the POWER-DOWN mode is entered.Power-DownThePOWER-DOWN modeof the HIP7010 is entered by set-ting the PD bit in the Control Register (seeControl Registerfor more information). Setting the PD bit can only be donewhen the HIP7010 is driving the IDLE pin low. Once set, thePD forces the HIP7010 to the POWER-DOWN mode 2µsafter the completion of the Status/Control Register transfer.While in the POWER-DOWN mode the CLK input is internallygated off, minimizing power dissipation. The Slow ClockDetect is inhibited while in the POWER-DOWN mode.A return to the RUN mode from the POWER-DOWN mode isnormally caused by a low level on VPWIN. During POWER-15
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HIP7010DOWN the input signal is not filtered via the7µs digital filter (noclocks are available to drive the digital filter). Without filtering inplace it is possible for a noise spike, less than7µs wide, towake-up the HIP7010. In such a case the HIP7010 returns toRUN mode, but the spike is rejected by the now running, digitalfilter and the bus continues in the Idle state. To notify the Hostwhen such spurious wake-ups occur, STATE monitors the out-put of the digital filter and if, within 12µs after the wake-up, thedigital filter doesn’t indicate VPWIN is low, STATE pulses IDLEhigh for 2µs and then drives it low again. The HIP7010 is now inthe RUN mode. It is the responsibility of the Host to recognizethe pulse on the IDLE pin and set PD in the Control Register toreenter the POWER-DOWN mode. In systems where the Hostdirectly monitors the VPWIN pin during POWER-DOWN, moni-toring the IDLE pin may not be necessary.One of the mechanisms to exit POWER-DOWN is to provide ahigh level on the RDY pin. Since this is a level sensitive eventthe HOST must ensure that RDY is not already high when thePD bit is set in the Control Register. A well behaved Host willcontrol this properly. However, in the event RDY is high whenPD is set, a 12µs time-out will occur similar to that describedfor waking-up with a noise pulse onVPWIN. After the time-out, IDLE will pulse high for 2µs then low again. The Hostshould react to this pulse appropriately.Test Block 1Once the TEST Sequence has been entered,IDLE will golow. OnceIDLE has gone low, each time that RDY is pulsed(with theshort form of RDY) it will result in an exchange ofdata between the Host’s SPI register and the BLIC’s dataregister. Following a reset, the BLIC’s data register will con-tain $00. For all other exchanges during the TEST sequencethe BLIC will give back to the Host the byte it supplied duringthe prior exchange. During each exchange theIDLE pin willgo high and return low when the exchange is complete. Fol-lowing each exchange the Host should query the BLIC’s Sta-tus Register by pulsing STAT. All flags should be clear.This section of the TEST Sequence not only checks properoperation of the Serial Register of the BLIC, the TEST,IDLE,RDY, and STAT pins but it also does an internal verification of>70% of the inputs of the BLIC’s State Machine.Test Block 2The TEST Sequence can now be exited by lowering TESTand setting the NXT bit in the Control Register, or the secondportion of the TEST Sequence can be invoked by leavingTEST high and doing one last transfer of an $FF using thelong form of RDY. Following this exchange the BLIC will senda high TV2 followed by a low TV1 followed by a high noisepulse (to prevent bus interference the HIP7020 Transceivershould be in Loopback Mode during this sequence). Followingthe noise pulse, the State Machine will return to the start ofthe TEST Sequence andIDLE will go low. If all tests were suc-cessful the ERR bit should be set in the Status Register (dueto the noise pulse) and the Serial Data Register should havebeen set to $00 (done following the TV1). This can be verifiedby doing a STAT transfer followed by a RDY transfer. Normallythe TEST Sequence would now be exited by lowering TESTand setting NXT in the Control Register.The second block of the TEST Sequence boosts the numberof tested State Machine inputs to over 90%.Using TEST for Loopback OperationWhenever TEST is high the BLIC is operating in “loopback”mode. This provides a convenient means to isolate faultsbetween the Bus, the Transceiver, and the BLIC. It also sim-plifies extended testing of the BLIC’s Symbol Genera-tion/Detection, Message Handling and CRCGeneration/Detection logic.To isolate Module faults from Bus faults: place the HIP7020Transceiver in loopback (by loweringLBE) and send a mes-sage. Verify the message and CRC are properly reflectedand the Status bits are clear. If all are good, the fault can beassumed to be on the output of the Transceiver or on the busitself. If all are not good, leave the Transceiver in loopbackand place the BLIC in loopback (to place the BLIC in loop-back, wait forIDLE to go low and then raise TEST) and senda message again verifying that the message and CRC areproperly reflected and that the Status bits are clear. If all aregood the Transceiver or VPWOUT or VPWIN of the BLIC arefaulty. If all are not good the fault is either internal to the BLICor is a problem with the Host/BLIC interface. If the TESTSequence can be properly run the problem has been iso-lated to an internal fault of the HIP7010.Test ModeOverviewWhen the TEST Pin of the HIP7010 is driven high, it modi-fies the operation of the BLIC in two ways:1.It inhibits receipt of bus signals on theVPWIN pin andinternally routes the VPWOUT signal to the VPWINinput.During this “loopback” mode of operation theVPWOUT pin will continue to operate.The State Machine which controls the operation of theHIP7010 is extended to include a special TEST Sequence.The TEST Sequence can only be entered from one loca-tion in the normal State Machine flow. This point can con-veniently be reached following reset of the BLIC or bysetting the NXT bit in the BLIC’s Control Register.2.Entering the TEST SequenceEntry into the TEST Sequence of the BLIC’s State Machinerequires that the TEST pin is highand the State Machine isat it’s “start”. The State Machine will always pass through itsstarting point at certain identifiable times:1.2.3.4.Following the first Status/Control Transfer after a ResetFollowing completion of a J1850 message (i.e., after EOD)Following abortion of a message frame due to noise, badsymbol, bad CRC, receipt of a Break, etc.Following setting of the NXT bit in the Control RegisterAs are all states, the starting point is a transitory state. Onceentered, the State Machine will remain at its start only untilthe bus has been low for a TV4 min (i.e., EOF, 239µs). Toensure proper synchronization, the TEST Sequence shouldgenerally be entered only after a Reset or after setting theNXT bit in the BLIC’s Control Register.16
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HIP7010Error HandlingThe Status RegisterThe various flags in the Status Register can be used todetect many errors which would typically be generated bysystem noise, errant nodes, or improperly designed Hostcode. It is good practice to maintain error counts in the Hostfor service reporting and to trigger recovery procedures.Whenever the ERR or CRC are set in the Status Register,the current message is aborted and the BLIC enters a “waitfor Idle” mode. Following is a detailed listing of the errorswhich can be trapped by reading the Status Register.Errors Which Set the ERR FlagThe ERR flagwill be set whenever:1.2.A noise pulse (i.e., a symbol less than TV1MIN) is received- including while waiting for an Idle.An illegal symbol, (i.e., a symbol other than a TV1, TV2, orBreak) is received in the middle of a message which isbeing received or transmitted.A message with an incomplete byte is received (i.e., totaldata bit count not equal to 0 modulo 8).The Host attemptsto initiate a message more thanTV2MIN (96µs) after the IDLE line goes high.An improperly framed message is received (i.e., SOF notequal to TV3, wrong EOD, EOF, or NB widths).An SOF occurs less than TV4 after the end of a Type 0message.While transmitting a message that the Host fails to assertRDY prior to a data transfer.The Host fails to use the long form of RDY to indicate thelast byte of a message.The Host attempts to transmit an IFR by setting ACK butfails to assert RDY prior to 135µs after the CRC.waiting for an Idle. That is to say that the current messageis discarded. “Waiting for Idle” happens following: Reset,setting of NXT, any error which sets ERR (except assertingSTAT during a data transfer), a CRC error, a Break, or fol-lowing EOD after a Type 1, 2, or 3 message.3.After aType 1, 2, or 3 message, a second NB or an SOFfor a new message received before EOF will be ignored.Any following symbols will be ignored until EOF isdetected. This implies that if two messages appear on thebus with less than an EOF between them the second mes-sage will be ignored, but no error generated. Similarly, if anIFR is attached to a message after EOD and a second NBis generated an EOD after the initial IFR, the NB and allsucceeding symbols will be ignored until Idle is detected.No error will be generated.Errors Which Set the CRC FlagThe CRC flagwill be set whenever:1.2.3.The CRC check byte of the body of any type message isbad (any IFR will be aborted/ignored).All components of a Type 3 message frame are goodexcept the IFR’s CRC check byte.A zero length message (SOF followed by EOD) is received.3.4.5.6.7.8.9.Host Time-outsOther classes of errors, including catastrophic failure of theJ1850 bus, can sometimes only be detected by monitoringthe time between successfully received messages and/orthe delay betweenIDLEs - when the time exceeds some limitthe Host assumes that a bus fault exists and attempt to iso-late the cause (perhaps using the TEST pin) and performrecovery/”limp home” actions.Error RecoveryIf errors are detected on multiple occasions or a Host time-out occurs, the BLIC should be reset by loweringRESET orstopping the CLK (or setting NXT if theRESET or CLK pin isnot controllable), and DS2-0 should be re-initialized in theControl Register.If resetting the BLIC doesn’t eliminate the error condition, atest procedure should be entered using TEST and loopbackmodes.10.The Host attempts to transmit a single byte (Type 1 orType 2) IFR by setting ACK but without using the longform of RDY for the firstbyte transfer.11.The Host asserts STAT during a data byte transfer.12.While transmitting, a Status/Control Register transfer is inprogress when a data byte transfer begins.13.A transition has occurred on the VPWOUT pin and thereflected transition has not been detected onVPWIN(echo fail).14.A failure occurs during TEST mode.15.Alow pulse <7µs occurs onVPWIN during the POWER-DOWN mode.Errors WhichDon’t Set the ERR FlagDue to various considerations, some errors which the usermight otherwise expect to be trapped by ERR are not. Theseinclude:1.2.A zero length message (SOF followed by EOD) will not setERR, but will set the CRC flag.Any symbol, other than a noise pulse, is ignored while17
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HIP7010PA36805 MICROCONTROLLEROSCOUTTCAPMOSISCKPA2PA1PA0MISOSINSOUTSCKSACTIVECLKRESETSTATRDYIDLESSHIP7010 BLICVPWINLB ENBATTR/F43VMOVM1C10.1µFC20.01µFRS57KΩJ1850 BUSTRANSCEIVERTXVPWINRX BUS OUTRo10Ω+5VTEST5.1KΩRF BUS IN15KΩC30.01µFGNDJ1850 BUS11KΩ/1KΩRBUS330/3300pFCBUSFIGURE 8.18
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HIP7010Dual-In-Line Plastic Packages (PDIP)NE1INDEXAREA123N/2-B--A-DBASEPLANESEATINGPLANED1B1B0.010 (0.25)MD1A1-C-A2LACLEE14.3(JEDEC MS-001-AA ISSUE D)14 LEAD DUAL-IN-LINE PLASTIC PACKAGEINCHESSYMBOLAA1A2BB1CDD1EE1eeAeBLNMIN-0.0150.1150.0140.0450.0080.7350.0050.3000.240MAX0.210-0.1950.0220.0700.0140.775-0.3250.280MILLIMETERSMIN-0.392.930.3561.150.20418.660.137.626.10MAX5.33-4.950.5581.770.35519.68-8.257.11NOTES44--8-5565-6749Rev. 0 12/93eAeCCeCABSeBNOTES:1.Controlling Dimensions: INCH. In case of conflict betweenEnglish and Metric dimensions, the inch dimensions control.2.Dimensioning and tolerancing per ANSI Y14.5M-1982.3.Symbols are defined in the “MO Series Symbol List” in Section2.2 of Publication No. 95.4.Dimensions A, A1 and L are measured with the package seatedin JEDEC seating plane gauge GS-3.5.D, D1, and E1 dimensions do not include mold flash or protru-sions. Mold flash or protrusions shall not exceed 0.010 inch(0.25mm).6.E andeAare measured with the leads constrained to be per-pendicular to datum-C-.7.eB and eC are measured at the lead tips with the leads uncon-strained. eC must be zero or greater.8.B1 maximum dimensions do not include dambar protrusions.Dambar protrusions shall not exceed 0.010 inch (0.25mm).9.N is the maximum number of terminal positions.10.Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch(0.76 - 1.14mm).0.100 BSC0.300 BSC-0.115140.4300.150-2.54 BSC7.62 BSC10.923.81142.9319
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HIP7010Small Outline Plastic Packages (SOIC)NINDEXAREAHE-B-123SEATING PLANE-A-D-C-Ah x 45o0.25(0.010)MBMM14.15(JEDEC MS-012-AB ISSUE C)14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGEINCHESSYMBOLAA1LMILLIMETERSMIN1.350.100.330.198.553.805.800.250.40148o0o8oMAX1.750.250.510.258.754.006.200.501.27NOTES--9-34--567-Rev. 0 12/93MIN0.05320.00400.0130.00750.33670.14970.22840.00990.016140oMAX0.06880.00980.0200.00980.34440.15740.24400.01960.050BCDEe0.050 BSC1.27 BSCeB0.25(0.010)MCAMBSαA10.10(0.004)CHhLNNOTES:1.Symbols are defined in the “MO Series Symbol List” in Section2.2 of Publication Number 95.2.Dimensioning and tolerancing per ANSI Y14.5M-1982.3.Dimension “D” does not include mold flash, protrusions or gateburrs. Mold flash, protrusion and gate burrs shall not exceed0.15mm (0.006 inch) per side.4.Dimension “E” does not include interlead flash or protrusions. In-terlead flash and protrusions shall not exceed 0.25mm (0.010inch) per side.5.The chamfer on the body is optional. If it is not present, a visualindex feature must be located within the crosshatched area.6.“L” is the length of terminal for soldering to a substrate.7.“N” is the number of terminal positions.8.Terminal numbers are shown for reference only.9.The lead width “B”, as measured 0.36mm (0.014 inch) or greaterabove the seating plane, shall not exceed a maximum value of0.61mm (0.024 inch).10.Controlling dimension:MILLIMETER. Converted inch dimen-sions are not necessarily exact.αAll Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification.Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time withoutnotice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurateand reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties whichmay result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.comSales Office HeadquartersNORTH AMERICAIntersil CorporationP. O. Box 883, Mail Stop 53-204Melbourne, FL32902TEL:(407) 724-7000FAX: (407) 724-7240EUROPEIntersil SAMercure Center100, Rue de la Fusee1130 Brussels, BelgiumTEL: (32) 2.724.2111FAX: (32) 2.724.22.05ASIAIntersil (Taiwan) Ltd.Taiwan Limited7F-6, No. 101 Fu Hsing North RoadTaipei, TaiwanRepublic of ChinaTEL: (886) 2 2716 9310FAX: (886) 2 2715 302920
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