Current-limiting logic interface circuit

专利名称：Current-limiting logic interface circuit发明人：Thierry Castagnet,Olivier Ladiray申请号：US10242518申请日：20020912公开号：US07091633B2公开日：20060815

专利附图：

摘要：A circuit of interface between a logic sensor and a logic input isolation barrier ofa processing circuit, including an element of protection against input overvoltages, acurrent-limiting circuit connected in series between an input terminal and an outputterminal of the interface circuit, and a control stage connected in parallel with the

galvanic isolation element to be controlled to control the logic states thereof, thecontrol stage inhibiting the operation of the galvanic isolation element if the inputcurrent is smaller than a predetermined threshold.

申请人：Thierry Castagnet,Olivier Ladiray

地址：Tours FR,Montlouis sur Loire FR

国籍：FR,FR

代理机构：Wolf, Greenfield & Sacks, P.C.

代理人：Lisa K. Jorgenson,William R. McClellan

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