Dynamically variable precision calculation

专利名称：Dynamically variable precision calculation发明人：グレッグ サドウスキー,ウェイン バールソン申请号：JP2019521000申请日：20171017公开号：JP2019537787A公开日：20191226

专利附图：

摘要：The conversion device (115) converts the operand (110) from a conventionalnumber system representing each binary number of the operand as one bit to a

redundant number system (RNS) operand (210, 215) representing each binary number asa plurality of bits. Convert to The arithmetic logic unit (205) performs an arithmetic

operation on the RNS operand in a direction from the most significant bit (MSB) to theleast significant bit (LSB). The arithmetic logic unit stops performing the arithmeticoperation before performing the arithmetic operation on the target binary numberindicated by the dynamic precision associated with the RNS operand. In some cases, thepower supply (330) provides power to the bit slices (311, 312, 313, 314, 315) in the

arithmetic logic unit, and the clock signal generator (335) supplies a clock signal to the bitslices. I do. [Selection diagram] Fig. 1

申请人：アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド

地址：アメリカ合衆国 ９５０５４ カリフォルニア州、 サンタ クララ、オーガスティン ドライブ ２４８５

国籍：US

代理人：早川 裕司,佐野 良太,村雨 圭介

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