SC16C650BIN40资料

2021-03-12 来源：步旅网

元器件交易网www.cecb2b.com

SC16C650B

5V, 3.3V and 2.5V UART with32-byteFIFOsandinfrared(IrDA) encoder/decoder

Rev. 03 — 10 December 2004

Product data

1.General description

TheSC16C650B is a Universal Asynchronous Receiver and Transmitter (UART)used for serial data communications. Its principal function is to convert parallel dataintoserialdata,andviceversa.TheUARTcanhandleserialdataratesupto3Mbit/s.The SC16C650B is pin compatible with the ST16C650A and it will power-up to befunctionally equivalent to the 16C450. Programming of control registers enables theadded features of the SC16C650B. Some of these added features are the 32-bytereceiveandtransmitFIFOs,automatichardwareorsoftwareﬂowcontrolandinfraredencoding/decoding. The selectable auto-ﬂow control feature signiﬁcantly reducessoftware overload and increases system efﬁciency while in FIFO mode by

automatically controlling serial data ﬂow usingRTS output andCTS input signals.TheSC16C650BalsoprovidesDMAmodedatatransfersthroughFIFOtriggerlevelsandtheRXRDYandTXRDYsignals.On-boardstatusregistersprovidetheuserwitherror indications, operational status, and modem interface control. System interruptsmay be tailored to meet user requirements. An internal loop-back capability allowson-board diagnostics.

The SC16C650B operates at 5V, 3.3V and 2.5V, and the industrial temperaturerange,andisavailableinplasticDIP40,PLCC44,LQFP48,andHVQFN32packages.

2.Features

sssssssssss

Single channel

5V, 3.3V and 2.5V operation5V tolerant inputs

Industrial temperature range (−40°C to +85°C)

After reset, all registers are identical to the typical 16C450 register setCapable of running with all existing generic 16C450 software

Pin compatibility with the industry-standard ST16C450/550, TL16C450/550,PC16C450/550. Software compatible with ST16C650.

Up to 3Mbit/s transmit/receive operation at 5V, 2Mbit/s at 3.3V, and 1Mbit/sat2.5V

32byte transmit FIFO

32byte receive FIFO with error ﬂagsProgrammable auto-RTS and auto-CTSxIn auto-CTS mode,CTS controls transmitterxIn auto-RTS mode, RxFIFO contents and threshold controlRTSAutomatic software/hardware ﬂow controlProgrammable Xon/Xoff characters

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

sssssssss

sssssss

Software selectable Baud Rate GeneratorSupports IrDA version 1.0 (up to 115.2kbit/s)

Four selectable Receive and Transmit FIFO interrupt trigger levelsStandard modem interface or infrared IrDA encoder/decoder interfaceSleep mode

Standard asynchronous error and framing bits (Start, Stop, and Parity OverrunBreak)

Independent receiver clock input

Transmit, Receive, Line Status, and Data Set interrupts independently controlledFully programmable character formatting:x5, 6, 7, or 8-bit characters

xEven, Odd, or No-Parity formatsx1, 11⁄2, or 2-stop bit

xBaud generation (DC to 3Mbit/s)False start-bit detection

Complete status reporting capabilities

3-State output TTL drive capabilities for bi-directional data bus and control busLine Break generation and detectionInternal diagnostic capabilities:

xLoop-back controls for communications link fault isolationPrioritized interrupt system controls

Modem control functions (CTS,RTS,DSR,DTR,RI,DCD).

3.Ordering information

Table 1:Ordering information

Industrial: VCC=2.5V, 3.3V or 5V± 10%; Tamb=−40°C to +85°C.Type numberSC16C650BIA44SC16C650BIB48SC16C650BIBSSC16C650BIN40

PackageNamePLCC44LQFP48HVQFN32DIP40

Descriptionplastic leaded chip carrier; 44 leads

plastic low proﬁle quad ﬂat package; 48 leads; body 7×7×1.4mmplastic thermal enhanced very thin quad ﬂat package; no leads;32terminals; body 5×5×0.85mm

plastic dual in-line package; 40 leads (600mil)

VersionSOT187-2SOT313-2SOT617-1SOT129-1

Product dataRev. 03 — 10 December 20042 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

4.Block diagram

SC16C650BTRANSMITFIFOREGISTERSD0–D7IOR, IORIOW, IOWRESETDATA BUSANDCONTROL LOGIC FLOWCONTROLLOGICTRANSMITSHIFTREGISTERTXIRENCODERINTERCONNECT BUS LINESANDCONTROL SIGNALSRECEIVEFIFOREGISTERSRECEIVESHIFTREGISTERRXA0–A2CS0, CS1, CS2ASREGISTERSELECTLOGICFLOWCONTROLLOGICIRDECODERDDISDTRRTSOUT1, OUT2MODEMCONTROLLOGICINTERRUPTCONTROLLOGICCLOCK ANDBAUD RATEGENERATORINTTXRDYRXRDYCTSRIDCDDSR002aaa602XTAL1RCLKXTAL2BAUDOUTFig 1.Block diagram.939775014451© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product dataRev. 03 — 10 December 20043 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

5.Pinning information

5.1Pinning

42DCD44VCC41DSR40CTS1n.c.6D45D34D23D12D0D5D6D778943RI39RESET38OUT137DTR36RTS35OUT2RCLK10RX11n.c.12TX13CS014CS115CS216BAUDOUT17SC16C650BIA4434n.c.33INT32RXRDY31A030A129A2XTAL118XTAL219IOW20IOW21GND22n.c.23IOR24IOR25DDIS26TXRDY27AS28002aaa603Fig 2.PLCC44 pin conﬁguration.939775014451© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product dataRev. 03 — 10 December 20044 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

40DCD42VCC39DSR38CTS48n.c.n.c.D5D6D7RCLKn.c.RXTXCS012345637n.c.47D446D345D244D143D041RI36n.c.35RESET34OUT133DTR32RTS31OUT2SC16C650BIB4878930INT29RXRDY28A027A126A225n.c.CS110CS211BAUDOUT12n.c.13XTAL114XTAL215IOW16IOW17GND18IOR19IOR20n.c.21DDIS22TXRDY23AS24002aaa604Fig 3.LQFP48 pin conﬁguration.27VCC26DSR32D431D330D229D1D5D6D7RCLKRXTXCSBAUDOUT28D0terminal 1index area1234567825CTS24RESET23OUT22DTR21RTS20INT19RXRDY18A017A1A216002aaa947© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

SC16C650BIBS(top view)XTAL210IOW11n.c.12GND13IOR14Fig 4.HVQFN32 pin conﬁguration (top view).939775014451

Product dataRev. 03 — 10 December 2004

TXRDY15XTAL195 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

D01D12D23D34D45D56D67D7840VCC39RI38DCD37DSR36CTS35RESET34OUT133DTRRX10TX11CS012CS113CS214BAUDOUT15XTAL116XTAL217IOW18IOW19GND20SC16C650BIN40RCLK932RTS31OUT230INT29RXRDY28A027A126A225AS24TXRDY23DDIS22IOR21IOR002aaa605Fig 5.DIP40 pin conﬁguration.5.2Pin description

Table 2:SymbolA0-A2Pin descriptionPinPLCC44LQFP48HVQFN32DIP4031, 30,2928, 27,2618, 17, 1628,I27, 26Register select. A0-A2 are used during read and writeoperations to select the UART register to read from or writeto. Refer toTable3 for register addresses and refer toASdescription.Addressstrobe.WhenASisactive(LOW),A0,A1,andA2and CS0, CS1, andCS2 drive the internal select logicdirectly;whenASisHIGH,theregisterselectandchipselectsignals are held at the logic levels they were in when theLOW-to-HIGH transition ofAS occurred.Baud out.BAUDOUT is a 16× clock signal for thetransmittersectionoftheUART.Theclockrateisestablishedby the reference oscillator frequency divided by a divisorspeciﬁed in the baud generator divisor latches.BAUDOUTmayalsobeusedforthereceiversectionbytyingthisoutputto RCLK.© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

TypeDescriptionAS2824-25IBAUDOUT1712815O939775014451

Product dataRev. 03 — 10 December 20046 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

Table 2:SymbolCS0, CS1,CS2CSCTSPin description…continuedPinPLCC44LQFP48HVQFN32DIP4014, 15,16-409, 10,11-38-72512,I13, 14-36IIChip select. When CS0 and CS1 are HIGH andCS2 isLOW,thesethreeinputsselecttheUART.Whenanyoftheseinputs are inactive, the UART remains inactive (refer toASdescription).Clear to send.CTS is a modem status signal. Its conditioncan be checked by reading bit 4 (CTS) of the modem statusregister.Bit0(∆CTS)ofthemodemstatusregisterindicatesthatCTS has changed states since the last read from themodem status register. If the modem status interrupt isenabled whenCTS changes levels and the auto-CTS modeisnotenabled,aninterruptisgenerated.CTSisalsousedinthe auto-CTS mode to control the transmitter.Data bus. Eight data lines with 3-State outputs provide abi-directional path for data, control and status informationbetween the UART and the CPU.Data carrier detect.DCD is a modem status signal. Itscondition can be checked by reading bit 7 (DCD) of themodem status register. Bit 3 (∆DCD) of the modem statusregister indicates thatDCD has changed states since thelast read from the modem status register. If the modemstatus interrupt is enabled whenDCD changes levels, aninterrupt is generated.Driver disable.DDIS is active (LOW) when the CPU is notreading data. When active,DDIS can disable an externaltransceiver.Datasetready.DSRisamodemstatussignal.Itsconditioncanbecheckedbyreadingbit5(DSR)ofthemodemstatusregister.Bit1(∆DSR)ofthemodemstatusregisterindicatesDSRhaschangedlevelssincethelastreadfromthemodemstatus register. If the modem status interrupt is enabledwhenDSR changes levels, an interrupt is generated.Data terminal ready. When active (LOW),DTR informs amodem or data set that the UART is ready to establishcommunication.DTR is placed in the active level by settingtheDTR bit of the modem control register.DTR is placed intheinactiveleveleitherasaresultofaMasterReset,duringloop mode operation, or clearing theDTR bit.Interrupt. When active (HIGH), INT informs the CPU thatthe UART has an interrupt to be serviced. Four conditionsthat cause an interrupt to be issued are: a receiver error,received data that is available or timed out (FIFO modeonly), an empty transmitter holding register or an enabledmodem status interrupt. INT is reset (deactivated) eitherwhen the interrupt is serviced or as a result of a MasterReset.TypeDescriptionD7-D09-24-2,47-43403-1, 32-288-1I/ODCD42-38IDDIS2622-23ODSR41392637IDTR37332233OINT33302030O939775014451© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product dataRev. 03 — 10 December 20047 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

Table 2:SymbolOUT1,OUT2OUTPin description…continuedPinPLCC44LQFP48HVQFN32DIP4038, 35-34, 31--2334, 31O-OOutputs 1 and 2. These are user-designated outputterminals that are set to the active (low) level by settingrespective modem control register (MCR) bits (OUT1 andOUT2).OUT1andOUT2aresettoinactivethe(HIGH)levelasaresultofMasterReset,duringloopmodeoperations,orby clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR.Receiver clock. RCLK is the 16× baud rate clock for thereceiver section of the UART.Read inputs. When eitherIOR or IOR is active (LOW orHIGH, respectively) while the UART is selected, the CPU isallowed to read status information or data from a selectedUART register. Only one of these inputs is required for thetransfer of data during a read operation; the other inputshouldbetiedtoitsinactivelevel(i.e.,IORtiedLOWorIORtied HIGH).Master Reset. When active (HIGH), MR clears most UARTregisters and sets the levels of various output signals.Ring indicator.RI is a modem status signal. Its conditioncan be checked by reading bit 6 (RI) of the modem statusregister. Bit 2 (∆RI) of the modem status register indicatesthatRI has transitioned from a LOW to a HIGH level sincethe last read from the modem status register. If the modemstatus interrupt is enabled when this transition occurs, aninterrupt is generated.Request to send. When active,RTS informs the modem ordatasetthattheUARTisreadytoreceivedata.RTSissettotheactivelevelbysettingtheRTSmodemcontrolregisterbitand is set to the inactive (HIGH) level either as a result of aMaster Reset or during loop mode operations or by clearingbit1(RTS)oftheMCR.Intheauto-RTSmode,RTSissettothe inactive level by the receiver threshold control logic.Receiver ready. Receiver direct memory access (DMA)signaling is available withRXRDY. When operating in theFIFO mode, one of two types of DMA signaling can beselected using the FIFO control register bit 3 (FCR[3]).When operating in the 16C450 mode, only DMA mode 0 isallowed. Mode 0 supports single-transfer DMA in which atransferismadebetweenCPUbuscycles.Mode1supportsmulti-transfer DMA in which multiple transfers are madecontinuously until the receiver FIFO has been emptied. InDMA mode 0 (FCR0=0 or FCR0=1, FCR3=0), whenthere is at least one character in the receiver FIFO orreceiver holding register,RXRDY is active (LOW). WhenRXRDY has been active but there are no characters in theFIFO or holding register,RXRDY goes inactive (HIGH). InDMA mode1 (FCR0=1, FCR3=1), when the trigger levelor the time-out has been reached,RXRDY goes active(LOW); when it has been active but there are no morecharacters in the FIFO or holding register, it goes inactive(HIGH).© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

TypeDescriptionRCLKIORIOR102524520194-1492221IIIRESETRI3943354124-3539IIRTS36322132ORXRDY32291929O939775014451

Product dataRev. 03 — 10 December 20048 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

Table 2:SymbolRXTXPin description…continuedPinPLCC44LQFP48HVQFN32DIP40111378561011IOSerial data input. RX is serial data input from a connectedcommunications device.Serial data output. TX is composite serial data output to aconnected communication device. TX is set to the marking(HIGH) level as a result of Master Reset.Transmitter ready. Transmitter DMA signaling is availablewithTXRDY. When operating in the FIFO mode, one of twotypesofDMAsignalingcanbeselectedusingFCR[3].Whenoperatinginthe16C450mode,onlyDMAmode0isallowed.Mode0 supports single-transfer DMA in which a transfer ismade between CPU bus cycles. Mode1 supportsmulti-transfer DMA in which multiple transfers are madecontinuously until the transmit FIFO has been ﬁlled.TypeDescriptionTXRDY27231524OVCCGNDIOWIOW44222120421817162713-1140201918Power2.5V, 3V or 5V supply voltage.PowerGround voltage.IIWrite inputs. When eitherIOW or IOW is active (LOW orHIGH, respectively) and while the UART is selected, theCPUisallowedtowritecontrolwordsordataintoaselectedUART register. Only one of these inputs is required totransferdataduringawriteoperation;theotherinputshouldbe tied to its inactive level (i.e., IOW tied LOW orIOW tiedHIGH).Crystal connection or External clock input.CrystalconnectionortheinversionofXTAL1ifXTAL1isdriven.not connectedXTAL1XTAL2[1]n.c.18191, 12,23, 3414159101617-IO-1,6,13,1221, 25,36, 37,48[1]In sleep mode, XTAL2 is left ﬂoating.

Product dataRev. 03 — 10 December 20049 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

6.Functional description

TheSC16C650B provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter andreceiver sections. These functions are necessary for converting the serial data

streamintoparalleldatathatisrequiredwithdigitaldatasystems.Synchronizationforthe serial data stream is accomplished by adding start and stop bits to the transmitdatatoformadatacharacter(characterorientatedprotocol).Dataintegrityisinsuredbyattachingaparitybittothedatacharacter.Theparitybitischeckedbythereceiverfor any transmission bit errors. TheSC16C650B is fabricated with an advancedCMOS process to achieve low drain power and high speed requirements.

TheSC16C650Bisanupwardsolutionthatprovides32bytesoftransmitandreceiveFIFOmemory,insteadofnoneinthe16C450,or16inthe16C550.TheSC16C650Bis designed to work with high speed modems and shared network environments thatrequire fast data processing time. Increased performance is realized in theSC16C650B by the larger transmit and receive FIFOs. This allows the externalprocessor to handle more networking tasks within a given time. In addition, the fourselectable levels of FIFO trigger interrupt and automatic hardware/software ﬂowcontrol is uniquely provided for maximum data throughput performance, especiallywhenoperatinginamulti-channelenvironment.Thecombinationoftheabovegreatlyreduces the bandwidth requirement of the external controlling CPU, increasesperformance, and reduces power consumption.

TheSC16C650B is capable of operation up to 3Mbit/s with a 48MHz external clockinput (at 5V).

The rich feature set of theSC16C650B is available through internal registers.Automatic hardware/software ﬂow control, selectable transmit and receive FIFO

triggerlevel,selectableTXandRXbaudrates,modeminterfacecontrols,andasleepmode are some of these features.

Product dataRev. 03 — 10 December 200410 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

6.1Internal registers

TheSC16C650B provides 17 internal registers for monitoring and control. TheseregistersareshowninTable3.Twelveregistersaresimilartothosealreadyavailablein the standard 16C550. These registers function as data holding registers

(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register(FCR), line status and control registers (LCR/LSR), modem status and control

registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM),and a user accessible scratchpad register (SPR). Beyond the general 16C550features and capabilities, theSC16C650B offers an enhanced feature register set(EFR, Xon/Xoff1-2) that provides on-board hardware/software ﬂow control. Registerfunctions are more fully described in the following paragraphs.

Table 3:A2000011110001111

[1][2][3]

Internal registers decodingA1001100110010011

A0010101010100101

READ modeReceive Holding RegisterInterrupt Enable RegisterInterrupt Status RegisterLine Control RegisterModem Control RegisterLine Status RegisterModem Status RegisterScratchpad RegisterLSB of Divisor LatchMSB of Divisor LatchEnhanced Feature RegisterXon1 wordXon2 wordXoff1 wordXoff2 word

WRITE modeTransmit Holding RegisterInterrupt Enable RegisterFIFO Control RegisterLine Control RegisterModem Control Registern/an/a

Scratchpad RegisterLSB of Divisor LatchMSB of Divisor LatchEnhanced Feature RegisterXon1 wordXon2 wordXoff1 wordXoff2 word

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1]Baud rate register set (DLL/DLM)[2]

Enhanced register set (EFR, Xon/off 1-2)[3]

These registers are accessible only when LCR[7] is a logic0.These registers are accessible only when LCR[7] is a logic1.

Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to “BF”(HEX).

6.2FIFO operation

The 32-byte transmit and receive data FIFOs are enabled by the FIFO ControlRegister bit-0 (FCR[0]). With 16C550 devices, the user can set the receive triggerlevel,butnotthetransmittriggerlevel.TheSC16C650Bprovidesindependenttriggerlevels for both receiver and transmitter. To remain compatible with SC16C550, thetransmitinterrupttriggerlevelissetto16followingareset.Itshouldbenotedthattheuser can set the transmit trigger levels by writing to the FCR register, but activationwill not take place until EFR[4] is set to a logic1. The receiver FIFO section includes

Product dataRev. 03 — 10 December 200411 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

a time-out function to ensure data is delivered to the external CPU. An interrupt isgenerated whenever the Receive Holding Register (RHR) has not been read

following the loading of a character or the receive trigger level has not been reached.

Table 4:

Flow control mechanism

INT pin activation8162428

NegateRTS orsend Xoff8162428

AssertRTS orsend Xon071523

Selected trigger level(characters)8162428

6.3Hardware ﬂow control

Whenautomatichardwareﬂowcontrolisenabled,theSC16C650BmonitorstheCTSpin for a remote buffer overﬂow indication and controls theRTS pin for local bufferoverﬂows. Automatic hardware ﬂow control is selected by setting EFR[6] (RTS) andEFR[7] (CTS) to a logic1. IfCTS transitions from a logic0 to a logic1 indicating aﬂow control request, ISR[5] will be set to a logic1 (if enabled via IER[6,7]), and theSC16C650BwillsuspendTXtransmissionsassoonasthestopbitofthecharacterinprocess is shifted out. Transmission is resumed after theCTS input returns to alogic0, indicating more data may be sent.

WiththeAuto-RTSfunctionenabled,aninterruptisgeneratedwhenthereceiveFIFOreaches the programmed trigger level. TheRTS pin will not be forced to a logic1(RTSoff),untilthereceiveFIFOreachesthenexttriggerlevel.However,theRTSpinwillreturntoalogic0afterthedatabuffer(FIFO)isunloadedtothenexttriggerlevelbelowtheprogrammedtriggerlevel.However,undertheabovedescribedconditions,the SC16C650B will continue to accept data until the receive FIFO is full.

6.4Software ﬂow control

When software ﬂow control is enabled, theSC16C650B compares one or twosequential receive data characters with the programmed Xon or Xoff charactervalue(s). If received character(s) match the programmed Xoff values, the

SC16C650B will halt transmission (TX) as soon as the current character(s) has

completedtransmission.Whenamatchoccurs,thereceiveready(ifenabledviaXoffIER[5])ﬂagswillbesetandtheinterruptoutputpin(ifreceiveinterruptisenabled)willbe activated. Following a suspension due to a match of the Xoff characters’ values,theSC16C650B will monitor the receive data stream for a match to the Xon1,2character value(s). If a match is found, theSC16C650B will resume operation andclear the ﬂags (ISR[4]).

ResetinitiallysetsthecontentsoftheXon/Xoff8-bitﬂowcontrolregisterstoalogic0.Following reset, the user can write any Xon/Xoff value desired for software ﬂowcontrol. Different conditions can be set to detect Xon/Xoff characters and

suspend/resumetransmissions.Whendouble8-bitXon/Xoffcharactersareselected,theSC16C650Bcomparestwoconsecutivereceivecharacterswithtwosoftwareﬂowcontrol 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissionsaccordingly. Under the above described ﬂow control mechanisms, ﬂow control

Product dataRev. 03 — 10 December 200412 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

characters are not placed (stacked) in the user accessible RX data buffer or FIFO.When using a software ﬂow control the Xon/Xoff characters cannot be used for datatransfer.

Intheeventthatthereceivebufferisoverﬁllingandﬂowcontrolneedstobeexecuted,theSC16C650B automatically sends an Xoff message (when enabled) via the serialTX output to the remote modem. TheSC16C650B sends the Xoff1,2 characters assoon as received data passes the programmed trigger level. To clear this condition,theSC16C650BwilltransmittheprogrammedXon1,2charactersassoonasreceivedata drops below the next low or programmed trigger level.

6.5Special feature software ﬂow control

A special feature is provided to detect an 8-bit character when EFR[5] is set. When8-bit character is detected, it will be placed on the user-accessible data stack alongwith normal incoming RX data. This condition is selected in conjunction with

EFR[0:3].Notethatsoftwareﬂowcontrolshouldbeturnedoffwhenusingthisspecialmode by setting EFR[0:3] to a logic0.

TheSC16C650B compares each incoming receive character with Xoff2 data. If amatch exists, the received data will be transferred to the FIFO, and ISR[4] will be setto indicate detection of a special character. Although the Internal Register Table(Table8) shows each X-Register with eight bits of character information, the actualnumber of bits is dependent on the programmed word length. Line Control Registerbits LCR[0:1] deﬁne the number of character bits, i.e., either 5bits, 6bits, 7bits or8bits. The word length selected by LCR[0:1] also determine the number of bits thatwillbeusedforthespecialcharactercomparison.Bit0intheX-registerscorrespondswith the LSB bit for the receive character.

6.6Hardware/software and time-out interrupts

Threespecialinterruptshavebeenaddedtomonitorthehardwareandsoftwareﬂowcontrol. The interrupts are enabled by IER[5:7]. Care must be taken when handlingthese interrupts. Following a reset, the transmitter interrupt is enabled, the

SC16C650B will issue an interrupt to indicate that the Transmit Holding Register isempty. This interrupt must be serviced prior to continuing operations. The ISR

register provides the current singular highest priority interrupt only. It could be notedthat CTS and RTS interrupts have lowest interrupt priority. A condition can existwhere a higher priority interrupt may mask the lower priority CTS/RTS interrupt(s).Only after servicing the higher pending interrupt will the lower priority CTS/TRSinterrupt(s) be reﬂected in the status register. Servicing the interrupt withoutinvestigating further interrupt conditions can result in data errors.

When two interrupt conditions have the same priority, it is important to service theseinterrupts correctly. Receive Data Ready and Receive Time Out have the same

interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after thenumber of characters have reached the programmed trigger level. In this case, theSC16C650B FIFO may hold more characters than the programmed trigger level.Following the removal of a data byte, the user should re-check LSR[0] for additionalcharacters. A Receive Time Out will not occur if the receive FIFO is empty. Thetime-out counter is reset at the center of each stop bit received or each time the

receive holding register (RHR) is read. The actual time-out value is 4 character time.

939775014451

Product dataRev. 03 — 10 December 200413 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

6.7Programmable baud rate generator

TheSC16C650B supports high speed modem technologies that have increasedinputdataratesbyemployingdatacompressionschemes.Forexample,a33.6kbit/smodem that employs data compression may require a 115.2kbit/s input data rate.A128.0kbit/s ISDN modem that supports data compression may need an inputdatarate of 460.8kbit/s.

A single baud rate generator is provided for the transmitter and receiver, allowingindependent TX/RX channel control. The programmable Baud Rate Generator iscapable of accepting an input clock up to 48MHz, as required for supporting a

3Mbit/s data rate. TheSC16C650B can be conﬁgured for internal or external clockoperation.Forinternalclockoscillatoroperation,anindustrystandardmicroprocessorcrystal (parallel resonant/22-33pF load) is connected externally between the XTAL1and XTAL2 pins (seeFigure6). Alternatively, an external clock can be connected tothe XTAL1 pin to clock the internal baud rate generator for standard or custom rates(seeTable5).

XTAL1XTAL2XTAL1XTAL2X11.8432 MHz1.5 kΩC122 pFC247 pF002aaa586X11.8432 MHzC122 pFC233 pFFig 6.Crystal oscillator connection.The generator divides the input 16× clock by any divisor from 1 to 216−1. TheSC16C650B divides the basic crystal or external clock by 16. The frequency of theBAUDOUT output pin is exactly 16× (16 times) of the selected baud rate

(BAUDOUT=16Baud Rate). Customized baud rates can be achieved by selectingthe proper divisor values for the MSB and LSB sections of baud rate generator.Setting MCR[7] to a logic1 provides an additional divide-by-4, whereas settingMCR[7] to a logic0 only divides by 1 (seeTable5 andFigure7).

Programming the Baud Rate Generator registers DLM (MSB) and DLL (LSB)

provides a user capability for selecting the desired ﬁnal baud rate. The example inTable5 shows selectable baud rates when using a 1.8432MHz crystal and settingMCR[7] to a logic0.

For custom baud rates, the divisor value can be calculated using the followingequation:

XTAL1 clock frequency

Divisor (in decimal)=----------------------------------------------------------serial data rate×16

(1)

Product dataRev. 03 — 10 December 200414 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

Baud rates using 1.8432MHz or 3.072MHz crystal

Using 3.072MHz crystalBaud rateerrorDesiredbaud rate50750.0260.058110134.5150300600120018000.6920002400360048007200960019200384002.86Divisor for16× clock384025601745142812806403201601079680534027201051.230.6280.3120.0260.034Baud rateerrorDivisor for16× clock2304153610478577683841929664584832241612632Table 5:Desiredbaud rate5075110134.515030060012001800200024003600480072009600192003840056000Using 1.8432MHz crystalDIVIDE-BY-1LOGICXTAL1XTAL2CLOCKOSCILLATORLOGICDIVIDE-BY-4LOGICMCR[7] = 0BAUD RATEGENERATORLOGICBAUDOUTMCR[7] = 1002aaa208Fig 7.Baud rate generator circuitry.939775014451© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product dataRev. 03 — 10 December 200415 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

6.8DMA operation

TheSC16C650B FIFO trigger level provides additional ﬂexibility to the user for blockmode operation. The user can optionally operate the transmit and receive FIFOs intheDMAmode(FCR[3]).TheDMAmodeaffectsthestateoftheRXRDYandTXRDYoutput pins. Tables6 and7 show this.

Table 6:

Effect of DMA mode on state ofRXRDY pinDMA mode0-to-1 transition when FIFO empties

1-to-0 transition when FIFO reaches trigger level,ortime-out occurs

Non-DMA mode1 = FIFO empty

0 = at least 1 byte in FIFO

Table 7:Effect of DMA mode on state ofTXRDY pinDMA mode0-to-1 transition when FIFO becomes full1-to-0 transition when FIFO has 1 empty space

Non-DMA mode1 = at least 1 byte in FIFO0 = FIFO empty

6.9Sleep mode

TheSC16C650Bisdesignedtooperatewithlowpowerconsumption.Aspecialsleepmode is included to further reduce power consumption when the chip is not beingused. With EFR[4] and IER[4] enabled (set to a logic1), theSC16C650B enters thesleep mode, but resumes normal operation when a start bit is detected, a change ofstateonanyofthemodeminputpinsRI,CTS,DSR,DCD,RXpin,oratransmitdatais provided by the user. If the sleep mode is enabled and theSC16C650B is

awakened by one of the conditions described above, it will return to the sleep modeautomatically after the last character is transmitted or read by the user. In any case,thesleepmodewillnotbeenteredwhileaninterrupt(s)ispending.TheSC16C650Bwill stay in the sleep mode of operation until it is disabled by setting IER[4] to alogic0.

6.10Loop-back mode

Theinternalloop-backcapabilityallowson-boarddiagnostics.Intheloop-backmode,the normal modem interface pins are disconnected and reconﬁgured for loop-backinternally.MCR[0:3]registerbitsareusedforcontrollingloop-backdiagnostictesting.In the loop-back mode, OUT1 and OUT2 in the MCR register (bits 2:3) control themodemRI andDCD inputs, respectively. MCR signalsDTR andRTS (bits 0:1) areusedtocontrolthemodemDSRandCTSinputs,respectively.Thetransmitteroutput(TX) and the receiver input (RX) are disconnected from their associated interfacepins, and instead are connected together internally (seeFigure8). TheCTS,DSR,DCD, andRI are disconnected from their normal modem control input pins, andinsteadareconnectedinternallytoDTR,RTS,OUT1andOUT2.Loop-backtestdatais entered into the transmit holding register via the user data bus interface, D0-D7.The transmit UART serializes the data and passes the serial data to the receiveUART via the internal loop-back connection. The receive UART converts the serialdata back into parallel data that is then made available at the user data interfaceD0-D7.Theuseroptionallycomparesthereceiveddatatotheinitialtransmitteddatafor verifying error-free operation of the UART TX/RX circuits.

Product dataRev. 03 — 10 December 200416 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

Inthismode,thereceiverandtransmitterinterruptsarefullyoperational.TheModemControl Interrupts are also operational. However, the interrupts can only be readusing lower four bits of the Modem Status Register (MSR[0:3]) instead of the fourModem Status Register bits 4:7. The interrupts are still controlled by the IER.

SC16C650BTRANSMITFIFOREGISTERSD0–D7IOR, IORIOW, IOWRESETDATA BUSANDCONTROL LOGICFLOWCONTROLLOGICTRANSMITSHIFTREGISTERTXIRENCODERINTERCONNECT BUS LINESANDCONTROL SIGNALSRECEIVEFIFOREGISTERSRECEIVESHIFTREGISTERMCR[4] = 1RXA0–A2CS0, CS1CS2ASREGISTERSELECTLOGICFLOWCONTROLLOGICIRDECODERRTSDDISCTSDTRMODEMCONTROLLOGICDSROUT1INTTXRDYRXRDYINTERRUPTCONTROLLOGICCLOCK ANDBAUD RATEGENERATORRIOUT2DCD002aaa606XTAL1RCLKXTAL2BAUDOUTFig 8.Internal loop-back mode diagram.939775014451© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product dataRev. 03 — 10 December 200417 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

7.Register descriptions

Table8detailstheassignedbitfunctionsfortheﬁfteenSC16C650Binternalregisters.TheassignedbitfunctionsaremorefullydeﬁnedinSection7.1throughSection7.11.

Table 8:SC16C650B internal registers

Shaded bits are only accessible when EFR[4] is set.A2A1A0RegisterDefault[1]Bit 7General Register Set[2]000000001RHRTHRIERXXXX00bit 7bit 7CTSinterruptRCVRtrigger(MSB)FIFOsenableddivisorlatchenableClockselectFIFOdataerrorDCDbit 7bit 7bit 15AutoCTSbit 6bit 6RTSinterruptRCVRtrigger(LSB)FIFOsenabledbit 5bit 5XoffinterruptTXtrigger(MSB)INTprioritybit 4bit 4bit 4Sleepmodebit 3bit 3modemstatusinterruptbit 2bit 2bit 1bit 1bit 0bit 0receiveholdingregisterFIFOenableINTstatuswordlengthbit0DTRBit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0receivetransmitlinestatusholdinginterruptregisterXMITFIFOresetINTprioritybit1stop bitsRCVRFIFOresetINTprioritybit0wordlengthbit1RTS010FCR00TXtriggerDMA(LSB)modeselectINTprioritybit3INTprioritybit2parityenable010ISR01011LCR00set breakset parityevenparity100MCR00IR enableINT typeloop backOUT2,selectINTenabletrans.emptyRIbit 6bit 6bit 14trans.holdingemptyDSRbit 5bit 5bit 13breakinterruptCTSbit 4bit 4bit 12framingerror∆DCDbit 3bit 3bit 11OUT1101LSR60parityerror∆RIbit 2bit 2bit 10Cont-2Tx, RxControloverrunerror∆DSRbit 1bit 1bit 9Cont-1Tx, RxControlreceivedataready∆CTSbit 0bit 0bit 8Cont-0Tx, RxControl110001100101010MSRSPRDLLDLMEFRX0FFXXXX00Special Register Set[3]Enhanced Register Set[4]AutoRTSSpecialchar.selectEnableCont-3IER[4:7],Tx, RxISR[4,5],ControlFCR[4,5],MCR[5:7]bit 4bit 12bit 4bit 12bit 3bit 11bit 3bit 111111[1][2][3][4]

00110101Xon-1Xon-2Xoff-1Xoff-200000000bit 7bit 15bit 7bit 15bit 6bit 14bit 6bit 14bit 5bit 13bit 5bit 13bit 2bit 10bit 2bit 10bit 1bit 9bit 1bit 9bit 0bit 8bit 0bit 8The value shown represents the register’s initialized HEX value; X=n/a.These registers are accessible only when LCR[7]=0.

The Special Register set is accessible only when LCR[7] is set to a logic 1.

Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BFHex’.

939775014451

Product dataRev. 03 — 10 December 200418 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

7.1Transmit (THR) and Receive (RHR) Holding Registers

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) andTransmit Shift Register (TSR). The status of the THR is provided in the Line StatusRegister (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) tothe THR, providing that the THR or TSR is empty. The THR empty ﬂag in the LSRregister will be set to a logic1 when the transmitter is empty or when data is

transferred to the TSR. Note that a write operation can be performed when the THRempty ﬂag is set (logic0=FIFO full; logic1=at least one FIFO location available).The serial receive section also contains an 8-bit Receive Holding Register (RHR).ReceivedataisremovedfromtheSC16C650BandreceiveFIFObyreadingtheRHRregister. The receive section provides a mechanism to prevent false starts. On thefalling edge of a start or false start bit, an internal receiver counter starts countingclocks at the 16× clock rate. After 7-1⁄2 clocks, the start bit time should be shifted tothe center of the start bit. At this time the start bit is sampled, and if it is still a logic0it is validated. Evaluating the start bit in this manner prevents the receiver fromassembling a false character. Receiver status codes will be posted in the LSR.

7.2Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready,transmitter empty, line status and modem status registers. These interrupts wouldnormally be seen on the INT output pin.

Table 9:Bit7

Interrupt Enable Register bits description

DescriptionCTS interrupt.

Logic0 = Disable the CTS interrupt (normal default condition).

Logic1=EnabletheCTSinterrupt.TheSC16C650Bissuesaninterruptwhen the CTS pin transitions from a logic 0 to a logic 1.

IER[6]

RTS interrupt.

Logic0 = Disable the RTS interrupt (normal default condition).

Logic1=EnabletheRTSinterrupt.TheSC16C650Bissuesaninterruptwhen the RTS pin transitions from a logic0 to a logic1.

IER[5]

Xoff interrupt.

Logic0 = Disable the software ﬂow control, receive Xoff interrupt(normal default condition).

Logic1 = Enable the software ﬂow control, receive Xoff interrupt. SeeSection 6.4 “Software ﬂow control” for details.

IER[4]

Sleep mode.

Logic0 = Disable sleep mode (normal default condition).

Logic1 = Enable sleep mode. SeeSection 6.9 “Sleep mode” for details.

IER[3]

Modem Status Interrupt.

Logic0 = Disable the modem status register interrupt (normal defaultcondition).

Logic1 = Enable the modem status register interrupt.

SymbolIER[7]

Product dataRev. 03 — 10 December 200419 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

Interrupt Enable Register bits description…continuedDescriptionReceiveLineStatusinterrupt.Thisinterruptwillbeissuedwheneverafullyassembled receive character is transferred from RSR to the RHR/FIFO,i.e., data ready, LSR[0].

Logic0 = Disable the receiver line status interrupt (normal defaultcondition).

Logic1 = Enable the receiver line status interrupt.

Table 9:Bit2

SymbolIER[2]

1IER[1]

Transmit Holding Register interrupt. This interrupt will be issued wheneverthe THR is empty, and is associated with LSR[1].

Logic0 = Disable the transmitter empty interrupt (normal defaultcondition).

Logic1 = Enable the transmitter empty interrupt.

0IER[0]

Receive Holding Register interrupt. This interrupt will be issued when theFIFO has reached the programmed trigger level, or is cleared when theFIFO drops below the trigger level in the FIFO mode of operation.Logic0 = Disable the receiver ready interrupt (normal default condition).Logic1 = Enable the receiver ready interrupt.

7.2.1IER versus Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0]=logic1), and receive interrupts (IER[0]=logic1)are enabled, the receive interrupts and register status will reﬂect the following:

•The receive data available interrupts are issued to the external CPU when the

FIFO has reached the programmed trigger level. It will be cleared when the FIFOdrops below the programmed trigger level.

•FIFO status will also be reﬂected in the user accessible ISR register when the

FIFO trigger level is reached. Both the ISR register status bit and the interrupt willbe cleared when the FIFO drops below the trigger level.

•The data ready bit (LSR[0]) is set as soon as a character is transferred from the

shift register to the receive FIFO. It is reset when the FIFO is empty.

7.2.2

IER versus Receive/Transmit FIFO polled mode operation

When FCR[0]=logic1, resetting IER[0:3] enables theSC16C650B in the FIFO

polledmodeofoperation.SincethereceiverandtransmitterhaveseparatebitsintheLSR,eitherorbothcanbeusedinthepolledmodebyselectingrespectivetransmitorreceive control bit(s).

••••

LSR[0] will be a logic1 as long as there is one byte in the receive FIFO.LSR[1:4] will provide the type of errors encountered, if any.LSR[5] will indicate when the transmit FIFO is empty.

LSR[6] will indicate when both the transmit FIFO and transmit shift register areempty.

•LSR[7] will indicate any FIFO data errors.

Product dataRev. 03 — 10 December 200420 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

7.3FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFOtrigger levels, and select the DMA mode.

7.3.1

DMA mode

Mode 0 (FCR bit 3 = 0):Set and enable the interrupt for each single transmit orreceive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) willgotoalogic0wheneveranemptytransmitspaceisavailableintheTransmitHoldingRegister (THR). Receive Ready (RXRDY) will go to a logic0 whenever the ReceiveHolding Register (RHR) is loaded with a character.

Mode 1 (FCR bit 3 = 1):Setandenabletheinterruptinablockmodeoperation.Thetransmit interrupt is set when the transmit FIFO is below the programmed triggerlevel. The receive interrupt is set when the receive FIFO ﬁlls to the programmedtrigger level. However, the FIFO continues to ﬁll regardless of the programmed leveluntil the FIFO is full.RXRDY remains a logic0 as long as the FIFO ﬁll level is abovethe programmed trigger level.

7.3.2

FIFO mode

Table 10:Bit7-6FIFO Control Register bits description

DescriptionRCVRtrigger.ThesebitsareusedtosetthetriggerlevelforthereceiveFIFO interrupt.

An interrupt is generated when the number of characters in the FIFOequalstheprogrammedtriggerlevel.However,theFIFOwillcontinuetobe loaded until it is full. Refer toTable11.

Logic 0 or cleared is the default condition; TX trigger level=16.These bits are used to set the trigger level for the transmit FIFO

interrupt.TheSC16C650Bwillissueatransmitemptyinterruptwhenthenumber of characters in FIFO drops below the selected trigger level.Refer toTable12.DMA mode select.

Logic 0 = Set DMA mode ‘0’ (normal default condition).Logic 1 = Set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC16C650B is in the

16C450 mode (FIFOs disabled; FCR[0] = logic0) or in the FIFO mode(FIFOsenabled;FCR[0]=logic1;FCR[3]=logic0),andwhenthereareno characters in the transmit FIFO or transmit holding register, theTXRDY pin will be a logic0. Once active, theTXRDY pin will go to alogic1 after the ﬁrst character is loaded into the transmit holdingregister.

Receive operation in mode ‘0’: When the SC16C650B is in 16C450mode, or in the FIFO mode (FCR[0] = logic1; FCR[3] = logic 0) andthere is at least one character in the receive FIFO, theRXRDY pin willbealogic0.Onceactive,theRXRDYpinwillgotoalogic1whenthereare no more characters in the receiver.

SymbolFCR[7](MSB),FCR[6](LSB)FCR[5](MSB),FCR[4](LSB)FCR[3]

5-4

Product dataRev. 03 — 10 December 200421 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

FIFO Control Register bits description…continuedDescriptionTransmit operation in mode ‘1’: When the SC16C650B is in FIFOmode (FCR[0] = logic1; FCR[3]=logic1), theTXRDY pin will be alogic1whenthetransmitFIFOiscompletelyfull.Itwillbealogic0whenFIFO has 1empty space.

Receive operation in mode ‘1’: When the SC16C650B is in FIFO

mode(FCR[0]=logic1;FCR[3]=logic1)andthetriggerlevelhasbeenreached,oraReceiveTime-Outhasoccurred,theRXRDYpinwillgotoa logic 0. Once activated, it will go to a logic 1 after there are no morecharacters in the FIFO.

Table 10:BitSymbol2FCR[2]XMIT FIFO reset.

Logic0 = No FIFO transmit reset (normal default condition).Logic1 = Clears the contents of the transmit FIFO and resets theFIFO counter logic (the transmit shift register is not cleared oraltered). This bit will return to a logic0 after clearing the FIFO.

1FCR[1]RCVR FIFO reset.

Logic0 = No FIFO receive reset (normal default condition).

Logic1=ClearsthecontentsofthereceiveFIFOandresetstheFIFOcounter logic (the receive shift register is not cleared or altered). Thisbit will return to a logic 0 after clearing the FIFO.

0FCR[0]FIFO enable.

Logic0 = Disable the transmit and receive FIFO (normal defaultcondition).

Logic1 = Enable the transmit and receive FIFO.This bit must be a‘1’ when other FCR bits are written to, or they will not beprogrammed.

Table 11:FCR[7]0011Table 12:FCR[5]0011

RCVR trigger levelsFCR[6]0101

RX FIFO trigger level (bytes)8162428

TX FIFO trigger levelsFCR[4]0101

TX FIFO trigger level (bytes)1682430

Product dataRev. 03 — 10 December 200422 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

7.4Interrupt Status Register (ISR)

TheSC16C650B provides six levels of prioritized interrupts to minimize externalsoftware interaction. The Interrupt Status Register (ISR) provides the user with sixinterruptstatusbits.PerformingareadcycleontheISRwillprovidetheuserwiththehighest pending interrupt level to be serviced. No other interrupts are acknowledgeduntil the pending interrupt is serviced. Whenever the interrupt status register is read,the interrupt status is cleared. However, it should be noted that only the currentpending interrupt is cleared by the read. A lower level interrupt may be seen afterre-readingtheinterruptstatusbits.Table13“Interruptsource”showsthedatavalues(bits 0:5) for the six prioritized interrupt levels and the interrupt sources associated

with each of these interrupt levels.

Table 13:Prioritylevel1223456Table 14:Bit7:6

Interrupt sourceISR[5]0000001

ISR[4]0000010

ISR[3]0010000

ISR[2]1110000

ISR[1]1001000

ISR[0]0000000

Source of the interruptLSR(ReceiverLineStatusRegister)

RXRDY (Received DataReady)

RXRDY (Receive Datatime-out)

TXRDY (Transmitter

Holding Register Empty)MSR (Modem StatusRegister)

RXRDY (Received Xoffsignal) / Special characterCTS,RTSchange of state

Interrupt Status Register bits descriptionSymbolISR[7:6]

DescriptionFIFOs enabled. These bits are set to a logic0 when the FIFO isnot being used. They are set to a logic1 when the FIFOs areenabled.

Logic0 or cleared = default condition.

INT priority bits 4:3. These bits are enabled when EFR[4] is set toa logic 1. ISR[4] indicates that matching Xoff character(s) havebeen detected. ISR[5] indicates that CTS, RTS have been

generated.Notethatoncesettoalogic1,theISR[4]bitwillstayalogic1 until Xon character(s) are received.Logic0 or cleared = default condition.

INT priority bits 2:0. These bits indicate the source for a pendinginterrupt at interrupt priority levels 1, 2, and 3 (seeTable13).Logic0 or cleared = default condition.INT status.

Logic0 = An interrupt is pending and the ISR contents may beused as a pointer to the appropriate interrupt service routine.Logic1 = No interrupt pending (normal default condition).

5:4ISR[5:4]

3:1ISR[3:1]

0ISR[0]

Product dataRev. 03 — 10 December 200423 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

7.5Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communicationformat. The word length, the number of stop bits, and the parity are selected bywriting the appropriate bits in this register.

Table 15:Bit7

Line Control Register bits description

DescriptionDivisor latch enable. The internal baud rate counter latch and EnhanceFeature mode enable.

Logic0 = Divisor latch disabled (normal default condition).Logic1 = Divisor latch and enhanced feature register enabled.

LCR[6]

Setbreak.Whenenabled,theBreakcontrolbitcausesabreakconditionto be transmitted (the TX output is forced to a logic0 state). Thiscondition exists until disabled by setting LCR[6] to a logic0.Logic0 = no TX break condition (normal default condition).

Logic1=forcesthetransmitteroutput(TX)toalogic0foralertingtheremote receiver to a line break condition.

LCR[5]

Set parity. If the parity bit is enabled, LCR[5] selects the forced parityformat. Programs the parity conditions (seeTable16).Logic0 = parity is not forced (normal default condition).

LCR[5]=logic1andLCR[4]=logic0:paritybitisforcedtoalogical1for the transmit and receive data.

LCR[5]=logic1andLCR[4]=logic1:paritybitisforcedtoalogical0for the transmit and receive data.

LCR[4]

Even parity. If the parity bit is enabled with LCR[3] set to a logic1,LCR[4] selects the even or odd parity format.

Logic0 = ODD Parity is generated by forcing an odd number of

logic1s in the transmitted data. The receiver must be programmed tocheck the same format (normal default condition).

Logic1 = EVEN Parity is generated by forcing an even number oflogic1s in the transmitted data. The receiver must be programmed tocheck the same format.

LCR[3]

Parity enable. Parity or no parity can be selected via this bit.Logic0 = no parity (normal default condition).

Logic1 = a parity bit is generated during the transmission, receiverchecks the data and parity for transmission errors.

LCR[2]

Stopbits.Thelengthofstopbitisspeciﬁedbythisbitinconjunctionwiththe programmed word length (seeTable17).Logic0 or cleared = default condition.

1:0

LCR[1:0]

Word length bits 1, 0. These two bits specify the word length to betransmitted or received (seeTable18).Logic0 or cleared = default condition.

SymbolLCR[7]

Product dataRev. 03 — 10 December 200424 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

LCR[5] parity selectionLCR[4]X0101

LCR[3]01111

Parity selectionno parityODD parityEVEN parityforce parity ‘1’forced parity ‘0’

Table 16:LCR[5]X0011Table 17:LCR[2]011Table 18:LCR[1]0011

LCR[2] stop bit lengthWord length5, 6, 7, 856, 7, 8

Stop bit length (bit times)11-1⁄22

LCR[1:0] word lengthLCR[0]0101

Word length5678

7.6Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 19:Bit7

Modem Control Register bits descriptionSymbolMCR[7]

DescriptionClock select.

Logic0 = Divide-by-1. The input clock (crystal or external) is

dividedby16andthenpresentedtotheProgrammableBaudRateGenerator (BGR) without further modiﬁcation, i.e., divide-by-1(normal default condition).

Logic1 = Divide-by-4. The divide-by-1 clock described in MCR[7]equals a logic0, is further divided by four (see alsoSection 6.7“Programmable baud rate generator”).

MCR[6]

IR enable.

Logic0 = Enable the standard modem receive and transmitinput/output interface (normal default condition).

Logic1=EnableinfraredIrDAreceiveandtransmitinputs/outputs.While in this mode, the TX/RX output/inputs are routed to theinfrared encoder/decoder. The data input and output levels willconform to the IrDA infrared interface requirement. As such, whileinthismode,theinfraredTXoutputwillbealogic0duringidledataconditions.

Product dataRev. 03 — 10 December 200425 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

Modem Control Register bits description…continuedSymbolMCR[5]

DescriptionINT typ select.

Logic0=Enable active or 3-State interrupt output mode (normaldefault condition).

Logic=1=Enable open source interrupt output mode. Providesshared interrupts in the STD mode by producing a wire-OR outputdrivercapabilityforinterrupts.ThisoutputappearsattheIRQA/INTpin. When using this option, an external pull-down resistor of200to500Ω must be tied from the IRQA/INT pin to ground toprovide and acceptable logic0 level

Table 19:Bit5

4MCR[4]

Loop-back. Enable the local loop-back mode (diagnostics). In thismode the transmitter output (TX) and the receiver input (RX),CTS,DSR,DCD, andRI are disconnected from the SC16C650B I/O pins.Internally the modem data and control pins are connected into a

loop-backdataconﬁguration(seeFigure8).Inthismode,thereceiverand transmitter interrupts remain fully operational. The Modem

ControlInterruptsarealsooperational,buttheinterrupts’sourcesareswitched to the lower four bits of the Modem Control. Interruptscontinue to be controlled by the IER register.

Logic 0 = Disable loop-back mode (normal default condition).Logic 1 = Enable local loop-back mode (diagnostics).

3MCR[3]OUT2, INTx enable. Used to control the modemDCD signal in theloop-back mode.

Logic0 = Forces INT output to the 3-State mode. In the loop-backmode, setsOUT2 (DCD) internally to a logic1.

Logic1 = Forces the INT output to the active mode. In theloop-back mode, setsOUT2 (DCD) internally to a logic 0.2MCR[2]OUT1. This bit is used in the Loop-back mode only. In the loop-backmode, this bit is used to write the state of the modemRI interfacesignal viaOUT1.RTSLogic0=ForceRTS output to a logic1 (normal default condition).Logic1=ForceRTS output to a logic0.

1MCR[1]0MCR[0]DTRLogic0=ForceDTR output to a logic1 (normal default condition).Logic1=ForceDTR output to a logic0.

Product dataRev. 03 — 10 December 200426 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

7.7Line Status Register (LSR)

This register provides the status of data transfers between theSC16C650B andtheCPU.

Table 20:Bit7Line Status Register bits description

DescriptionFIFO data error.Logic0 = No error (normal default condition).

Logic1=Atleastoneparityerror,framingerrororbreakindicationisinthe current FIFO data. This bit is cleared when LSR register is read.

LSR[6]

THR and TSR empty. This bit is the Transmit Empty indicator. This bit isset to a logic1 whenever the transmit holding register and the transmitshiftregisterarebothempty.Itisresettologic0whenevereithertheTHRor TSR contains a data character. In the FIFO mode, this bit is set to ‘1’whenever the transmit FIFO and transmit shift register are both empty.THR empty. This bit is the Transmit Holding Register Empty indicator.This bit indicates that the UART is ready to accept a new character fortransmission.Inaddition,thisbitcausestheUARTtoissueaninterrupttoCPUwhentheTHRinterruptenableisset.TheTHRbitissettoalogic1whenacharacteristransferredfromthetransmitholdingregisterintothetransmittershiftregister.Thebitisresettoalogic0concurrentlywiththeloadingofthetransmitterholdingregisterbytheCPU.IntheFIFOmode,this bit is set when the transmit FIFO is empty; it is cleared when at least1byte is written to the transmit FIFO.Break interrupt.

Logic0 = No break condition (normal default condition).

Logic1 = The receiver received a break signal (RX was a logic0 foronecharacterframetime).IntheFIFOmode,onlyonebreakcharacteris loaded into the FIFO.

LSR[3]

Framing error.

Logic0 = No framing error (normal default condition).

Logic1=Framingerror.Thereceivecharacterdidnothaveavalidstopbit(s). In the FIFO mode, this error is associated with the character atthe top of the FIFO.

LSR[2]

Parity error.

Logic0 = No parity error (normal default condition).

Logic1 = Parity error. The receive character does not have correctparity information and is suspect. In the FIFO mode, this error isassociated with the character at the top of the FIFO.

LSR[1]

Overrun error.

Logic0=No overrun error (normal default condition).

Logic1=Overrun error. A data overrun error occurred in the receiveshiftregister.ThishappenswhenadditionaldataarriveswhiletheFIFOis full. In this case, the previous data in the shift register is overwritten.Notethatunderthiscondition,thedatabyteinthereceiveshiftregisteris not transferred into the FIFO, therefore the data in the FIFO is notcorrupted by the error.

SymbolLSR[7]5LSR[5]

4LSR[4]

Product dataRev. 03 — 10 December 200427 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

Line Status Register bits description…continuedDescriptionReceive data ready.

Logic0=No data in receive holding register or FIFO (normal defaultcondition).

Logic1=Data has been received and is saved in the receive holdingregister or FIFO.

Table 20:Bit0

SymbolLSR[0]

7.8Modem Status Register (MSR)

This register provides the current state of the control interface signals from the

modem, or other peripheral device to which theSC16C650B is connected. Four bitsof this register are used to indicate the changed information. These bits are set to alogic1wheneveracontrolinputfromthemodemchangesstate.Thesebitsaresettoa logic0 whenever the CPU reads this register.

Table 21:Bit7Modem Status Register bits description

DescriptionData Carrier Detect. DCD (Active-HIGH, logical1). Normally this bit isthe complement of theDCD input. In the loop-back mode this bit isequivalent to the OUT2 bit in the MCR register.

Ring Indicator. RI (Active-HIGH, logical1). Normally this bit is the

complement of theRI input. In the loop-back mode this bit is equivalentto the OUT1 bit in the MCR register.

Data Set Ready. DSR (Active-HIGH, logical1). Normally this bit is thecomplementoftheDSRinput.Inloop-backmodethisbitisequivalenttothe DTR bit in the MCR register.

ClearToSend.CTS.CTSfunctionsashardwareﬂowcontrolsignalinputif it is enabled via EFR[7]. Flow control (when enabled) allows startingand stopping the transmissions based on the external modemCTSsignal. A logic1 at theCTS pin will stop SC16C650B transmissions assoonascurrentcharacterhasﬁnishedtransmission.NormallyMSR[4]isthe complement of theCTS input. However, in the loop-back mode, thisbit is equivalent to the RTS bit in the MCR register.∆DCD[1]Logic0=NoDCD change (normal default condition).Logic1=TheDCD input to the SC16C650B has changed state sincethe last time it was read. A modem Status Interrupt will be generated.

2MSR[2]∆RI[1]Logic0=NoRI change (normal default condition).Logic1=TheRI input to the SC16C650B has changed from a logic0to a logic1. A modem Status Interrupt will be generated.

SymbolMSR[7]6MSR[6]

5MSR[5]

Product dataRev. 03 — 10 December 200428 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

Modem Status Register bits description…continuedDescription∆DSR[1]Logic0=NoDSR change (normal default condition).Logic1=TheDSR input to the SC16C650B has changed state sincethe last time it was read. A modem Status Interrupt will be generated.

Table 21:Bit1SymbolMSR[1]0MSR[0]∆CTS[1]Logic0= NoCTS change (normal default condition).Logic1= TheCTS input to the SC16C650B has changed state sincethe last time it was read. A modem Status Interrupt will be generated.

[1]Whenever any MSR bit 0:3 is set to logic1, a Modem Status Interrupt will be generated.

7.9Scratchpad Register (SPR)

TheSC16C650B provides a temporary data register to store 8bits of userinformation.

7.10Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register.

Bits 0 through 4 provide single or dual character software ﬂow control selection.When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double8-bit words are concatenated into two sequential numbers.

Table 22:Bit7

Enhanced Feature Register bits description

DescriptionAutomatic CTS ﬂow control.

Logic0=Automatic CTS ﬂow control is disabled (normal defaultcondition).

Logic1=Enable Automatic CTS ﬂow control. Transmission will stopwhenCTS goes to a logical1. Transmission will resume when theCTSpin returns to a logical0.

EFR[6]

AutomaticRTSﬂowcontrol.AutomaticRTSmaybeusedforhardwareﬂowcontrol by enabling EFR[6]. When Auto-RTS is selected, an interrupt willbe generated when the receive FIFO is ﬁlled to the programmed triggerlevelandRTSwillgotoalogic1atthenexttriggerlevel.RTSwillreturntoa logic0 when data is unloaded below the next lower trigger level

(programmedtriggerlevel1).Thestateofthisregisterbitchangeswiththestatus of the hardware ﬂow control.RTS functions normally whenhardware ﬂow control is disabled.

0=Automatic RTS ﬂow control is disabled (normal default condition).1=Enable Automatic RTS ﬂow control.

SymbolEFR[7]

Product dataRev. 03 — 10 December 200429 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

Enhanced Feature Register bits description…continuedDescriptionSpecial Character Detect.

Logic0 = Special character detect disabled (normal default condition).Logic1=Specialcharacterdetectenabled.TheSC16C650Bcompareseach incoming receive character with Xoff2 data. If a match exists, thereceived data will be transferred to FIFO and ISR[4] will be set toindicate detection of special character. Bit-0 in the X-registers

correspondswiththeLSBbitforthereceivecharacter.Whenthisfeatureis enabled, the normal software ﬂow control must be disabled (EFR[3:0]must be set to a logic0).

Table 22:Bit5

SymbolEFR[5]

4EFR[4]

Enhancedfunctioncontrolbit.ThecontentofIER[7:4],ISR[5:4],FCR[5:4],andMCR[7:5]canbemodiﬁedandlatched.Aftermodifyinganybitsintheenhancedregisters,EFR[4]canbesettoalogic0tolatchthenewvalues.This feature prevents existing software from altering or overwriting theSC16C650B enhanced functions.

Logic0 = Disable (normal default condition).Logic1 = Enable.

3:0

EFR[3:0]Cont-3:0 Tx, Rx control. Logic 0 or cleared is the default condition.

Combinations of software ﬂow control can be selected by programmingthese bits. SeeTable23.

Software ﬂow control functions[1]Cont-20011XXX011

Cont-1XXXX010111

Cont-0XXXX001111

TX, RX software ﬂow controlsNo transmit ﬂow controlTransmit Xon1/Xoff1Transmit Xon2/Xoff2

Transmit Xon1 and Xon2/Xoff1 and Xoff2No receive ﬂow controlReceiver compares Xon1/Xoff1Receiver compares Xon2/Xoff2Transmit Xon1/Xoff1

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2Transmit Xon2/Xoff2

Receiver compares Xon1 and Xon2/Xoff1 and Xoff2Transmit Xon1 and Xon2/Xoff1 and Xoff2

Receiver compares Xon1 and Xon2/Xoff1 and Xoff2

Table 23:Cont-30101XXX101

[1]When using a software ﬂow control the Xon/Xoff characters cannot be used for data transfer.

Product dataRev. 03 — 10 December 200430 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

7.11SC16C650B external reset conditions

Table 24:RegisterIERISRLCRMCRLSRMSRFCREFRTable 25:OutputTXRTSDTRRXRDYTXRDYINT

Reset state for registers

Reset stateIER[7:0] = 0ISR[7:1] = 0; ISR[0] = 1LCR[7:0] = 0MCR[7:0] = 0

LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0MSR[7:4] = input signals; MSR[3:0] = 0FCR[7:0] = 0EFR[7:0] = 0

Reset state for outputs

Reset stateHIGHHIGHHIGHHIGH (STD mode)LOW (STD mode)LOW (STD mode)

8.Limiting values

Table 26:Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).SymbolVCCVnTambTstgPtot(pack)

Parametersupply voltagevoltage at any pinoperating temperaturestorage temperaturetotalpowerdissipationperpackage

ConditionsMin-GND−0.3−40−65-Max7VCC+0.3+85+150500

UnitVV°C°CmW

Product dataRev. 03 — 10 December 200431 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

9.Static characteristics

Table 27:DC electrical characteristics

Tamb=−40°C to +85°C; VCC=2.5V, 3.3V or 5.0V±10%, unless otherwise speciﬁed.SymbolVIL(CK)VIH(CK)VILVIHVOL

ParameterLOW-level clock input voltageHIGH-level clock input voltageLOW-level input voltageHIGH-level input voltageLOW-level output voltageonalloutputs[1]

IOL=5mA(databus)IOL=4mA(other outputs)IOL=2mA(databus)IOL=1.6mA(other outputs)

VOH

HIGH-level output voltage

IOH=−5mA(databus)IOH=−1mA(other outputs)IOH=−800µA(databus)IOH=−400µA(other outputs)

ILILICLICCCiRpu(int)

[1][2]

ConditionsMin−0.31.8−0.31.6------1.851.85--f=5MHz

--500

2.5VMax0.45VCC0.65---0.40.4----±10±303.55-Min−0.32.4−0.32.0-----2.0------500

3.3VMax0.6VCC0.8--0.4------±10±304.55-Min−0.53.0−0.52.2----2.4-------500

5.0VMax0.6VCC0.8VCC0.4-------±10±304.55-

UnitVVVVVVVVVVVVµAµAmApFkΩ

LOW-level input leakage currentclock leakage

average power supply currentinput capacitance

internal pull-up resistance[2]

Except for x2, VOL=1V typically.

Refer toTable 2 “Pin description” on page 6 for a listing of pins having internal pull-up resistors.

Product dataRev. 03 — 10 December 200432 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

10.Dynamic characteristics

Table 28:AC electrical characteristics

Tamb=−40°C to +85°C; VCC=2.5V, 3.3V or 5V±10%, unless otherwise speciﬁed.Symbolt1w, t2wt3wt4wt5st5ht6st6ht6s't6ht7dt7wt7ht7h't8dt9dt11dt12dt12ht13dt13wt13ht14dt15dt16st16ht17dt18dt19dt20dt21dt22dt23dt24dt25dt26dt27d

939775014451

Parameterclock pulse durationoscillator/clock frequencyaddress strobe widthaddress set-up timeaddress hold time

chip select set-up time toASaddress hold timeaddress set-up timechip select hold timeIOR delay from chip selectIOR strobe widthchip select hold time fromIORaddress hold timeIOR delay from addressread cycle delayIOR toDDIS delaydelay fromIOR to datadata disable time

IOW delay from chip selectIOW strobe widthchip select hold time fromIOWIOW delay from address write cycle delaydata set-up timedata hold time

delay fromIOW to outputdelay to set interrupt from Modeminput

delay to reset interrupt fromIORdelay from stop to set interruptdelay fromIOR to reset interruptdelay from start to set interruptdelay fromIOW to transmit startdelay fromIOW to reset interruptdelay from stop to setRXRDYdelay fromIOR to resetRXRDYdelay fromIOW to setTXRDYConditionsMin15

[1]

2.5VMax-16-------------1007715-------1001001001100100241001100100Min13-3555501001026051020---102001025205------8----3.3VMax-32-------------352615-------33242412945244514545Min10-251500501023051020---101501020155------8----5.0VMax-48-------------302315-------29232312840244014040UnitnsMHznsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsRclknsnsRclknsRclknsns-4555100

[2]

1001025pF load[2]

77051020---1020010252015

25pF load25pF load25pF load25pF load

Product dataRev. 03 — 10 December 200433 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

Table 28:AC electrical characteristics…continuedTamb=−40°C to +85°C; VCC=2.5V, 3.3V or 5V±10%, unless otherwise speciﬁed.Symbolt28dtRESETN

[1][2]

Parameterdelay from start to resetTXRDYReset pulse widthbaud rate divisor

ConditionsMin-1001

2.5VMax8-Min-40

3.3VMax8-Min-40

5.0VMax8-

UnitRclkns

216−11216−11216−1Rclk

Applies to external clock, crystal oscillator max 24MHz.Applicable only whenAS is tied LOW.10.1Timing diagrams

t4wASt5st5hA0–A2VALIDADDRESSt6st6hCS2CS1–CS0t7dt8dVALIDt7ht9dt7wIOR, IORACTIVEt11dt11dDDISACTIVEt12dt12hD0–D7DATA002aaa331Fig 9.General read timing when usingAS signal.939775014451© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product dataRev. 03 — 10 December 200434 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

t4wASt5st5hA0–A2VALIDADDRESSt6st6hCS2CS1–CS0t13dt14dVALIDt13ht15dt13wIOW, IOWACTIVEt16st16hD0–D7DATA002aaa332Fig 10.General write timing when usingAS signal.A0–A2VALIDADDRESSVALIDADDRESSt7h′t6s′t7h′t6s′t7wCSACTIVEACTIVEt7wt9dIORACTIVEt12ht12dt12dt12hD0–D7DATA002aaa333Fig 11.General read timing whenAS is tied to GND.939775014451© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product dataRev. 03 — 10 December 200435 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

A0–A2VALIDADDRESSVALIDADDRESSt7h′t6s′t7h′t6s′CSACTIVEACTIVEt13wt15dt13wIOWACTIVEt16ht16st16st16hD0–D7DATA002aaa334Fig 12.General write timing whenAS is tied to GND.IOWACTIVEt17dRTSDTRCHANGE OF STATECHANGE OF STATEDCDCTSDSRt18dt18dCHANGE OF STATECHANGE OF STATEINTACTIVEACTIVEACTIVEt19dIORACTIVEACTIVEACTIVEt18dRICHANGE OF STATE002aaa351Fig 13.Modem input/output timing.939775014451

Product dataRev. 03 — 10 December 200436 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

t2wEXTERNALCLOCKt3wFig 14.External clock timing.t1w002aaa112startbitdata bits (0 to 7)D0D1D2D3D4D5D6D7paritybitstopbitnextdatastartbitRX5 data bits6 data bits7 data bitsINTt20dactivet21dIORactive16 baud rate clock002aaa113Fig 15.Receive timing.939775014451© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product dataRev. 03 — 10 December 200437 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

STARTBITDATA BITS (5–8)PARITYBITSTOPBITNEXTDATASTARTBITRXD0D1D2D3D4D5D6D7t25dACTIVEDATAREADYt26dRXRDYIORACTIVE002aaa578Fig 16.Receive ready timing in non-FIFO mode.STARTBITDATA BITS (5–8)PARITYBITSTOPBITRXD0D1D2D3D4D5D6D7FIRST BYTE THATREACHES THE TRIGGER LEVELt25dACTIVEDATAREADYt26dRXRDYIORACTIVE002aaa579Fig 17.Receive ready timing in FIFO mode.939775014451© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product dataRev. 03 — 10 December 200438 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

startbitdata bits (0 to 7)D0D1D2D3D4D5D6D7paritybitstopbitnextdatastartbitTX5 data bits6 data bits7 data bitsINTt22dt23dIOWactiveactivetransmitter readyt24dactive16 baud rate clock002aaa116Fig 18.Transmit timing.STARTBITDATA BITS (5-8)PARITYBITSTOPBITNEXTDATASTARTBITTXD0D1D2D3D4D5D6D7IOWACTIVED0-D7BYTE #1t28dt27dTXRDYACTIVETRANSMITTER READYTRANSMITTERNOT READY002aaa580Fig 19.Transmit ready timing in non-FIFO mode.939775014451

Product dataRev. 03 — 10 December 200439 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

STARTBITDATA BITS (5-8)PARITYBITSTOPBITTXD0D1D2D3D4D5D6D75 DATA BITS6 DATA BITS7 DATA BITSIOWACTIVEt28dD0–D7BYTE #16t27dTXRDYFIFO FULL002aaa581Fig 20.Transmit ready timing in FIFO mode (DMA mode ‘1’).939775014451© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product dataRev. 03 — 10 December 200440 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

UART framestartdata bitsstopTX data0101001101IrDA TX data1/ bit time23/ bit time16bittime002aaa212Fig 21.Infrared transmit timing.IrDA RX databittimeRX data010100 to 1 16× clock delay01101startdata bitsstopUART frame002aaa213Fig 22.Infrared receive timing.939775014451© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product dataRev. 03 — 10 December 200441 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

11.Package outline

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

eDyXAZEeE392928bpb1wM40441pin 1 indexEHEAA4A1(A )3eβk618Lp7eDHD17ZDBvMBvMAdetail X05scale10 mmDIMENSIONS (mm dimensions are derived from the original inch dimensions)A4A1eUNITAA3D(1)E(1)eDeEHDbpb1max.min.mm4.574.190.510.250.013.050.530.330.810.66HEkLp1.441.02v0.18w0.18y0.1ZD(1)ZE(1)max.max.2.162.16β16.6616.6616.0016.0017.6517.651.221.2716.5116.5114.9914.9917.4017.401.070.630.590.630.590.180inches0.020.1650.0210.0320.6560.6560.050.120.0130.0260.6500.6500.6950.6950.0480.0570.0070.0070.0040.0850.0850.6850.6850.0420.04045oNote1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINEVERSIONSOT187-2 REFERENCES IEC112E10 JEDECMS-018 JEITAEDR-7319EUROPEANPROJECTIONISSUE DATE99-12-2701-11-14Fig 23.PLCC44 (SOT187-2).

939775014451

Product dataRev. 03 — 10 December 200442 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mmSOT313-2

cyX36372524ZEAeEHEAA2A1(A )3θwMpin 1 index48 112ZDvMA13detail XbpLLpebpDHDwMBvMB02.5scale5 mmDIMENSIONS (mm are the original dimensions)UNITmmAmax.1.6A10.200.05A21.451.35A30.25bp0.270.17c0.180.12D(1)7.16.9E(1)7.16.9e0.5HD9.158.85HE9.158.85L1Lp0.750.45v0.2w0.12y0.1ZD(1)ZE(1)0.950.550.950.55θ7o0oNote1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINEVERSION SOT313-2 REFERENCES IEC136E05 JEDECMS-026 JEITAEUROPEANPROJECTIONISSUE DATE00-01-1903-02-25Fig 24.LQFP48 (SOT313-2).

939775014451

Product dataRev. 03 — 10 December 200443 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;32 terminals; body 5 x 5 x 0.85 mm

SOT617-1

DBAterminal 1index areaEAA1cdetail Xe1e9L817e1/2 eCb16vMCABwMCy1CyEh1/2 ee21terminal 1index area2432Dh02.5scaleE(1)5.14.9Eh3.252.95e0.5e13.5e23.5L0.50.3v0.1w0.05y0.05y10.15 mm25XDIMENSIONS (mm are the original dimensions)UNITmmA(1)max.1A10.050.00b0.300.18c0.2D(1)5.14.9Dh3.252.95Note1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINEVERSION SOT617-1 REFERENCES IEC- - - JEDECMO-220 JEITA- - -EUROPEANPROJECTIONISSUE DATE01-08-0802-10-18Fig 25.HVQFN32 (SOT617-1).

Product dataRev. 03 — 10 December 200444 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

DIP40: plastic dual in-line package; 40 leads (600 mil)SOT129-1

seating planeDMEA2ALA1cZeb1b4021wM(e )1MHpin 1 indexE12005scale10 mmDIMENSIONS (inch dimensions are derived from the original mm dimensions)UNITmminchesAmax.4.70.19A 1min.0.510.02A 2max.40.16b1.701.140.0670.045b10.530.380.0210.015c0.360.230.0140.009D(1)E(1)e2.540.1e115.240.6L3.603.050.140.12ME15.8015.240.620.60MH17.4215.900.690.63w0.2540.01Z(1)max.2.25 0.089 52.551.52.0672.02814.113.70.560.54Note1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINEVERSIONSOT129-1 REFERENCES IEC051G08 JEDECMO-015 JEITASC-511-40EUROPEANPROJECTIONISSUE DATE99-12-2703-02-13Fig 26.DIP40 (SOT129-1).

939775014451

Product dataRev. 03 — 10 December 200445 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

12.Soldering

12.1Introduction

This text gives a very brief insight to a complex technology. A more in-depth accountof soldering ICs can be found in ourData Handbook IC26; Integrated CircuitPackages (document order number 939865290011).

ThereisnosolderingmethodthatisidealforallICpackages.Wavesolderingisoftenpreferred when through-hole and surface mount components are mixed on one

printed-circuit board. Wave soldering can still be used for certain surface mount ICs,but it is not suitable for ﬁne pitch SMDs. In these situations reﬂow soldering is

recommended. Driven by legislation and environmental forces the worldwide use oflead-free solder pastes is increasing.

12.2Through-hole mount packages

12.2.1

Soldering by dipping or by solder wave

Typical dwell time of the leads in the wave ranges from 3to4seconds at 250°C or265°C, depending on solder material applied, SnPb or Pb-free respectively.The total contact time of successive solder waves must not exceed 5seconds.The device may be mounted up to the seating plane, but the temperature of the

plasticbodymustnotexceedthespeciﬁedmaximumstoragetemperature(Tstg(max)).If the printed-circuit board has been pre-heated, forced cooling may be necessaryimmediately after soldering to keep the temperature within the permissible limit.

12.2.2Manual soldering

Apply the soldering iron (24V or less) to the lead(s) of the package, either below theseatingplaneornotmorethan2mmaboveit.Ifthetemperatureofthesolderingironbit is less than 300°C it may remain in contact for up to 10seconds. If the bittemperature is between 300and400°C, contact may be up to 5seconds.

12.3Surface mount packages

12.3.1

Reﬂow soldering

Reﬂowsolderingrequiressolderpaste(asuspensionofﬁnesolderparticles,ﬂuxandbindingagent)tobeappliedtotheprinted-circuitboardbyscreenprinting,stencillingor pressure-syringe dispensing before package placement.

Several methods exist for reﬂowing; for example, convection or convection/infraredheating in a conveyor type oven. Throughput times (preheating, soldering andcooling) vary between 100and200seconds depending on heating method.Typical reﬂow peak temperatures range from 215to270°C depending on solderpaste material. The top-surface temperature of the packages should preferably bekept:

•below 225°C (SnPb process) or below 245°C (Pb-free process)

–for all the BGA and SSOP-T packages

939775014451

Product dataRev. 03 — 10 December 200446 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

–for packages with a thickness≥2.5mm

–for packages with a thickness <2.5mm and a volume≥350mm3 so calledthick/large packages.

•below240°C(SnPbprocess)orbelow260°C(Pb-freeprocess)forpackageswith

a thickness <2.5mm and a volume <350mm3 so called small/thin packages.Moisture sensitivity precautions, as indicated on packing, must be respected at alltimes.

12.3.2

Wave soldering

Conventional single wave soldering is not recommended for surface mount devices(SMDs) or printed-circuit boards with a high component density, as solder bridgingand non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcallydeveloped.

If wave soldering is used the following conditions must be observed for optimalresults:

•Use a double-wave soldering method comprising a turbulent wave with high

upward pressure followed by a smooth laminar wave.

•For packages with leads on two sides and a pitch (e):

–largerthanorequalto1.27mm,thefootprintlongitudinalaxisispreferredtobeparallel to the transport direction of the printed-circuit board;

–smaller than 1.27mm, the footprint longitudinal axismust be parallel to thetransport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

•For packages with leads on four sides, the footprint must be placed at a 45° angle

to the transport direction of the printed-circuit board. The footprint mustincorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet ofadhesive. The adhesive can be applied by screen printing, pin transfer or syringedispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3to4seconds at 250°C or265°C, depending on solder material applied, SnPb or Pb-free respectively.Amildly-activated ﬂux will eliminate the need for removal of corrosive residues inmost applications.

12.3.3

Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a lowvoltage (24V or less) soldering iron applied to the ﬂat part of the lead. Contact timemust be limited to 10seconds at up to 300°C.

When using a dedicated tool, all other leads can be soldered in one operation within2to5seconds between 270and320°C.

Product dataRev. 03 — 10 December 200447 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

12.4Package related soldering information

Table 29:MountingThrough-holemountThrough-hole-surface mountSurface mount

Suitability of IC packages for wave, reﬂow and dipping soldering methods

Package[1]DBS, DIP, HDIP, RDBS,SDIP, SILPMFP[4]

BGA, LBGA, LFBGA,SQFP, SSOP-T[5],TFBGA, VFBGADHVQFN, HBCC, HBGA,HLQFP, HSQFP, HSOP,HTQFP, HTSSOP,

HVQFN, HVSON, SMSPLCC[7], SO, SOJLQFP, QFP, TQFPSSOP, TSSOP, VSO,VSSOP

[1][2]

Soldering methodWavesuitable[3]not suitablenot suitable

Reﬂow[2]−not

suitablesuitable

Dippingsuitable−−

not suitable[6]suitable−

suitable

not recommended[7][8]not recommended[9]

suitablesuitablesuitable

−−−

[3][4][5]

[6]

[7][8][9]

For more detailed information on the BGA packages refer to the(LF)BGA Application Note(AN01026); order a copy from your Philips Semiconductors sales ofﬁce.

Allsurfacemount(SMD)packagesaremoisturesensitive.Dependinguponthemoisturecontent,themaximumtemperature(withrespecttotime)andbodysizeofthepackage,thereisariskthatinternalor external package cracks may occur due to vaporization of the moisture in them (the so calledpopcorn effect). For details, refer to the Drypack information in theDataHandbook IC26; IntegratedCircuit Packages; Section: Packing Methods.

For SDIP packages, the longitudinal axis must be parallel to the transport direction of theprinted-circuit board.

Hot bar soldering or manual soldering is suitable for PMFP packages.

These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and muston no account be processed through more than one soldering cycle or subjected to infrared reﬂowsolderingwithpeaktemperatureexceeding217°C±10°Cmeasuredintheatmosphereofthereﬂowoven. The package body peak temperature must be kept as low as possible.

These packages are not suitable for wave soldering. On versions with the heatsink on the bottomside,thesoldercannotpenetratebetweentheprinted-circuitboardandtheheatsink.Onversionswiththe heatsink on the top side, the solder might be deposited on the heatsink surface.

If wave soldering is considered, then the package must be placed at a 45° angle to the solder wavedirection. Thepackage footprint must incorporate solder thieves downstream and at the side corners.Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8mm; itis deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65mm.

Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than0.65mm; itis deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5mm.

Product dataRev. 03 — 10 December 200448 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

13.Revision history

Table 30:RevDate03

20041210

Revision history

CPCN-DescriptionProduct data (939775014451)Modiﬁcations:

•

0201

2004060320040330

There is no modiﬁcation to the data sheet. However, reader is advised to refer toAN10333(Rev. 02) “SC16CXXXB baud rate deviation tolerance” (939775014411)thatwas released together with this revision.

Product data (939775013317)Product data (939775011994)

Product dataRev. 03 — 10 December 200449 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

14.Data sheet status

LevelIII

Data sheet status[1]Objective dataPreliminary data

Product status[2][3]DevelopmentQualiﬁcation

DeﬁnitionThis data sheet contains data from the objective speciﬁcation for product development. PhilipsSemiconductors reserves the right to change the speciﬁcation in any manner without notice.

Thisdatasheetcontainsdatafromthepreliminaryspeciﬁcation.Supplementarydatawillbepublishedatalaterdate.PhilipsSemiconductorsreservestherighttochangethespeciﬁcationwithoutnotice,inorder to improve the design and supply the best possible product.

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves therighttomakechangesatanytimeinordertoimprovethedesign,manufacturingandsupply.Relevantchanges will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

IIIProduct dataProduction

[1][2][3]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet atURLhttp://www.semiconductors.philips.com.

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

15.Deﬁnitions

Short-form speciﬁcation —The data in a short-form speciﬁcation isextracted from a full data sheet with the same type number and title. Fordetailed information see the relevant data sheet or data handbook.

Limiting values deﬁnition — Limiting values given are in accordance withthe Absolute Maximum Rating System (IEC60134). Stress above one ormore of the limiting values may cause permanent damage to the device.These are stress ratings only and operation of the device at these or at anyother conditions above those given in the Characteristics sections of thespeciﬁcation is not implied. Exposure to limiting values for extended periodsmay affect device reliability.

Application information — Applications that are described herein for anyof these products are for illustrative purposes only. Philips Semiconductorsmakenorepresentationorwarrantythatsuchapplicationswillbesuitableforthe speciﬁed use without further testing or modiﬁcation.

16.Disclaimers

Life support —These products are not designed for use in life supportappliances, devices, or systems where malfunction of these products canreasonably be expected to result in personal injury. Philips Semiconductorscustomers using or selling these products for use in such applications do soat their own risk and agree to fully indemnify Philips Semiconductors for anydamages resulting from such application.

Right to make changes —Philips Semiconductors reserves the right tomake changes in the products - including circuits, standard cells, and/orsoftware - described or contained herein in order to improve design and/orperformance. When the product is in full production (status ‘Production’),relevant changes will be communicated via a Customer Product/ProcessChange Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys nolicence or title under any patent, copyright, or mask work right to these

products,andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,copyright,ormaskworkrightinfringement,unlessotherwisespeciﬁed.

Contact information

For additional information, please visithttp://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to:sales.addresses@www.semiconductors.philips.com.

939775014451

Fax: +31 40 27 24825

Product dataRev. 03 — 10 December 200450 of 51

元器件交易网www.cecb2b.com

Philips Semiconductors

SC16C650B

UART with 32-byteFIFOs andIrDA encoder/decoder

Contents

1General description. . . . . . . . . . . . . . . . . . . . . . 12Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Ordering information. . . . . . . . . . . . . . . . . . . . . 24Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 35Pinning information. . . . . . . . . . . . . . . . . . . . . . 45.1Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45.2Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 66Functional description . . . . . . . . . . . . . . . . . . 106.1Internal registers. . . . . . . . . . . . . . . . . . . . . . . 116.2FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 116.3Hardware ﬂow control. . . . . . . . . . . . . . . . . . . 126.4Software ﬂow control . . . . . . . . . . . . . . . . . . . 126.5Special feature software ﬂow control . . . . . . . 136.6Hardware/software and time-out interrupts. . . 136.7Programmable baud rate generator . . . . . . . . 146.8DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 166.9Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 166.10Loop-back mode. . . . . . . . . . . . . . . . . . . . . . . 167Register descriptions . . . . . . . . . . . . . . . . . . . 187.1Transmit (THR) and Receive (RHR)

Holding Registers . . . . . . . . . . . . . . . . . . . . . 197.2Interrupt Enable Register (IER) . . . . . . . . . . . 197.2.1IER versus Receive FIFO interrupt

mode operation . . . . . . . . . . . . . . . . . . . . . . . 207.2.2IER versus Receive/Transmit FIFO polled

mode operation . . . . . . . . . . . . . . . . . . . . . . . 207.3FIFO Control Register (FCR) . . . . . . . . . . . . . 217.3.1DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 217.3.2FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 217.4Interrupt Status Register (ISR). . . . . . . . . . . . 237.5Line Control Register (LCR). . . . . . . . . . . . . . 247.6Modem Control Register (MCR). . . . . . . . . . . 257.7Line Status Register (LSR). . . . . . . . . . . . . . . 277.8Modem Status Register (MSR). . . . . . . . . . . . 287.9Scratchpad Register (SPR) . . . . . . . . . . . . . . 297.10Enhanced Feature Register (EFR). . . . . . . . . 297.11

SC16C650B external reset conditions . . . . . . 31

Allrightsarereserved.Reproductioninwholeorinpartisprohibitedwithoutthepriorwritten consent of the copyright owner.

Theinformationpresentedinthisdocumentdoesnotformpartofanyquotationorcontract,isbelievedtobeaccurateandreliableandmaybechangedwithoutnotice.Noliabilitywillbeacceptedbythepublisherforanyconsequenceofitsuse.Publicationthereofdoesnotconveynorimplyanylicenseunderpatent-orotherindustrialorintellectual property rights.

Date of release: 10 December 2004

Document order number: 939775014451

8Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 319Static characteristics . . . . . . . . . . . . . . . . . . . 3210Dynamic characteristics. . . . . . . . . . . . . . . . . 3310.1Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 3411Package outline. . . . . . . . . . . . . . . . . . . . . . . . 4212Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4612.1Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . 4612.2Through-hole mount packages . . . . . . . . . . . 4612.2.1Soldering by dipping or by solder wave . . . . . 4612.2.2Manual soldering . . . . . . . . . . . . . . . . . . . . . . 4612.3Surface mount packages . . . . . . . . . . . . . . . . 4612.3.1Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 4612.3.2Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 4712.3.3Manual soldering . . . . . . . . . . . . . . . . . . . . . . 4712.4Package related soldering information. . . . . . 4813Revision history . . . . . . . . . . . . . . . . . . . . . . . 4914Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 5015Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5016

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .

因篇幅问题不能全部显示，请点此查看更多更全内容

查看全文

全部栏目

SC16C650BIN40资料