专利名称：SYNCHRONIZATION OF SERIAL MEMORY发明人：KAZUO KATAGI申请号：US3643220D申请日：19700326公开号：US3643220A公开日：19720215
摘要：A delay line refresh memory stores the bits to be displayed on a visual displaymeans such as a television receiver. A shift register in the feedback loop applies thestored bits back to the input circuit of the memory. Synchronization pulses which occuronce each recirculation period are employed to determine which stage of the register toconnect back to the memory, that is, to determine the amount of delay which must beinserted in the memory feedback loop to make the stored data synchronous with thesynchronization pulses.
申请人：RCA CORP.
更多信息请下载全文后查看
因篇幅问题不能全部显示，请点此查看更多更全内容