eda实验报告最终版

实验二

1、24进制加法计数器的程序：

LIBRARY Ieee;

USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; ENTITY count24 IS

PORT(en,clk: IN STD_LOGIC;

qa: out STD_LOGIC_VECTOR(3 DOWNTO 0); --个位数计数

qb: out STD_LOGIC_VECTOR(1 DOWNTO 0)); --十位数计数 END count24;

ARCHITECTURE a1 OF count24 IS BEGIN process(clk)

variable tma: STD_LOGIC_VECTOR(3 DOWNTO 0); variable tmb: STD_LOGIC_VECTOR(1 DOWNTO 0); begin

if clk'event and clk='1' then if en='1' then

if tma=\"1001\" then tma:=\"0000\";tmb:=tmb+1;

Elsif tmb=\"10\" and tma=\"0011\" then tma:=\"0000\"; tmb:=\"00\"; else tma:=tma+1; end if; end if; end if; qa<=tma; qb<=tmb; end process; END a1;

2，60进制的加法器的实验程序

LIBRARY Ieee;

USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; ENTITY count60 IS

PORT(en,clk: IN STD_LOGIC;

qa: out STD_LOGIC_VECTOR(3 DOWNTO 0); --个位数计数

qb: out STD_LOGIC_VECTOR(2 DOWNTO 0)); --十位数计数 END count60;

ARCHITECTURE a1 OF count60 IS BEGIN process(clk)

variable tma: STD_LOGIC_VECTOR(3 DOWNTO 0); variable tmb: STD_LOGIC_VECTOR(2 DOWNTO 0); begin

if clk'event and clk='1' then if en='1' then

if tma=\"1001\" and tmb=\"101\" then tmb:=\"000\"; tma:=\"0000\" ;

Elsif tma=\"1001\" then tma:=\"0000\";tmb:=tmb+1; else tma:=tma+1; end if; end if; end if; qa<=tma; qb<=tmb; end process; END a1;

实验三

9、采用VHDL语言描述以上3-8译码器

LIBRARY IEEE ;

USE IEEE.STD_LOGIC_1164.ALL ; ENTITY s3_8 IS

PORT ( A : IN STD_LOGIC_VECTOR(2 DOWNTO 0); D : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ; END ;

ARCHITECTURE one OF s3_8 IS BEGIN

PROCESS( A ) BEGIN

CASE A IS

WHEN \"000\" => D <= \"00000001\" ; WHEN \"001\" => D <= \"00000010\" ; WHEN \"010\" => D <= \"00000100\" ; WHEN \"011\" => D <= \"00001000\" ; WHEN \"100\" => D <= \"00010000\" ; WHEN \"101\" => D <= \"00100000\" ; WHEN \"110\" => D <= \"01000000\" ; WHEN \"111\" => D <= \"10000000\" ; WHEN OTHERS => NULL ; END CASE ; END PROCESS ; END ;

实验四

1、用VHDL语言设计一个四舍五入判别电路，其输入为8421BCD码，要求当输入大于或等于５时，判别电路输出为１，反之为０。参考电路原理图如图4.1所示。

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity s4_5 is

port(D0,D1,D2,D3:in std_logic; OUT1:out std_logic); end entity s4_5;

architecture one of s4_5 is begin

process(D0,D1,D2,D3) variable a1: std_logic; variable b1: std_logic; begin

a1:=(D0 and D2); b1:=(D1 and D2);

OUT1<=a1 OR b1 or D3; end process; end one;

图4.1 四舍五入判别参考电路

2、用VHDL语言设计四个开关控制一盏灯的逻辑电路，要求改变任意开关的状态能够引起灯亮灭状态的改变。（即任一开关的合断改变原来灯亮灭的状态，参考电路原理图如图4.2所示。）

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all; entity k4 is

port(k0,k1,k2,k3:in std_logic; OUT1:out std_logic); end entity k4;

architecture one of k4 is begin

process(k0,k1,k2,k3) variable a1: std_logic; variable b1: std_logic; begin

a1:=(k0 xor k1); b1:=(k2 xor k3); OUT1<=a1 xor b1; end process; end one;

图4.2 灯控参考电路

3、用VHDL语言设计一个优先排队电路（参考电路原理图如图4.3所示），其中：A=1，最高优先级；B=1，次高优先级；C=1， 最低优先级。要求输出端最多只能有一端为“１”，即只能是优先级较高的输入端所对应的输出端为“１”。

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity youxianji is

port(A : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

D : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); end entity youxianji;

architecture one of youxianji is begin process(A) begin

CASE A IS

WHEN \"000\" => D <= \"000\" ; WHEN \"001\" => D <= \"001\" ; WHEN \"010\" => D <= \"010\" ; WHEN \"011\" => D <= \"010\" ;

WHEN \"100\" => D <= \"100\" ; WHEN \"101\" => D <= \"100\" ; WHEN \"110\" => D <= \"100\" ; WHEN \"111\" => D <= \"100\" ; WHEN OTHERS => NULL ; END CASE ; end process; end one;

图4.3 优先排队参考电路

4、自行设计纪录方式，完成实验报告 (1)

（2）

(3)

实验五

RS触发器 library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity sy51 is

port(rd,sd:in std_logic; q,nq:out std_logic); end entity sy51;

architecture one of sy51 is begin

process(rd,sd)

variable a1: std_logic; variable b1: std_logic; begin

a1:=not(sd and b1); b1:=not(rd and a1); q<=a1; nq<=b1; end process; end one;

实验六

实验七

实验八

实验九

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity second is port (

CLK : in std_logic; RESET : in std_logic;

A : out std_logic_vector(3 downto 0); B : out std_logic_vector(3 downto 0); CKMIN : out std_logic ); end second;

architecture trans of second is

signal A_xhdl0 : std_logic_vector(3 downto 0); signal B_xhdl1 : std_logic_vector(3 downto 0); begin

-- Drive referenced outputs A <= A_xhdl0; B <= B_xhdl1;

process (CLK, RESET) begin

if (RESET = '1') then

A_xhdl0<=\"0000\"; B_xhdl1<=\"0000\"; elsif (CLK'event and CLK = '1') then

if (A_xhdl0 = \"1001\" and B_xhdl1 = \"0101\") then A_xhdl0<=\"0000\"; B_xhdl1<=\"0000\"; elsif (A_xhdl0 = \"1001\") then

A_xhdl0 <= \"0000\";

B_xhdl1 <= B_xhdl1 + \"0001\"; else

A_xhdl0 <= A_xhdl0 + \"0001\"; end if; end if; end process;

process (CLK, RESET) begin

if (RESET = '1') then CKMIN <= '0';

elsif (CLK'event and CLK = '1') then

if (A_xhdl0 = \"1001\" and B_xhdl1 = \"0101\") then CKMIN <= '1'; else

CKMIN <= '0'; end if; end if; end process; end trans;

LIBRARY ieee;

USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all;

ENTITY minute IS PORT (

CKMIN : IN STD_LOGIC; RESET : IN STD_LOGIC; SETMIN : IN STD_LOGIC;

A : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CKHOUR : OUT STD_LOGIC );

END minute;

ARCHITECTURE trans OF minute IS SIGNAL c : STD_LOGIC;

SIGNAL A_xhdl0 : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL B_xhdl1 : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN

-- Drive referenced outputs A <= A_xhdl0;

B <= B_xhdl1;

c <= CKMIN XOR SETMIN; PROCESS (c, RESET) BEGIN

IF (RESET = '1') THEN

A_xhdl0 <= \"0000\"; B_xhdl1 <= \"0000\"; ELSIF (c'EVENT AND c = '1') THEN

IF (A_xhdl0 = \"1001\" AND B_xhdl1 = \"0101\") THEN A_xhdl0 <= \"0000\"; B_xhdl1 <= \"0000\"; ELSIF (A_xhdl0 = \"1001\") THEN A_xhdl0 <= \"0000\";

B_xhdl1 <= B_xhdl1 + \"0001\"; ELSE

A_xhdl0 <= A_xhdl0 + \"0001\"; END IF; END IF; END PROCESS;

PROCESS (c, RESET) BEGIN

IF (RESET = '1') THEN CKHOUR <= '0';

ELSIF (c'EVENT AND c = '1') THEN

IF (A_xhdl0 = \"1001\" AND B_xhdl1 = \"0101\") THEN CKHOUR <= '1'; ELSE

CKHOUR <= '0'; END IF; END IF; END PROCESS; END trans;

LIBRARY ieee;

USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all;

ENTITY hour IS PORT (

CKHOUR : IN STD_LOGIC; RESET : IN STD_LOGIC; SETHOUR : IN STD_LOGIC;

A : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); B : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) );

END hour;

ARCHITECTURE trans OF hour IS SIGNAL c : STD_LOGIC;

SIGNAL A_xhdl0 : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL B_xhdl1 : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN

-- Drive referenced outputs A <= A_xhdl0; B <= B_xhdl1;

c <= CKHOUR XOR SETHOUR; PROCESS(RESET,c) BEGIN

IF (RESET = '1') THEN

A_xhdl0 <= \"0000\"; B_xhdl1 <= \"00\"; ELSIF (c'EVENT AND c = '1') THEN

IF (A_xhdl0 = \"0011\" AND B_xhdl1 = \"10\") THEN A_xhdl0 <= \"0000\"; B_xhdl1 <= \"00\"; ELSIF (A_xhdl0 = \"1001\") THEN A_xhdl0 <= \"0000\";

B_xhdl1 <= B_xhdl1 + \"01\"; ELSE

A_xhdl0 <= A_xhdl0 + \"0001\"; END IF; END IF; END PROCESS; END trans;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY deled IS PORT (

NUM : IN STD_LOGIC_VECTOR(3 DOWNTO 0); A : OUT STD_LOGIC; B : OUT STD_LOGIC; C : OUT STD_LOGIC; D : OUT STD_LOGIC; E : OUT STD_LOGIC; F : OUT STD_LOGIC; G : OUT STD_LOGIC );

END deled;

ARCHITECTURE trans OF deled IS

SIGNAL xhdl0 : STD_LOGIC_VECTOR(6 DOWNTO 0); BEGIN

(G,F,E,D,C,B,A) <= xhdl0; PROCESS (NUM) BEGIN

CASE NUM IS

WHEN \"0000\" =>

xhdl0 <= \"0111111\"; WHEN \"0001\" =>

xhdl0 <= \"0000110\"; WHEN \"0010\" =>

xhdl0 <= \"1011011\"; WHEN \"0011\" =>

xhdl0 <= \"1001111\"; WHEN \"0100\" =>

xhdl0 <= \"1100110\"; WHEN \"0101\" =>

xhdl0 <= \"1101101\"; WHEN \"0110\" =>

xhdl0 <= \"1111101\"; WHEN \"0111\" =>

xhdl0 <= \"0000111\"; WHEN \"1000\" =>

xhdl0 <= \"1111111\"; WHEN \"1001\" =>

xhdl0 <= \"1101111\"; WHEN \"1010\" =>

xhdl0 <= \"1000000\"; WHEN \"1011\" =>

xhdl0 <= \"1111100\"; WHEN \"1100\" =>

xhdl0 <= \"0111001\"; WHEN \"1101\" =>

xhdl0 <= \"1011110\"; WHEN \"1110\" =>

xhdl0 <= \"1111001\"; WHEN \"1111\" =>

xhdl0 <= \"1110001\"; WHEN OTHERS =>

xhdl0 <= \"XXXXXXX\"; END CASE; END PROCESS; END trans;