128K x 8 AutoStoreTM nvSRAM
QuantumTrapTM CMOS Nonvolatile Static RAM
DESCRIPTION
STK14CA8
FEATURES
• 25ns, 35ns and 45ns Access Times
• “Hands-off” Automatic STORE on Power Down with only a small capacitor
• STORE to QuantumTrap™ Nonvolatile
Elements is Initiated by Software , device pin or AutoStore™ on Power Down
• RECALL to SRAM Initiated by Software or Power Up
• Unlimited READ, WRITE and RECALL Cycles • 5mA Typical ICC at 200ns Cycle Time
• 1,000,000 STORE Cycles to QuantumTrap™ • 100-Year Data Retention to QuantumTrap™ • Single 3V +20%, -10% Operation
• Commercial and Industrial Temperatures • SOIC, SSOP and DIP Packages • RoHS Compliance
The Simtek STK14CA8 is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate
TM
Simtek’s QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent, nonvolatile data resides in the
TM
highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.
BLOCK DIAGRAM
A5A6A7A8A9A12 A13 A14 A15 A16 DQ0DQ1 DQ2 DQ3 DQ4DQ5 DQ6DQ7ROW DECODER Quantum Trap1024 X 1024STORESTATIC RAMARRAY 1024 X 1024RECALLVCC VCAP POWERCONTROL STORE/ RECALL CONTROL HSB SOFTWAREDETECT INPUT BUFFERS COLUMN I/OCOLUMN DECA15 – A0A0 A1 A2 A3 A4 A10 A11GEW Figure 1. Block Diagram
December 2004
1Document Control #ML0022 rev 1.0
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STK14CA8 PACKAGES VCAP A16 A14 A12 A7 A6 A5 A4 VSS DQ0 A3 A2 A1 A0 DQ1 DQ2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC A15HSB W A13A8 A9 A11 VSS DQ6GA10E DQ7DQ5DQ4DQ3VCCVCAPA16A14A12A7A6A5A4A3A2A1A0DQ0DQ1DQ2VSS1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32313029282726252423222120191817VCC A15HSB W A13A8A9A11GA10E DQ7DQ6DQ5DQ4DQ3 32 Pin SOIC or PDIPSSOPRelative PCB area usage. See website for detailed package size specifications. 2 48 Pin SSOP PIN DESCRIPTIONS Pin Name I/O Description A16 – A0 Input Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array. DQ7 –DQ0 I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM. E W G Input Input Input Chip Enable: The active low E input selects the device. Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the falling edge ofE . Output Enable: The active low G input enables the data output buffers during read cycles. De-assertingG high causes the DQ pins to tri-state. VCC Power Supply Power 3.0V +20%, -10% Hardware Store Busy: When low this output indicates a Hardware Store is in progress. When pulled low external HSB I/O to the chip it will initiate a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not connected. (Connection Optional) Autostore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile VCAP Power Supply elements. VSS Power Supply Ground (Blank) No Connect Unlabeled pins have no internal connection. December 2004 Document Control #ML0022 rev 1.0 元器件交易网www.cecb2b.com
STK14CA8
ABSOLUTE MAXIMUM RATINGSa -0.5V to +4.1V Power Supply Voltage -0.5V to (VCC + 0.5V) Voltage on Input Relative to VSS Voltage on Outputs -0.5V to (VCC + 0.5V) Temperature under Bias –55°C to 125°C Junction Temperature –55°C to 140°C –65°C to 150°C Storage Temperature 1W Power Dissipation DC Output Current (1 output at a time, 1s duration) 15mA Notes a: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at con-ditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-ing conditions for extended periods may affect reliability. Package Thermal Characteristics see website: http://www.simtek.com/ DC CHARACTERISTICS Commercial Industrial Symbol Parameter MIN MAX MIN MAX UnitsICC1 Average VCC Current 65 55 50 70 60 55 Notes ICC2 Average VCC Current during STORE Average VCC Current at tAVAV = 200ns 3 3 mA tAVAV = 25ns mA tAVAV = 35ns mA tAVAV = 45ns Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Don’t Care, VCC = max Average current for duration of STORE mA cycle (tSTORE). W ≥ (VCC – 0.2V) All Others Inputs Cycling, at CMOS Levels. Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Don’t Care Average current for duration of STORE cycle (tSTORE). E ≥ (VCC – 0.2V) All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V) Standby current level after nonvolatile cycle is complete. VCC = max ICC3 3V, 25°C, Typical 5 5 mA Average VCAP Current during AutoStore™ Cycle VCC Standby Current ICC4 3 3 mA ISB (Standby, Stable CMOS Input Levels) 2 2 mA IILK IOLK VIH VIL VOH VOL TA VCC VCAP Input Leakage Current Off-State Output Leakage Current Input Logic “1” Voltage Input Logic “0” Voltage Output Logic “1” Voltage Output Logic “0” Voltage Operating Temperature Operating Voltage Storage Capacitor ±1 2.0 VSS – 0.5 2.4 ±1 VCC + 0.3 0.8 0.4 µA V V V V o±1 ±1 µA VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G ≥ VIH All Inputs All Inputs IOUT = –2mA IOUT = 4mA 3.0V +20%, -10% Between Vcap pin and Vss, 5V rated. 2.0 VCC + 0.3 VSS – 0.5 2.4 0.8 0.4 0 70 –40 85 C 2.7 3.6 2.7 3.6 V17 57 17 57 µF December 2004 3Document Control #ML0022 rev 1.0
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STK14CA8 AC TEST CONDITIONS 0V to 3V Input Pulse Levels Input Rise and Fall Times ≤ 5ns Input and Output Timing Reference Levels 1.5V Output Load See Figure 2 and Figure 3 b CAPACITANCE (TA = 25°C, f = 1.0MHz) SYMBOL PARAMETER MAX UNITS CONDITIONS CIN Notes Input Capacitance 7 pF ∆V = 0 to 3V COUT Output Capacitance 7 pF ∆V = 0 to 3V b: These parameters are guaranteed but not tested 3.0V 577 Ohms 3.0V 577 OhmsOUTPUT 789 Ohms OUTPUT30 pF INCLUDING SCOPE ANDFIXTURE 789 Ohms5 pF 30 pF INCLUDING SCOPE ANDFIXTURE Figure 2. AC Output Loading Figure 3. AC Output Loading, for tristate specs ( tHZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ ) December 2004 4Document Control #ML0022 rev 1.0
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STK14CA8
SRAM READ CYCLES #1 & #2 NO. ctAVAV dtAVQV SYMBOLS STK14CA8-25 STK14CA8-35 STK14CA8-45 PARAMETER UNITS #1 #2 Alt. MIN MAX MIN MAX MIN MAX tELQV ctAVAV 1 2 3 4 5 6 7 8 9 10 11 tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold after Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby 25 3 3 0 0 25 25 12 10 10 25 35 3 3 0 0 35 35 15 13 13 35 45 3 3 0 0 45 45 20 15 15 45 ns ns ns ns ns ns ns ns ns ns ns tGLQV tELQX etEHQZ dtAXQX tGLQX etGHQZ tELICCb btEHICC Notes c: W must be high during SRAM READ cycles d: Device is continuously selected with E and G both low e: Measured ± 200mV from steady state output voltage f: HSB must remain high during READ and WRITE cycles. SRAM READ CYCLE #1: Address Controlledc,d,f SRAM READ CYCLE #2: E Controlledc,f 2 tAVAV2 tAVAV ADDRESS 5 tAXQX 3 tAVQV DATA VALID DQ (DATA OUT) 1 tELQV 11 tEHICCL 7 tEHQZ ADDRESS E 6 tELQX G 4 8 DQ (DATA OUT) tGLQX tGLQV9 tGHQZ DATA VALID 10 tELICCH ACTIVEICC STANDBY December 2004 5Document Control #ML0022 rev 1.0
STK14CA8 SRAM WRITE CYCLES #1 & #2 NO. SYMBOLS STK14CA8-25 STK14CA8-35 STK14CA8-45 UNITS PARAMETER #1 #2 Alt. MIN MAX MIN MAX MIN MAX tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold after End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold after End of Write Write Enable to Output Disable Output Active after End of Write 12 tAVAV 13 tWLWH 14 tELWH 25 35 45 ns 20 25 30 ns 20 25 30 ns 10 12 15 ns 0 0 0 ns 20 25 30 ns 0 0 0 ns 0 0 0 ns 10 13 15 ns 3 3 3 ns 15 tDVWH 16 tWHDX 17 tAVWH 18 tAVWL 19 tWHAX 20 tWLQZe,g 21 tWHQX Notes g: If W is low when E goes low, the outputs remain in the high-impedance state. h: E or W must be ≥ VIH during address transitions. SRAM WRITE CYCLE #1: W Controlledh,f DATA OUT PREVIOUS DATA 12 tAVAVADDRESS 14 tELWH 19 tWHAX E 17 tAVWH 13 tWLWH 15 tDVWHDATA VALID 18 tAVWL W DATA IN 20 tWLQZ 16 tWHDX HIGH IMPEDANCE 21 tWHQX SRAM WRITE CYCLE #2: E Controlledh,f 12 tAVAV ADDRESS 18 tAVEL 14 tELEH 19 tEHAX E 17 tAVEH W 13 tWLEH 15 tDVEH 16 tEHDX DATA VALID HIGH IMPEDANCE DATA IN DATA OUT December 2004 6Document Control #ML0022 rev 1.0 元器件交易网www.cecb2b.com
STK14CA8
MODE SELECTION E H L L W X H L G X L X A15 - A0 MODE X X X Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Autostore Disable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Autostore Enable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall I/O POWER Standby Active Active NOTES Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z 0x4E38 0xB1C7 0x83E0 L H L 0x7C1F 0x703F 0x8B45 0x4E38 0xB1C7 0x83E0 L H L 0x7C1F 0x703F 0x4B46 0x4E38 0xB1C7 0x83E0 L H L 0x7C1F 0x703F 0x8FC0 0x4E38 0xB1C7 0x83E0 L H L 0x7C1F 0x703F 0x4C63 Active i, j, k Active i, j, k Active ICC2 i, j, k Active i, j, k Notes i: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. j: While there are 17 addresses on the STK14CA8, only the lower 16 are used to control software modes k: I/O state depends on the state of G . The I/O table shown assumes G low. December 2004 7Document Control #ML0022 rev 1.0
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STK14CA8 AutoStore™ /POWER-UP RECALL NO. SYMBOLS PARAMETER STK14CA8 UNITS NOTES Standard Alternate MIN MAX tHLHZ Power-up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level VCC Rise Time l 20 ms m 12.5 ms 2.55 2.65 V 22 tHRECALL 23 tSTORE 24 VSWITCH 25 tVCCRISE 150 µs Notes l: tHRECALL starts from the time VCC rises above VSWITCH m: If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place AutoStore™/POWER-UP RECALL 24 VSWITCH VCC STORE occurs only if a SRAM write has happened. No STORE occurs without at least one SRAM write. 25 tVCCRISE 23 tSTORE 23 tSTORE AutoStoreTM POWER-UP RECALL 22 tHRECALL 22 tHRECALL Read & Write Inhibited Note: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH.POWER-UP RECALL BROWN OUT TMAutoStore POWER-UP RECALL POWER DOWN TMAutoStore December 2004 8Document Control #ML0022 rev 1.0 STK14CA8
SOFTWARE-CONTROLLED STORE/RECALL CYCLEn,o SYMBOLS NO. E cont 26 tAVAV 27 tAVEL 28 tELEH 29 tELAX 30 tRECALL G cont tAVAV tAVGL tGLGH tGLAX tRECALL tRC tAS tCW STORE/RECALL Initiation Cycle Time Address Set-up Time Clock Pulse Width Address Hold Time RECALL Duration Alt. PARAMETER STK14CA8-25 STK14CA8-35 STK14CA8-45 UNITS NOTES MIN MAX MIN MAX MIN MAX 25 35 45 ns o 0 0 0 ns 20 25 30 ns 20 20 20 ns 40 40 40 µs Notes n: The software sequence is clocked with E controlled READs or G controlled READs. o: The six consecutive addresses must be read in the order listed in the Mode Selection Table. W must be high during all six consecutive cycles. SOFTWARE STORE/RECALL CYCLE: E Controlledo 26 tAVAV ADDRESS 27 tAVEL ADDRESS #1 26 tAVAVADDRESS #6 E 28 tELEH DQ (DATA) G 29 tELAX 23 tSTOREDATA VALID DATA VALID /30 tRECALL HIGH IMPEDENCE SOFTWARE STORE/RECALL CYCLE: G Controlledo ADDRESS 26 tAVAV ADDRESS #1 26 tAVAVADDRESS #6 E 27 tAVGL 28 tGLGH G 29 tGLAX DQ (DATA) DATA VALID DATA VALID 23 tSTORE/30 tRECALL HIGH IMPEDENCE December 2004 9Document Control #ML0022 rev 1.0 STK14CA8 HARDWARE STORE CYCLE NO. 31 32 SYMBOLS Standard Alternate tDELAY tHLHX tHLQZ PARAMETER UNITS NOTES MIN MAX 1 15 300 µs ns ns p STK14CA8 Time Allowed to Complete SRAM Cycle Hardware STORE Pulse Width tHLBL Hardware STORE Low to STORE Busy 33 Notes p: Read and Write cycles in progress before HSB is asserted are given this amount of time to complete. HARDWARE STORE CYCLE 32 HSB (OUT) 33 tHLBL HIGH IMPEDENCE tHLHX HSB (IN) 23 tSTOREHIGH IMPEDENCE DQ (DATA OUT) 31 tDELAY DATA VALID DATA VALIDDecember 2004 10Document Control #ML0022 rev 1.0 元器件交易网www.cecb2b.com
STK14CA8
DEVICE OPERATION nvSRAM The STK14CA8 nvSRAM is made up of two functional components paired in the same physical cell. These are a SRAM memory cell and a nonvolatile QuantumTrap™ cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture allows all cells to be stored and recalled in parallel. During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited. The STK14CA8 supports unlimited reads and writes just like a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to 1 million STORE operations. SRAM WRITE A WRITE cycle is performed whenever E and W are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low. AutoStore™ OPERATION The STK14CA8 stores data to nvSRAM using one of three storage operations. These three operations are Hardware Store, activated by HSB , Software Store, actived by an address sequence, and AutoStore™, on device power down. AutoStore™ operation is a unique feature of Simtek QuantumTrap™ technology and is enabled by default on the STK14CA8. During normal operation, the device will draw current from Vcc to charge a capacitor connected to the Vcap pin. This stored charge will be used by the chip to perform a single STORE operation. If the voltage on the Vcc pin drops below Vswitch, the part will automatically disconnect the Vcap pin from Vcc. A STORE operation will be initiated with power provided by the Vcap capacitor. Figure 4 shows the proper connection of the storage capacitor (Vcap) for automatic store operation. Refer to the DC CHARACTERISTICS table for the size of Vcap. The voltage on the Vcap pin is driven to 5V by a charge pump internal to the chip. A pull up should be placed on W to hold it inactive during power up. To reduce unneeded nonvolatile stores, AutoStore™ and Hardware Store operations will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. The HSB signal can be monitored by the system to detect an AutoStore™ cycle is in progress. SRAM READ The STK14CA8 performs a READ cycle whenever E and G are low while W and HSB are high. The address specified on pins A16-0 determines which of the 131,072 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G , the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high, or W or HSB is brought low. VCCVCAPVCC10k OhmVCAPW0.1µF Figure 4: AutoStoreTM Mode December 2004 11Document Control #ML0022 rev 1.0
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STK14CA8
HARDWARE STORE(HSB ) OPERATION
The STK14CA8 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin can be used to request a hardware STORE cycle. When theHSB pin is driven low, the STK14CA8 will conditionally initiate a STORE operation after tDELAY. An actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress.
SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the STK14CA8 will continue SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high.
During any STORE operation, regardless of how it was initiated, the STK14CA8 will continue to drive the HSB pin low, releasing it only when the STORE is complete. Upon completion of the STORE operation the STK14CA8 will remain disabled until the HSB pin returns high. If
HSB is not used, it should be left unconnected.
SOFTWARE STORE
Data can be transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK14CA8 software STORE cycle is initiated by executing sequential E controlled READ cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence, or the sequence will be aborted and no STORE or RECALL will take place.
To initiate the software STORE cycle, the following READ sequence must be performed: 1. Read address 0x4E38 Valid READ
0xB1C7
0x83E0 0x7C1F 0x703F 0x8FC0
Valid READ Valid READ Valid READ Valid READ
Initiate STORE cycle
2. Read address 3. Read address 4. Read address 5. Read address 6. Read address
The software sequence may be clocked with Econtrolled READs or G controlled READs.
HARDWARE RECALL (POWER-UP)
During power up, or after any low-power condition (VCC < VSWITCH), an internal RECALL request will be latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will SOFTWARE RECALL automatically be initiated and will take tHRECALL to Data can be transferred from the nonvolatile memory complete. to the SRAM by a software address sequence. A
software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of E controlled READ operations must be performed: 1. Read address 0x4E38 Valid READ
2. Read address 3. Read address 4. Read address 5. Read address 6. Read address
0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63
Valid READ Valid READ Valid READ Valid READ
Initiate RECALL cycle
Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation.
December 2004 12Document Control #ML0022 rev 1.0
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STK14CA8
Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the nonvolatile elements. NOISE CONSIDERATIONS The STK14CA8 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1µF connected between VCC and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, careful routing of power, ground and signals will reduce circuit noise. PREVENTING AUTOSTORETM The AutoStore™ function can be disabled by initiat-ing an AutoStore Disable sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore Disable sequence, the following sequence of E controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Valid READ Valid READ Valid READ Valid READ AutoStore Disable LOW AVERAGE ACTIVE POWER CMOS technology provides the STK14CA8 this the benefit of drawing significantly less current when it is cycled at times longer than 50ns. Figure 5 shows the relationship between ICC and READ/WRITE cycle time. Worst-case current consumption is shown for commercial temperature range, VCC = 3.6V, and chip enable at maximum frequency. Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK14CA8 depends on the following items: 1. The duty cycle of chip enable. 2. The overall cycle rate for accesses. 3. The ratio of READs to WRITEs. 4. The operating temperature. 5. The VCC level. 6. I/O loading. 2. Read address 3. Read address 4. Read address 5. Read address 6. Read address The AutoStore™ can be re-enabled by initiating an AutoStore Enable sequence. A sequence of read operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore Enable sequence, the following sequence of E controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 Valid READ Valid READ Valid READ Valid READ AutoStore Enable 2. Read address 3. Read address 4. Read address 5. Read address 6. Read address Average Active Current (mA)5040302010050100150200300Cycle Time (ns) WritesIf the AutoStore™ function is disabled or re-enabled a manual STORE operation (Hardware or Software) needs to be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore™ enabled. DATA PROTECTION The STK14CA8 protects data from corruption during low-voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low-voltage condition is detected when VCC < VSWITCH . If the STK14CA8 is in a WRITE mode (both E and W low ) at power-up, after a RECALL, or after a STORE, the WRITE will be inhibited until a negative transition on E or W is detected. This protects against inadvertent writes during power up or brown out conditions. ReadsFigure 5 Current vs. Cycle time December 2004 13Document Control #ML0022 rev 1.0
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STK14CA8 ORDERING INFORMATION STK14CA8 – R F 45 I Temperature Range Blank = Commercial (0 to 70ºC) I = Industrial (-40 to 85ºC) Access Time 25 = 25ns 35 = 35ns 45 = 45ns Lead Finish Blank = 85% Sn / 15% Pb F = 100% Sn (Matte Tin) RoHS Compliant Package N = Plastic 32-pin 300 mil SOIC (50 mil pitch) R = Plastic 48-pin 300 mil SSOP (25 mil pitch) W = Plastic 32-pin 600 mil DIP (100 mil pitch) December 2004 14Document Control #ML0022 rev 1.0
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STK14CA8 Document Revision History Revision Date Publish new datasheet 0.0 January 2003 Summary Add 48 pin SSOP, Modify AutoStore drawing (Figure 2), Update Mode Selection Table and Absolute Maximum Ratings, Added G control software 0.1 May 2003 store 0.2 September 2003 Added lead-free lead finish Parameter Old Value New Value Notes 1.0 December 2004 Vcap Min 10µF 17 µF tVCCRISE NA 150 µs New Spec ICC1 Max Com. 35 mA 50 mA @ 45ns access ICC1 Max Com. 40 mA 55 mA @ 35ns access ICC1 Max Com. 50 mA 65 mA @ 25ns access ICC1 Max Ind. 35 mA 55 mA @ 45ns access ICC1 Max Ind. 45 mA 60 mA @ 35ns access ICC1 Max Ind. 55 mA 70 mA @ 25ns access ICC2 Max 1.5 mA 3.0 mA Com. & Ind. ICC4 Max 0.5 mA 3 mA Com & Ind. tHRECALL 5 ms 20 ms tSTORE 10 ms 12.5 ms tRECALL 20µs 40µs tGLQV 10ns 12ns 25 ns device SIMTEK STK14CA8 Data Sheet, December 2004 Copyright 2004, Simtek Corporation. All rights reserved. This datasheet may only be printed for the express use of Simtek Customers. No part of this datasheet may be reproduced in any other form or means without express written permission from Simtek Corporation. The information contained in this publication is believed to be accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein constitutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark or other proprietary right.
December 2004
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