三位十进制计数显示器
一、 实验目的：
1、 学习时序电路中多进程的VHDL描述方法
2、 掌握层次化设计方法
3、 熟悉EDA的仿真分析和硬件测试技术
二、 实验原理：
三位十进制计数显示器的设计院分三步完成，先设计三位十进制计数电路，再设计显示译码电路，最后建立一个顶层文件将两者连接起来。
三、 实验设备：
计算机一台
操作系统：WINDOWS XP
软件： ispDesignEXPERT System
四、 实验步骤：
参考程序：
1、三位计数模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT3 IS
PORT(CLK,RESET,CIN:IN STD_LOGIC;
CO:OUT STD_LOGIC;
A,B,C:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COUNT3;
ARCHITECTURE ART OF COUNT3 IS
SIGNAL AP,BP,CP:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
KK1:PROCESS(CLK) IS
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF RESET='0' THEN
AP<=\"0000\";
ELSIF CIN='1' THEN
IF AP=\"1001\" THEN
AP<=\"0000\";
ELSE
AP<=AP+'1';
END IF;
END IF;
END IF;
END PROCESS KK1;
KK2:PROCESS(CLK) IS
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF RESET='0' THEN
BP<=\"0000\";
ELSIF CIN='1' AND AP=\"1001\" THEN
IF BP=\"1001\" THEN
BP<=\"0000\";
ELSE
BP<=BP+'1';
END IF;
END IF;
END IF;
END PROCESS KK2;
KK3:PROCESS(CLK) IS
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF RESET='0' THEN
CP<=\"0000\";
ELSIF CIN='1' AND AP=\"1001\" AND BP=\"1001\" THEN
IF CP=\"1001\" THEN
CP<=\"0000\";
ELSE
CP<=CP+'1';
END IF;
END IF;
END IF;
END PROCESS KK3;
A<=AP;
B<=BP;
C<=CP;
END ART;
2、译码电路
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY YIMA7 IS
PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
YIMA:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END YIMA7;
ARCHITECTURE ART OF YIMA7 IS
BEGIN
PROCESS(A) IS
BEGIN
CASE A IS
WHEN \"0000\"=>YIMA<=\"1000000\";
WHEN \"0001\"=>YIMA<=\"1111001\";
WHEN \"0010\"=>YIMA<=\"0100100\";
WHEN \"0011\"=>YIMA<=\"0110000\";
WHEN \"0100\"=>YIMA<=\"0011001\";
WHEN \"0101\"=>YIMA<=\"0010010\";
WHEN \"0110\"=>YIMA<=\"0000010\";
WHEN \"0111\"=>YIMA<=\"1111000\";
WHEN \"1000\"=>YIMA<=\"0000000\";
WHEN \"1001\"=>YIMA<=\"0010000\";
WHEN \"1010\"=>YIMA<=\"0001000\";
WHEN \"1011\"=>YIMA<=\"0000011\";
WHEN \"1100\"=>YIMA<=\"1000110\";
WHEN \"1101\"=>YIMA<=\"0100001\";
WHEN \"1110\"=>YIMA<=\"0000110\";
WHEN \"1111\"=>YIMA<=\"0001110\";
WHEN OTHERS=>YIMA<=\"1111111\";
END CASE;
END PROCESS;
END ART;
3、顶层文件
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY JISHUXIANSHI IS
PORT(CLK,RESET,ENA: IN STD_LOGIC;
SEG1,SEG2,SEG3:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END JISHUXIANSHI;
ARCHITECTURE ART OF JISHUXIANSHI IS
COMPONENT YIMA7
PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
YIMA:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END COMPONENT;
COMPONENT COUNT3
PORT(CLK,RESET,CIN:IN STD_LOGIC;
A,B,C:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
SIGNAL IN_A,IN_B,IN_C:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
U0:COUNT3 PORT MAP(CLK,RESET,ENA,IN_A,IN_B,IN_C);
U1:YIMA7 PORT MAP(IN_A,SEG1);
U2:YIMA7 PORT MAP(IN_B,SEG2);
U3:YIMA7 PORT MAP(IN_C,SEG3);
END ART;
源文件编译及综合
引脚锁定
硬件测试：
因篇幅问题不能全部显示，请点此查看更多更全内容