ASAHI KASEI
[AK4381]
AK4381108dB 192kHz 24-Bit 2ch ∆Σ DAC GENERAL DESCRIPTION
The AK4381 offers the perfect mix for cost and performance based audio systems. Using AKM's multi bit architecture for its modulator the AK4381 delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4381 has full differential SCF outputs, removing the need for AC coupling capacitors and increasing performance for systems with excessive clock jitter. The 24 Bit word length and 192kHz sampling rate make this part ideal for a wide range of applications including DVD-Audio. The AK4381 is offered in a space saving 16pin TSSOP package.
FEATURES
o Sampling Rate Ranging from 8kHz to 192kHz o 128 times Oversampling (Normal Speed Mode) o 64 times Oversampling (Double Speed Mode) o 32 times Oversampling (Quad Speed Mode) o 24-Bit 8 times FIR Digital Filter o On chip SCF
o Digital de-emphasis for 32k, 44.1k and 48kHz sampling o Soft mute
o Digital Attenuator (Linear 256 steps)
o I/F format: 24-Bit MSB justified, 24/20/16-Bit LSB justified or I2S o Master clock: 256fs, 384fs, 512fs or 768fs (Normal Speed Mode)
128fs, 192fs, 256fs or 384fs (Double Speed Mode) 128fs, 192fs (Quad Speed Mode)
o THD+N: -94dB
o Dynamic Range: 108dB
o High Tolerance to Clock Jitter o Power supply: 4.75 to 5.25V
o Very Small Package: 16pin TSSOP (6.4mm x 5.0mm) o AK4382A Pin Compatible
MCLKVDD
CSNCCLKCDTI
µPInterfaceDe-emphasisControlClockDividerVSSDZFLDZFR
LRCKBICKSDTI
AudioDataInterface8XInterpolator8XInterpolator∆ΣModulator∆ΣModulatorSCFAOUTL+AOUTL-AOUTR+AOUTR-
SCFPDN
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ASAHI KASEI
[AK4381]
n Ordering Guide
AK4381VT -40 ∼ +85°C 16pin TSSOP (0.65mm pitch) AKD4381 Evaluation Board for AK4381
n Pin Layout
MCLKBICKSDTILRCKPDNCSNCCLKCDTI
12345678161514DZFLDZFRVDDVSSAOUTL+AOUTL-AOUTR+AOUTR-
TopView131211109
PIN/FUNCTION
Function
Master Clock Input Pin
An external TTL clock should be input on this pin.
2 BICK I Audio Serial Data Clock Pin 3 SDTI I Audio Serial Data Input Pin 4 LRCK I L/R Clock Pin 5 PDN I Power-Down Mode Pin
When at “L”, the AK4381 is in the power-down mode and is held in reset. The AK4381 should always be reset upon power-up.
6 CSN I Chip Select Pin 7 CCLK I Control Data Input Pin 8 CDTI I Control Data Input Pin in serial mode 9 AOUTR- O Rch Negative Analog Output Pin 10 AOUTR+ O Rch Positive Analog Output Pin 11 AOUTL- O Lch Negative Analog Output Pin 12 AOUTL+ O Lch Positive Analog Output Pin 13 VSS - Ground Pin 14 VDD - Power Supply Pin 15 DZFR O Rch Data Zero Input Detect Pin 16 DZFL O Lch Data Zero Input Detect Pin Note: All input pins should not be left floating. No. 1
Pin Name MCLK
I/O I
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ASAHI KASEI
[AK4381]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1) Parameter Symbol min max Power Supply VDD -0.3 6.0 Input Current (any pins except for supplies) IIN - ±10 Input Voltage VIND -0.3 VDD+0.3 Ambient Operating Temperature Ta -40 85 Storage Temperature Tstg -65 150
Note: 1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Units V mA V °C °C
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1) Parameter Symbol min typ Power Supply VDD 4.75 5.0
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
max 5.25
Units V
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ASAHI KASEI
[AK4381]
ANALOG CHARACTERISTICS
(Ta=25°C; VDD=5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data; Measurement frequency=20Hz ∼ 20kHz; RL ≥4kΩ; unless otherwise specified) Parameter min typ max Resolution 24 Dynamic Characteristics (Note 3) THD+N fs=44.1kHz 0dBFS -94 -84
BW=20kHz -60dBFS -44 - fs=96kHz 0dBFS -92 - BW=40kHz -60dBFS -41 - fs=192kHz 0dBFS -92 - BW=40kHz -60dBFS -41 -
Dynamic Range (-60dBFS with A-weighted) (Note 4) 100 108 S/N (A-weighted) (Note 5) 100 108 Interchannel Isolation (1kHz) 90 110 Interchannel Gain Mismatch 0.2 0.5 DC Accuracy Gain Drift 100 - Output Voltage (Note 6) ±2.55 ±2.75 ±2.95 Load Resistance (Note 7) 4 Power Supplies
Power Supply Current (VDD)
17 27 Normal Operation (PDN = “H”, fs≤96kHz)
20 32 Normal Operation (PDN = “H”, fs=192kHz)
10 100 Power-Down Mode (PDN = “L”) (Note 8)
Notes: 3. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
4. 100dB at 16bit data.
5. S/N does not depend on input bit length.
6. Full-scale voltage (0dB). Output voltage scales with the voltage of VREF, AOUT (typ.@0dB)=(AOUT+)-(AOUT-)=±2.75Vpp × VREF/5. 7. For AC-load. 4kΩ for DC-load.
8. All digital inputs including clock pins (MCLK, BICK and LRCK) are held VDD or VSS.
Units Bits dB dB dB dB dB dB dB dB dB dB ppm/°C Vpp kΩ mA mA µA
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[AK4381]
SHARP ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; VDD = 4.75 ∼ 5.25V; fs = 44.1kHz; DEM = OFF; SLOW = “0”) Parameter Symbol min typ max Units Digital filter
PB 0 20.0 kHz Passband ±0.05dB (Note 9)
- 22.05 - kHz -6.0dB
Stopband (Note 9) SB 24.1 kHz Passband Ripple PR dB ± 0.02 Stopband Attenuation SA 54 dB Group Delay (Note 10) GD - 19.3 - 1/fs Digital Filter + SCF
dB - - FR Frequency Response 20.0kHz fs=44.1kHz ± 0.2
dB - - FR 40.0kHz fs=96kHz ± 0.3
dB - - FR 80.0kHz fs=192kHz +0.1/-0.6
Notes: 9. The passband and stopband frequencies scale with fs(system sampling rate).
For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
10. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data of both channels to input register to the output of analog signal.
SLOW ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 4.75~5.25V; fs = 44.1kHz; DEM = OFF; SLOW = “1”) Parameter Digital Filter
Passband ±0.04dB (Note 11) -3.0dB
Stopband (Note 11) Passband Ripple
Stopband Attenuation
Group Delay (Note 10) Digital Filter + SCF
Frequency Response 20.0kHz fs=44.kHz FR -
40.0kHz fs=96kHz FR - 80.0kHz fs=192kHz FR -
Note: 11. The passband and stopband frequencies scale with fs.
For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs.
+0/-5 +0/-4 +0.1/-5
- - -
dB dB dB
PB SB PR SA GD
0 - 39.2 72 -
18.2 19.3
8.1 - ± 0.005
-
kHz kHz kHz dB dB 1/fs
Symbol
min
typ
max
Units
DC CHARACTERISTICS
(Ta=25°C; VDD=4.75 ∼ 5.25V) Parameter
High-Level Input Voltage Low-Level Input Voltage
High-Level Output Voltage (Iout=-80µA) Low-Level Output Voltage (Iout=80µA) Input Leakage Current
Symbol VIH VIL VOH VOL Iin
min 2.2 - VDD-0.4
- -
typ - - - -
max - 0.8 - 0.4 ± 10
Units V V V V µA
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ASAHI KASEI
[AK4381]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=4.75 ∼ 5.25V; CL=20pF) Parameter Symbol min Master Clock Frequency fCLK 2.048 Duty Cycle dCLK 40 LRCK Frequency Normal Speed Mode fsn 8 Double Speed Mode fsd 60 Quad Speed Mode fsq 120 Duty Cycle Duty 45
Audio Interface Timing
BICK Period Normal Speed Mode 1/128fs tBCK Double/Quad Speed Mode 1/64fs tBCK
30 tBCKL BICK Pulse Width Low
Pulse Width High 30 tBCKH BICK rising to LRCK Edge (Note 12) 20 tBLR LRCK Edge to BICK rising (Note 12) 20 tLRB SDTI Hold Time 20 tSDH SDTI Setup Time 20 tSDS Control Interface Timing CCLK Period tCCK 200 CCLK Pulse Width Low tCCKL 80 Pulse Width High tCCKH 80 CDTI Setup Time tCDS 40 CDTI Hold Time tCDH 40 CSN “H” Time tCSW 150
tCSS 50 CSN “↓” to CCLK “↑”
tCSH 50 CCLK “↑” to CSN “↑”
Reset Timing PDN Pulse Width (Note 13) tPD 150
Notes: 12. BICK rising edge must not occur at the same time as LRCK edge.
13. The AK4381 can be reset by bringing PDN= “L”.
typ 11.2896
max 36.864 60 48 96 192 55
Units MHz % kHz kHz kHz % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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[AK4381]
n Timing Diagram
1/fCLKVIHVIL
tCLKHtCLKL
1/fsVIHVIL
tBCKVIHVIL
tBCKHtBCKLClock Timing
LRCK
tBLRtLRBVIHVIL
tSDStSDHVIHVIL
Serial Interface Timing
VIHVIL
dCLK=tCLKH x fCLK, tCLKL x fCLKMCLK
LRCK
BICK
BICK
SDTI
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[AK4381]
CSN
CCLK
CDTICSN
CCLK
CDTI
PDN
MS0152-E-00 VIH
VIL
tCSStCCKLtCCKHVIHVIL
tCDStCDHC1C0R/WA4VIHVIL
WRITE Command Input Timing
tCSWVIH
VIL
tCSHVIHVIL
D3D2D1D0
VIHVIL
WRITE Data Input Timing
tPDVIL
Power-down Timing
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[AK4381]
OPERATION OVERVIEW
n System Clock
The external clocks, which are required to operate the AK4381, are MCLK, LRCK and BICK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = “0”: Register 00H), the sampling speed is set by DFS0/1(Table 1). The frequency of MCLK at each sampling speed is set automatically. (Table 2~4).After exiting reset (PDN = “↑”), the AK4381 is in Auto Setting Mode. In Auto Setting Mode (ACKS = “1”: Default), as MCLK frequency is detected automatically (Table 5), and the internal master clock becomes the appropriate frequency (Table 6), it is not necessary to set DFS0/1.
All external clocks (MCLK,BICK and LRCK) should always be present whenever the AK4381 is in the normal operation mode (PDN= ”H”). If these clocks are not provided, the AK4381 may draw excess current and may fall into unpredictable operation. This is because the device utilizes dynamic refreshed logic internally. The AK4381 should be reset by PDN= “L” after threse clocks are provided. If the external clocks are not present, the AK4381 should be in the power-down mode (PDN= “L”). After exiting reset at power-up etc., the AK4381 is in the power-down mode until MCLK and LRCK are input.
DFS1 0 0 1
DFS0 0 1 0
Sampling Rate (fs)
Normal Speed Mode Double Speed Mode Quad Speed Mode
8kHz~48kHz 60kHz~96kHz 120kHz~192kHz
Default
Table 1. Sampling Speed (Manual Setting Mode)
LRCK fs 32.0kHz 44.1kHz 48.0kHz
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK fs 88.2kHz 96.0kHz
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK MCLK BICK fs 128fs 192fs 64fs 176.4kHz 22.5792MHz 33.8688MHz 11.2896MHz 192.0kHz 24.5760MHz 36.8640MHz 12.2880MHz
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
MCLK
128fs 192fs 256fs 384fs 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz
BICK 64fs 5.6448MHz 6.1440MHz
MCLK
256fs 384fs 512fs 768fs 8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz
BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz
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[AK4381]
MCLK 512fs 768fs 256fs 384fs 128fs 192fs
Sampling Speed
Normal Double Quad
Table 5. Sampling Speed (Auto Setting Mode: Default)
LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz
128fs - - - - - 22.5792 24.5760
MCLK (MHz)
192fs 256fs 384fs 512fs 768fs - - - 16.3840 24.5760 - - - 22.5792 33.8688 - - - 24.5760 36.8640 - 22.5792 33.8688 - - - 24.5760 36.8640 - - 33.8688 - - - - 36.8640 - - - -
Table 6. System Clock Example (Auto Setting Mode)
Sampling Speed
Normal Double Quad
n Audio Serial Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0-2 as shown in Table 7 can select five serial data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs.
Mode DIF2 DIF1 DIF0 SDTI Format BICK Figure 0 0 0 0 16bit LSB Justified Figure 1 ≥32fs 1 0 0 1 20bit LSB Justified Figure 2 ≥40fs 2 0 1 0 24bit MSB Justified Figure 3 Default ≥48fs 3 0 1 1 24bit I2S Compatible Figure 4 ≥48fs 4 1 0 0 24bit LSB Justified Figure 2 ≥48fs
Table 7. Audio Data Formats
LRCK
011011121314150110111213141501BICK(32fs)SDTIMode 0BICK(64fs)SDTIMode 0
0151146145154163172131001511461451541631721310150141Don’t care15:MSB, 0:LSB15140Don’t care15140Lch DataMS0152-E-00
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[AK4381]
Figure 1. Mode 0 Timing
LRCKBICK(64fs)SDTIMode 1SDTIMode 4
01891011123101891011123101Don’t care19:MSB, 0:LSBDon’t care23222120190Don’t care190190Don’t care2322212019023:MSB, 0:LSBLch Data
Figure 2. Mode 1,4 Timing
Rch Data
LRCK
0122223243031012222324303101BICK(64fs)SDTI
232223:MSB, 0:LSB10Don’t care232210Don’t care2322Lch Data
Figure 3. Mode 2 Timing
Rch Data
LRCK
01232324253101232324253101BICK(64fs)SDTI
232223:MSB, 0:LSB10Don’t care232210Don’t care23Lch Data Figure 4. Mode 3 Timing
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[AK4381]
n De-emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is enabled or disabled with DEM0 and DEM1. In case of double speed and quad speed mode, the digital de-emphasis filter is always off.
DEM1 0 0 1 1
DEM0 0 1 0 1
Mode 44.1kHz OFF 48kHz 32kHz
Default
Table 8. De-emphasis Filter Control (Normal Speed Mode)
n Output Volume
The AK4381 includes channel independent digital output volumes (ATT) with 256 levels at linear step including MUTE. These volumes are in front of the DAC and can attenuate the input data from 0dB to –48dB and mute. When changing levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The transition time of 1 level and all 256 levels is shown in Table 9.
Sampling Speed Transition Time
1 Level 255 to 0
Normal Speed Mode 4LRCK 1020LRCK Double Speed Mode 8LRCK 2040LRCK Quad Speed Mode 16LRCK 4080LRCK
Table 9. ATT Transition Time
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[AK4381]
n Zero Detection
The AK4381 has channel-independent zeros detect function. When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input data of each channel is not zero after going DZF “H”. If RSTN bit is “0”, DZF pins of both channels go to “H”. DZF pin of both channels go to “L” at 2~3/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, DZF pins of both channels go to “H” only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Zero detect function can be disabled by DZFE bit. In this case, DZF pins of both channels are always “L”. DZFB bit can invert the polarity of DZF pin.
n Soft Mute Operation
Soft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by -∞ during ATT_DATA×ATT transition time (Table 9) from the current ATT level. When the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT transition time. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission.
SMUTE bit
(1)(1)(3)ATT Level
Attenuation
-∞
GD(2)AOUT
(4)8192/fsGDDZF pin
Notes:
(1) ATT_DATA×ATT transition time (Table 9). For example, in Normal Speed Mode, this time is 1020LRCK cycles (1020/fs) at ATT_DATA=255.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”.
Figure 5. Soft Mute and Zero Detection
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[AK4381]
n System Reset
The AK4381 should be reset once by bringing PDN= ”L” upon power-up. The AK4381 is powered up and the internal timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4381 is in the power-down mode until MCLK and LRCK are input.
n Power-down
The AK4381 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z). Figure 6 shows an example of the system timing at the power-down and power-up.
PDNInternal StateD/A In (Digital)
GDNormal OperationPower-downNormal Operation“0” data(1)D/A Out (Analog)
Clock In
MCLK, LRCK, BICK(3)(4)(2)(3)GD(1)Don’t careDZFL/DZFRExternalMUTE
(6)(5)
Mute ON
Notes:
(1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”). (5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
(6) DZF pins are “L” in the power-down mode (PDN = “L”).
Figure 6. Power-down/up Sequence Example
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[AK4381]
n Reset Function
When RSTN=0, DAC is powered down but the internal register values are not initialized. The analog outputs go to VCOM voltage and DZF pin goes to “H”. Figure 7 shows the example of reset by RSTN bit.
RSTN bitInternalRSTN bitInternal StateD/A In (Digital)D/A Out (Analog)
Clock In
MCLK,LRCK,BICK
3~4/fs (6)2~3/fs (6)Normal OperationDigital Block Power-downNormal Operation“0” data(1)GD(3)(2)(4)Don’t care(3)GD(1)2/fs(5)DZF
Notes:
(1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs go to VCOM voltage (VDD/2).
(3) Click noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0” data is
input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = “L”).
(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”.
(6) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the
internal RSTN “1”.
Figure 7. Reset Sequence Example
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[AK4381]
n Mode Control Interface
Internal registers may be written by 3-wire µP interface pins, CSN, CCLK and CDTI. The data on this interface consists of Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”, Write only), Register Address (MSB first, 5bits) and Control Data (MSB first, 8bits). AK4381 latches the data on the rising edge of CCLK, so data should clocked in on the falling edge. The writing of data becomes valid by CSN “↑”. The clock speed of CCLK is 5MHz (max).
PDN = “L” resets the registers to their default values. The internal timing circuit is reset by RSTN bit, but the registers are not initialized.
CSN
0
1
2
3
4
5
6
7
8
9
10
1112
13
14
15
CCLK
Chip Address (Fixed to “01”)
READ/WRITE (Fixed to “1”, Write only) Register Address Control Data
Figure 8. Control I/F Timing
*AK4381 does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4381 is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control register is inhibited.
C1-C0: R/W: A4-A0: D7-D0:
CDTI
C1C0R/WA4A3A2A1A0D7D6D5D4D3D2D1D0n Register Map Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
02H 04H
Control 3 Rch ATT
0 ATT7
0 ATT6
0 ATT5
0 ATT4
0 ATT3
DZFB ATT2
0 ATT1
0 ATT0
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[AK4381]
n Register Definitions Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
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[AK4381]
DZFM: Data Zero Detect Mode
0: Channel Separated Mode 1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection 1: DZF goes “L” at Zero Detection Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
default 1 1 1 1 1 1 1 1
Analog Supply 5V
Figure 9. Typical Connection Diagram
Notes:
- LRCK = fs, BICK = 64fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive load.
- All input pins except pull-down/pull-up pins should not be left floating.
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[AK4381]
1. Grounding and Power Supply Decoupling
VDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling capacitor, especially 0.1µF ceramic capacitor for high frequency should be placed as near to VDD as possible. The differential Voltage between VDD and VSS pins set the analog output range.
2. Analog Outputs
The analog outputs are full-differential outputs and 0.55 x VDD Vpp (typ) centered around the internal common voltage (about AVDD/2). The differential outputs are summed externally, VAOUT=(AOUT+)-(AOUT-) between AOUT+ and AOUT-. If the summing gain is 1, the output range is 5.5Vpp (typ @VREFH=5V). The bias voltage of the external
summing circuit is supplied externally. The input data format is 2’s complement. The output voltage (VAOUT) is a positive full scale for 7FFFFF (@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for 000000H (@24bit).
The internal switched-capacitor filter and external low pass filter attenuate the noise generated by the delta-sigma
modulator beyond the audio passband. DC offset on AOUT+/- is eliminated without AC coupling since the analog outputs are differential. Figure 10 and 11 show the example of external op-amp circuit summing the differential outputs.
AOUT-4.7kR14.7k470pVop3300p4.7kR1AOUT+Vop1kAnalogOut
4.7k470pBIAS
47u
0.1uWhen R1=200Ωfc=93.2kHz, Q=0.712, g=-0.1dB at 40kHzWhen R1=180Ωfc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz1k
Figure 10. External 2nd order LPF Circuit Example (using op-amp with single power supply)
AOUT-
4.7kR14.7k470p+Vop3300p4.7kR1AOUT+
AnalogOut
-Vop4.7k470pWhen R1=200Ω
fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHzWhen R1=180Ω
fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
Figure 11. External 2nd order LPF Circuit Example (using op-amp with dual power supplies)
MS0152-E-00 - 19 -
2002/5
元器件交易网www.cecb2b.com
ASAHI KASEI
[AK4381]
PACKAGE
16pin TSSOP (Unit: mm)
*5.0±0.11.05±0.05
1691A
.0±2.40.4±*4.618 0.13 M0.22±0.10.650.17±0.05
Detail A0.1±0.12.0±5Seating Plane.0 0.10NOTE: Dimension \"*\" does not include mold flash.
0-10°
n Package & Lead frame material
Package molding compound: Epoxy Lead frame material: Cu
Lead frame surface treatment: Solder(Pb free) plate
MS0152-E-00 - 20 -
2002/5
元器件交易网www.cecb2b.com
ASAHI KASEI
[AK4381]
MARKING
AKM 4381VT XXYYY
1) Pin #1 indication
2) Date Code : XXYYY (5 digits)
XX: Lot#
YYY: Date Code
3) Marketing Code : 4381VT 4) Asahi Kasei Logo
IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0152-E-00 - 21 -
2002/5
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