Delay circuit having stable delay time

专利名称：Delay circuit having stable delay time发明人：Kobatake, Hiroyuki, c/o NEC Corporation申请号：EP90111686.3申请日：19900620公开号：EP0405319B1公开日：19951129

摘要：A delay circuit comprises a first inverter including a first MOSFET of a P-channeltype (P₁) having a gate connected to an input terminal (IN), a drain connected to a firstnode (1) and a source connected to a high voltage supply line (VCC); and a secondMOSFET (N₃) of an N-channel type having a gate connected to the input terminal, a drainconnected through a first resistor (R₁) to the first node and a source connected toground. There is provided a current mirror circuit having an input side current path (i₁)connected in parallel to the first MOSFET, and an output side current path (i₂) connectedbetween the first voltage supply line and a second node (2). A capacitor (C) is connectedbetween the second node and the ground, and there is provided a third MOSFET (N₅) ofthe N-channel type having a gate connected to receive an inverted signal of a signalapplied on the input terminal, a drain connected to the second node and a sourceconnected to the second voltage supply line (ground). A second inverter includes afourth MOSFET (P₆) of the P-channel type having a gate connected to the second node, adrain connected to an output terminal (OUT) and a source connected to the high voltagesupply line, and a fifth MOSFET (N₇) of the N-channel type having a gate connected to theinput terminal, a drain connected through a second resistor (R₂) to the output terminaland a source connected to the ground.

申请人：NEC CORP

地址：JP

国籍：JP

代理机构：Betten & Resch

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