专利名称：Efficient conditional instruction having
companion load predicate bits instruction
发明人：Gavin J. Stark申请号：US14311225申请日：20140620公开号：US09519482B2公开日：20161213
专利附图：
摘要：A pipelined run-to-completion processor can decode three instructions in threeconsecutive clock cycles, and can also execute the instructions in three consecutive clockcycles. The first instruction causes the ALU to generate a value which is then loaded due
to execution of the first instruction into a register of a register file. The second
instruction accesses the register and loads the value into predicate bits in a register fileread stage. The predicate bits are loaded in the very next clock cycle following the clockcycle in which the second instruction was decoded. The third instruction is a conditionalinstruction that uses the values of the predicate bits as a predicate code to determine apredicate function. If a predicate condition (as determined by the predicate function asapplied to flags) is true then an instruction operation of the third instruction is carriedout, otherwise it is not carried out.
申请人：Netronome Systems, Inc.
地址：Santa Clara CA US
国籍：US
代理机构：Imperium Patent Works LLP
代理人：T. Lester Wallace,Mark D. Marrello
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