Efficient arrangement of interconnection resources

专利名称：Efficient arrangement of interconnection

resources on programmable logic devices

发明人：Christopher F. Lane,Giles V. Powell,Wayne

Yeung,Chiakang Sung,Bruce B. Pedersen

申请号：US09908308申请日：20010717公开号：US06507216B1公开日：20030114

专利附图：

摘要：Interconnection block arrangements for selectively interconnecting logic on aprogrammable logic device is provided. Programmable logic connectors within the

interconnection blocks may be programmed to route signals between the variousconductors on the device and to route signals from various logic regions on the device tothe various conductors. The interconnection blocks are arranged to optimize the use ofmetallization resources and to increase interconnectivity and logic density.

申请人：ALTERA CORPORATION

代理机构：Fish & Neave

代理人：Michael E. Shanahan,Jeffrey C. Aldridge

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