集成电路实习报告
院系：电控学院电子科学与技术系 专业名称：电子科学与技术 班级：24050601 学号：2405060136 学生姓名：钱德亮 指导教师：邱彦章 肖剑
一、 实习目的
通过集成电路实习，掌握数字集成电路的设计流程和前端设计方法；熟悉Synopsys公司的电路仿真工具VCS和逻辑综合工具DC，完成密勒解码器的设计。
二、实习时间
2009年11月 30日～2009年12月11日
三、实习地点
国家集成电路设计西安产业化基地
四、实习内容 密勒解码器设计
一、题目：
设计一个密勒解码器电路 二、输入信号：
1． DIN：输入数据
2． CLK：频率为2MHz的方波，占空比为50％ 3． RESET：复位信号，低有效 三、输入信号说明：
输入数据为串行改进密勒码，每个码元持续时间为8μs，即16个CLK时钟；数据流是由A、B、C三种信号组成；
A：前8个时钟保持“1”，接着5个时钟变为“0”，最后3个时钟为“1”。 B：在整个码元持续时间内都没有出现“0”，即连续16个时钟保持“1”。 C：前5个时钟保持“0”，后面11个时钟保持“1”。 改进密勒码编码规则如下： 如果码元为逻辑“1”，用A信号表示。 如果码元为逻辑“0”，用B信号表示，但以下两种特例除外：如果出现两个以上连“0”，则从第二个“0”起用C信号表示；如果在“通信起始位”之后第一位就是“0”，则用C信号表示，以下类推；
“通信起始位”，用C信号表示； “通信结束位”，用“0”及紧随其后的B信号表示。 “无数据”，用连续的B信号表示。 输入数据信号示例如下：（S代表“通信起始位”，E代表“通信结束位”）
注意：当DIN为“1”时，CLK信号为连续的2MHz方波；当DIN为“0”时，CLK信号为“0”。输入数据信号总是在CLK信号的下降沿变化。 为便于理解，特将A信号图示如下： DIN：
CLK： 四、输出信号：
1． DOUT：输出数据
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2． DATA＿EN：输出数据使能信号 3． BIT＿EN：码元使能信号 五、输出信号规定：
DATA＿EN：
DOUT： 0 1 0 0 1 0 1
BIT＿EN：
DATA＿EN信号从“0”变为“1”到变回“0”，表示收到一帧完整的数据，DOUT和BIT＿EN只有在DATA＿EN为“1”时才是有效的；BIT＿EN信号为“1”时，DOUT的值即为当前码元。上图表示解码结果为0100101。
注意，“通信起始位”和“通信结束位”在输出信号中必须消去。 六、设计要求
● 设计一个密勒解码电路，输入信号为如下4帧数据：10010110、00010100、10100101、00100111（与前面输入数据信号示例相同），正确完成解码，并使输出信号符合规定。 ● 可不考虑错码。
● 请首先提供书面设计方案
1．总体设计框图
密勒解码器设计Signal_ACLKDINRESETBIT_EN_tempDOUTSignal_B检测模块Signal_C解码模块DATA_ENBIT_EN 图1－1：总体设计框图 2．总体设计思路说明
整个系统分为两个模块：检测模块和解码模块。检测模块主要完成从输入串行序列判断出A，B或C信号，并分别输出脉冲标志脉冲串Signal_A，Signal_B和Signal_C；同时，当检测到任一信号时，BIT_EN_temp输出一个高脉冲。解码模块根据检测模块输出的三个标志脉冲进行0/1解码，输出最终的密勒解码数据DOUT；同时，输出DATA_EN和BIT_EN两个标志信号。
3． 各个模块设计及时序关系说明
3．1 检测模块
由于时钟不完整，我们只能计算高电平个数，假设count为输入数据低电平之间高电平的个数；分析发现，根据前一个信号状态与count的值可以判定下一
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个信号状态，如下表所示：
表一：计数值与对应信号状态 当前信Count值 号 11 C 19 >19 (27 / 35 / >35) A 11 >11 (19/27/>27) 19 （从A转入） B 27 （从A转入） >27 下一个信号 C A B (BC/ BA/ BB) 结束 A B (BC/BA/BB) C A B 结束 其中AC两信号相连不存在，CB或BB代表一帧数据结束。 因此检测模块处理流程包含三个部分：计数部分，信号状态转移部分和检测输出部分。
计数部分：系统复位后处于B状态，设定一个5位寄存器count_temp，每个CLK上升沿进行计数，记满后保持原值不变（此时必定处于无效状态）；当DIN＝0时，一次计数完成，将count_temp的值赋给count保存，同时count_temp清零，准备下一次计数；count值送入“信号状态转移部分”，与当前信号一起判断下一个信号状态。这里要注意，当下一状态为B时，状态改变了但计数值没有清零(DIN＝0时count才清零)，如对于A状态，如果count>12（则下个状态是B），则将count_temp的值先保存，以得到B状态。然后再在B状态中根据count_temp最终的值，判断下一个状态。
信号状态转移部分：如图2－1所示(参考表一)
count=11Acount>11count=27count=31,起始Bcount>27count>19RESETcount=19Ccount=11count=19
图2－1：信号状态转移图
检测输出部分：若状态为A或C时，且在下一CLK上升沿，count_temp变为1，说明count_temp先被清零了，已经检测到一次A或C，因此Signal_A或Signal_B输出一次高脉冲；若状态为B，且count_temp>12或count_temp>20表
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示count_temp还未清零，检测到一次B，信号Signal_B输出一次高脉冲。 3．2 解码模块
与检测模块思想一致，根据本次状态和上次状态来判断是开始位，有效数据位或停止位。因此，我们可以设计一个三状态的有限状态机分别代表开始状态start，数据状态data或停止状态idle。A，B，C三个信号两两组合共有9组信号，其中AC信号不存在，BB，CB信号表示停止（参看表一）；在idle状态下如果检测到BC则表示数据传输开始，进入start状态，即start状态前一个状态为C，若当前状态为B，则进入idle状态，若当前状态为A或C则进入data状态。在data状态中有 AB，AA，BA，BC，CA，CC六种有效状态，若状态变为BB或CB则表示数据传输结束，进入idle状态。整个状态转移图如图3－1所示。
在有效状态下，DATA_EN置高，输出DOUT根据miller编码思想和输入状态来决定，如输入A则DOUT＝1，输入B/C，DOUT＝0。BIT_EN可由BIT_EN_temp与DATA_EN相与得到。
BBidleRESETCB/BBdataCA/CCCBBCstartAA/AB BA/BC CC/CA图3－1：有效数据状态转移图
4． 附件
4．1 文件清单及目录结构
本文档清单如下： “源代码”文件夹：
miller_decode.v 顶层模块
miller_decode_tb.v 顶层模块测试程序 Signal_detect.v 检测模块
Signal_detect_tb2.v 检测模块测试程序 decode.v 解码模块
decode_tb.v 解码模块测试程序 “结果波形文件夹”：
miller_decode_1.bmp 密勒解码器总体输入输出波形图
miller_decode_2.bmp 密勒解码器总体输入输出波形局部放大图
Signal_detect_1.bmp 密勒解码器检测模块输入输出波形图 Signal_detect_2.bmp 密勒解码器检测模块输入输出波形局部放大图
decode.bmp 密勒解码器解码部分波形图
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4．2 源代码及说明
“源代码”文件夹包含了设计的全部源程序，共记六个程序。其中 miller_decode.v 是设计的顶层文件，它调用了其他两个模块：Signal_detect.v 和 decode.v 。Signal_detect.v 主要完成信号A，B，C的检测，decode.v主要完成解码，输出0/1码。 4．3 测试说明
miller_decode_tb.v，Signal_detect_tb2.v以及decode_tb.v分别为miller_decode.v，Signal_detect.v 和 decode.v三个程序块的测试文件。
(1) 检测模块 （ Signal_detect_tb2.v） 在检测模块中，我们输入四帧信号：
frame1：1001_0110， 密勒编码为：C,A,B,C,A,B,A,A,B,C,B frame2：0001_0100， 密勒编码为：C,C,C,C,A,B,A,B,C,C,B frame3：1010_0101， 密勒编码为：C,A,B,A,B,C,A,B,A,B,B frame4：0010_0111， 密勒编码为：C,C,C,A,B,C,A,A,A,B,B
其中第一个C为起始位，最后C，B或B，B为停止位，中间八位为有效数据位
我们将这四帧信号每帧后面加入两个B，作为“无数据”状态，存入一个寄存器frame_total中，然后每来一个2MHz(完整时钟)时钟的下降沿就输出一个bit位，作为该模块的输入信号。 如下式所示：
always @(negedge clock) begin
din<=frame_total[847]; // 847=4*16*11+16*9-1 frame_total<=(frame_total<<1); end
不完整的时钟信号clk可以通过一个完整的2MHz时钟与din相与得到，如下式所示：
always @ (clock) //din orclock begin
clk = din & clock; end
例化检测模块Signal_detect.v即可观测输出数据是否表征了输入的A，B，C信号。该部分仿真结果如图4.4－1所示。
(2) 解码模块 (decode_tb.v)
在解码模块中，我们参考第一帧信号：
frame1：1001_0110， 密勒编码为：C,A,B,C,A,B,A,A,B,C,B 根据它的编码，人为的置sig_a，sig_b或sig_c一个个脉冲，例化解码模块 decode.v即可观测输出数据是否就是实际的 0/1码，从而判断程序的正确性。该模块仿真结果如图4.4－2所示。
(3) 顶层模块 (miller_decode_tb.v)
顶层模块例化检测模块和解码模块，该部分仿真结果如图4.4－3所示。
详细的设计流程请直接参考源程序。
4．4 波形及说明
(1) 检测模块
如图4.4－1所示为检测模块的仿真波形图，图中输入数据为：\"1001_0110\" （C ABCA_BAAB_CB），输出信号sig_a，sig_b，sig_c的顺序正好显示着
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C ABCA_BAAB_CB，由此可以判断检测模块按设计预想完成了从输入序列中正确检测A，B，C信号的功能。
图4.4－1：检测模块仿真波形图
（2）解码模块
如图4.4－2为解码模块仿真波形图，图中输入数据为根据第一帧编码后的A，B，C信号的顺序(C ABCA_BAAB_CB)。输出信号dout显示为“10010110”，这正是输入信号的密勒解码，由此可以判断出解码模块按设计预想从输入A，B，C顺序中解出了0/1码，正确完成了预想功能。
图4.4－2：解码模块仿真波形图
(3)顶层模块
顶层模块的输入与检测模块相同，输出要与解码模块一致。如图4.4－3所示
为顶层模块仿真波形图，从中可以看出，当输入序列为“C ABCA_BAAB_CB”
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时，输出信号为：\"1001_0110\"。由此说明了本文总体设计满足了题目设计密勒解码器的要求，正确实现了从密勒编码序列中解码的功能。
五．英文资料
图4.4－2：顶层模块仿真波形图
An application-specific integrated circuit (ASIC) is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC. Intermediate between ASICs and industry standard integrated circuits, like the 7400 or the 4000 series, are application specific standard products (ASSPs). As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 gates to over 100 million. Modern ASICs often include entire 32-bit processors, memory blocks including ROM, RAM, EEPROM, Flash and other large building blocks. Such an ASIC is often termed a SoC (system-on-a-chip). Designers of digital ASICs use a hardware description language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs. Field-programmable gate arrays (FPGA) are the modern-day technology for building a breadboard or prototype from standard parts; programmable logic blocks and programmable interconnects allow the same FPGA to be used in many different applications. For smaller designs and/or lower production volumes, FPGAs may be more cost effective than an ASIC design even in production. The non-recurring engineering cost of an ASIC can run into the millions of dollars. History
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The initial ASICs used gate array technology. Ferranti produced perhaps the first gate-array, the ULA (Uncommitted Logic Array), around 1980. An early successful commercial application was the ULA circuitry found in the 8-bit ZX81 and ZX Spectrum low-end personal computers, introduced in 1981 and 1982. These were used by Sinclair Research (UK) essentially as a low-cost I/O solution aimed at handling the computer's graphics. Some versions of ZX81/Timex Sinclair 1000 used just four chips (ULA, 2Kx8 RAM, 8Kx8 ROM, Z80A CPU) to implement an entire mass-market personal computer with built-in BASIC interpreter.
Customization occurred by varying the metal interconnect mask. ULAs had complexities of up to a few thousand gates. Later versions became more generalized, with different base dies customised by both metal and polysilicon layers. Some base dies include RAM elements.
Standard cell design
Main article: standard cell In the mid 1980s a designer would choose an ASIC manufacturer and implement their design using the design tools available from the manufacturer. While third party design tools were available, there was not an effective link from the third party design tools to the layout and actual semiconductor process performance characteristics of the various ASIC manufacturers. Most designers ended up using factory specific tools to complete the implementation of their designs. A solution to this problem that also yielded a much higher density device was the implementation of Standard Cells. Every ASIC manufacturer could create functional blocks with known electrical characteristics, such as propagation delay, capacitance and inductance, that could also be represented in third party tools. Standard Cell design is the utilization of these functional blocks to achieve very high gate density and good electrical performance. Standard cell design fits between Gate Array and Full Custom design in terms of both its NRE (Non-Recurring Engineering) and recurring component cost.
By the late 1990s, logic synthesis tools became available. Such tools could compile HDL descriptions into a gate-level netlist. This enabled a style of design called standard-cell design. Standard-cell Integrated Circuits (ICs) are designed in the following conceptual stages, although these stages overlap significantly in practice.
These steps, implemented with a level of skill common in the industry, almost always produce a final device that correctly implements the original design, unless flaws are later introduced by the physical fabrication process.
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1. A team of design engineers starts with a non-formal understanding
of the required functions for a new ASIC, usually derived from Requirements analysis.
2. The design team constructs a description of an ASIC to achieve these
goals using an HDL. This process is analogous to writing a computer program in a high-level language. This is usually called the RTL (Register transfer level) design.
3. Suitability for purpose is verified by functional verification.
This may include such techniques as logic simulation, formal verification, emulation, or creating an equivalent pure software model (see Simics, for example). Each technique has advantages and disadvantages, and often several methods are used.
4. Logic synthesis transforms the RTL design into a large collection
of lower-level constructs called standard cells. These constructs are taken from a standard-cell library consisting of pre-characterized collections of gates (such as 2 input nor, 2 input nand, inverters, etc.). The standard cells are typically specific to the planned manufacturer of the ASIC. The resulting collection of standard cells, plus the needed electrical connections between them, is called a gate-level netlist.
5. The gate-level net list is next processed by a placement tool which
places the standard cells onto a region representing the final ASIC. It attempts to find a placement of the standard cells, subject to a variety of specified constraints.
6. The routing tool takes the physical placement of the standard cells
and uses the netlist to create the electrical connections between them. Since the search space is large, this process will produce a “sufficient” rather than “globally-optimal” solution. The output is a file which can be used to create a set of photomasks enabling a semiconductor fabrication facility (commonly called a 'fab') to produce physical ICs.
7. Given the final layout, circuit extraction computes the parasitic
resistances and capacitances. In the case of a digital circuit, this will then be further mapped into delay information, from which the circuit performance can be estimated, usually by static timing analysis. This, and other final tests such as design rule checking and power analysis (collectively called signoff) are intended to ensure that the device will function correctly over all extremes of the process, voltage and temperature. When this testing is complete the photomask information is released for chip fabrication. These design steps (or flow) are also common to standard product design. The significant difference is that Standard Cell design uses the
manufacturer's cell libraries that have been used in potentially hundreds of other design implementations and therefore are of much lower risk than full custom design. Standard Cells produce a design density that is cost
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effective, and they can also integrate IP cores and SRAM (Static Random Access Memory) effectively, unlike Gate Arrays.
Gate array design
Gate array design is a manufacturing method in which the diffused layers, i.e. transistors and other active devices, are predefined and wafers containing such devices are held in stock prior to metallization, in other words, unconnected. The physical design process then defines the
interconnections of the final device. For most ASIC manufacturers, this consists of from two to as many as five metal layers, each metal layer running parallel to the one below it. Non-recurring engineering costs are much lower as photo-lithographic masks are required only for the metal layers, and production cycles are much shorter as metallization is a comparatively quick process.
Gate array ASICs are always a compromise as mapping a given design onto what a manufacturer held as a stock wafer never gives 100% utilization. Often difficulties in routing the interconnect require migration onto a larger array device with consequent increase in the piece part price. These difficulties are often a result of the layout software used to develop the interconnect.
Pure, logic-only gate array design is rarely implemented by circuit designers today, replaced almost entirely by field-programmable devices, such as field-programmable gate arrays (FPGAs), which can be programmed by the user and thus offer minimal tooling charges (non-recurring
engineering (NRE)), marginally increased piece part cost and comparable performance. Today gate arrays are evolving into structured ASICs that consist of a large IP core like a CPU, DSP unit, peripherals, standard interfaces, integrated memories SRAM, and a block of reconfigurable uncommitted logic. This shift is largely because ASIC devices are capable of integrating such large blocks of system functionality and \"system on a chip\" requires far more than just logic blocks.
In their frequent usages in the field, the terms \"gate array\" and
\"semi-custom\" are synonymous. Process engineers more commonly use the term \"semi-custom\" while \"gate-array\" is more commonly used by logic (or gate-level) designers.
Full-custom design
Main article: Full custom 10
By contrast, full-custom ASIC design defines all the photo lithographic layers of the device. Full-custom design is used for both ASIC design and for standard product design.
The benefits of full-custom design usually include reduced area (and therefore recurring component cost), performance improvements, and also the ability to integrate analog components and other pre-designed (and thus fully verified) components such as microprocessor cores that form a system-on-chip.
The disadvantages of full-custom design can include increased
manufacturing and design time, increased non-recurring engineering costs, more complexity in the computer-aided design (CAD) system and a much higher skill requirement on the part of the design team.
However for digital-only designs, \"standard-cell\" cell libraries
together with modern CAD systems can offer considerable performance/cost benefits with low risk. Automated layout tools are quick and easy to use and also offer the possibility to \"hand-tweak\" or manually optimise any performance-limiting aspect of the design.
Structured/platform design
Structured ASIC design (also referred to as platform ASIC design) has different meanings in different contexts. This is a relatively new term in the industry, which is why there is some variation in its definition. However, the basic premise of a structured/platform ASIC is that both manufacturing cycle time and design cycle time are reduced compared to cell-based ASIC by virtue of there being pre-defined metal layers (thus reducing manufacturing time) and pre-characterization of what is on the silicon (thus reducing design cycle time). One definition states that
In a \"structured ASIC\" design, the logic mask-layers of a device are predefined by the ASIC vendor (or in some cases by a third party). Design differentiation and customization is achieved by creating custom metal layers that create custom connections between predefined lower-layer logic elements. \"Structured ASIC\"
technology is seen as bridging the gap between field-programmable gate arrays and \"standard-cell\" ASIC designs. Because only a small number of chip layers must be custom-produced, \"structured ASIC\" designs have much smaller non-recurring expenditures (NRE) than \"standard-cell\" or \"full-custom\" chips, which require that a full mask set be produced for every design.
This is effectively the same definition as a gate array.
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What makes a structured/platform ASIC different from a gate array is that in a gate array the predefined metal layers serve to make manufacturing turnaround faster. In a structured/platform ASIC the predefined
metallization is primarily to reduce cost of the mask sets and is also used to make the design cycle time significantly shorter as well. For example, in a cell-based or gate-array design the user often must design power, clock, and test structures themselves; these are predefined in most Structured/Platform ASICs and therefore can save time and expense for the designer compared to gate-array. Likewise, the design tools used for structured/Platform ASIC can be substantially lower cost and easier (faster) to use than cell-based tools, because the tools do not have to perform all the functions that cell-based tools do. In some cases, the structured/platform ASIC vendor requires that customized tools for their device (for example, custom physical synthesis) be used, also allowing for the design to be brought into manufacturing more quickly. ChipX, Inc. eAsic, and Triad Semiconductor are examples of vendors offering this kind of structured ASIC.
One other important aspect about structured/platform ASIC is that it allows IP that is common to certain applications or industry segments to be \"built in\rather than \"designed in\". By building the IP directly into the architecture the designer can again save both time and money compared to designing IP into a cell-based ASIC.
The Altera technique of producing a structured cell ASIC where the cells are the same design as the FPGA, but the programmable routing is replaced with fixed wire interconnect is called HardCopy. These devices then do not need re-programming and cannot be re-programmed as an FPGA.
The Xilinx technique of producing a customer specific FPGA, that is 30% - 70% less expensive than a standard FPGA and where the cells are the same as the FPGA but the programmable capability is removed, is called EasyPath.
Cell libraries, IP-based design, hard and soft macros
Cell libraries of logical primitives are usually provided by the device manufacturer as part of the service. Although they will incur no additional cost, their release will be covered by the terms of a
non-disclosure agreement (NDA) and they will be regarded as intellectual property by the manufacturer. Usually their physical design will be pre-defined so they could be termed \"hard macros\".
What most engineers understand as \"intellectual property\" are IP cores, designs purchased from a third party as sub-components of a larger ASIC. They may be provided as an HDL description (often termed a \"soft macro\"),
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or as a fully routed design that could be printed directly onto an ASIC's mask (often termed a hard macro). Many organizations now sell such pre-designed IP, and larger organizations may have an entire department or division to produce such IP for the rest of the organization. For example, one can purchase CPUs, ethernet, USB or telephone interfaces. Indeed, the wide range of functions now available is a significant factor in the phenomenal increase in electronics in the late 1990s and early 2000s; as intellectual property takes a lot of time and investment to create, its re-use and further development cuts product cycle times dramatically and creates better products.
Soft macros are often process-independent, i.e., they can be fabricated on a wide range of manufacturing processes and different manufacturers. Hard macros are process-limited and usually further design effort must be invested to migrate (port) to a different process or manufacturer.
Multi-project wafers
Some manufacturers offer Multi-Project Wafers (MPW) as a method of obtaining low cost prototypes. Often called shuttles, these MPW,
containing several designs, run at regular, scheduled intervals on a \"cut and go\" basis, usually with very little liability on the part of the manufacturer. The contract involves the assembly and packaging of a handful of devices. The service usually involves the supply of a physical design data base i.e. masking information or Pattern Generation (PG) tape. The manufacturer is often referred to as a \"silicon foundry\" due to the low involvement it has in the process.
ASIC suppliers
There are two different types of ASIC suppliers, IDM and fabless. An IDM supplier's ASIC product is based in large part on proprietary technology such as design tools, IP, packaging, and usually although not necessarily the process technology. Fabless ASIC suppliers rely almost exclusively on outside suppliers for their technology. The classification can be confusing since several IDM's are also fabless semiconductor companies.
IDM ASIC suppliers
Avago Technologies Elmos Semiconductor Cavium Networks Fujitsu Freescale 13 HITACHI IBM Infineon Technologies LSI Corporation NEC NXP Semiconductors ON Semiconductor Renesas Samsung STMicroelectronics Texas Instruments Toshiba Fabless ASIC suppliers
Alchip ChipX eASIC eSilicon Faraday Technology Global UniChip KeyASIC MOSIS Netlogic Microsystems Open-Silicon Socle System to ASIC Triad Semiconductor Verisilicon QualComm References
1. Richard Ball (26 October 2004). \"The promise of structured Asic\". Electronics Weekly. http://www.electronicsweekly.com/Articles/2004/10/26/33416/The+promise+of+structured+Asic.htm. 2. \"Avago Technologies > Products > ASIC\". http://www.avagotech.com/pages/en/asics/. Further reading
Paul Naish (1988). \"Designing ASICs\". http://web.ukonline.co.uk/paul.naish/DA/contents.htm. — An 14
Introduction to ASIC design with an emphasis on synchronous clocking techniques. Written within the context of a training department. Perhaps rather dated now, as it deals only with primitive logic. Analogue engineers who need to include some digital logic into their designs would find this particularly useful. Kevin Morris (23 November 2003). \"Cost-Reduction Quagmire: Structured ASIC and Other Options\". FPGA and Programmable Logic Journal. http://www.fpgajournal.com/articles/20041123_quagmire.htm. Jim Turley (7 April 2005). \"Hard Choices Among FPGA Hardening Options\". TechOnline. http://www.techonline.com/article/192200241. Anthony Cataldo (26 March 2002). \"Xilinx looks to ease path to custom FPGAs\". EE Times (CMP Media, LLC). http://www.eetimes.com/story/OEG20020325S0060. \"Xilinx intros next-gen EasyPath FPGAs priced below structured ASICs\". EDP Weekly's IT Monitor (Millin Publishing, Inc.). 18 October 2004. http://findarticles.com/p/articles/mi_m0GZQ/is_41_45/ai_n8968679. Golshan, K. (2007). Physical design essentials: an ASIC design implementation perspective. New York: Springer. ISBN 0-387-36642-3.
六、实习总结
通过这几天的实习，我得到了很大的收获，这些都是平时在课堂理论学习中无法学到的，我主要的收获有以下几点：
1．掌握了几种基本的集成电路设计软件工具的使用，器件的连接方法，编程语言程序的规范；
2．了解了一般简单仿真和综合程序的使用方法，掌握了一般密勒解码器的原理及在UNIX操作环境下的操作技巧和编写代码的注意事项； 3．熟悉了整个集成电路制造，IC产业流程；
4．本次实习大大增强了我们的团队合作精神，培养了我们的动手实践能力和细心严谨的作风。
这段时间，我学到了很多东西，不仅有学习方面的，更学到了很多做人的道理，对我来说受益非浅。做为一个刚踏入社会的年轻人来说，什么都不懂，没有任何社会经验。不过，在领导和指导老师的帮助下，我很快融入了这个新的环境，这对我今后踏入新的工作岗位是非常有益的。除此以外，我还学会了如何更好地与别人沟通，如何更好地去陈述自己的观点，如何说服别人认同自己的观点。相信这些宝贵的经验会成为我今后成功的最重要的基石。实习是每一个大学毕业生必须拥有的一段经历，它使我们在实践中了解社会，让我们学到了很多在课堂上根本就学不到的知识，也打开了视野，增长了见识，为我们以后更好地服务社会打下了坚实的基础。
最后衷心感谢为我们这次实习一直辛勤努力的邱彦章老师和肖剑老师。
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