专利名称:Method and resulting structure for
fabricating DRAM cell structure using oxideline spacer
发明人:Mieno Fumitake,Bong Jae Lee,Guoqing Chen申请号:US10773799申请日:20040206公开号:US06967161B2公开日:20051122
专利附图:
摘要:A method for forming bit line and storage node contacts for a dynamic randomaccess device, e.g., DRAM. Other devices (e.g., Flash, EEPROM) may also be included. The
method includes providing a substrate, which has a bit line region and a capacitor contactregion. The method also includes forming at least a first gate structure and a secondgate structure overlying the substrate. The first gate structure and the second gatestructure include an overlying cap. The method also includes forming a conformaldielectric layer overlying the first gate structure, the second gate structure, the bit lineregion, and the capacitor contact region. The method includes forming an interlayerdielectric material overlying the conformal dielectric layer and planarizing the interlayerdielectric material. The method includes forming a masking layer overlying the planarizedinterlayer dielectric material and exposing a continuous common region within a portionof the planarized interlayer dielectric material overlying a portion of the first gatestructure, a portion of the second gate structure, a portion of the bit line region, and aportion of the capacitor contact region. A first etching process is performed to removethe exposed portion of the planarized interlayer dielectric layer. A second etchingprocess is performed to remove a portion of the conformal dielectric layer on the bit lineregion and to remove a portion of the conformal dielectric layer on the capacitor contactregion while using other portions of the conformal layer as a mask to prevent a portionof the first gate structure and a portion of the second gate structure from beingexposed. The method deposits a polysilicon fill material within the continuous commonregion and overlying the bit line region, the capacitor contact region, the first gatestructure, and the second gate structure to cover portions of the bit line region, thecapacitor contact region, the first gate structure, and the second gate structure to apredetermined thickness. The method includes planarizing the polysilicon fill material toreduce the predetermined thickness and to simultaneously reduce a thickness of aportion of the interlayer dielectric material.
申请人:Mieno Fumitake,Bong Jae Lee,Guoqing Chen
地址:Shanghai CN,Shanghai CN,Shanghai CN
国籍:CN,CN,CN
代理机构:Townsend and Townsend and Crew, LLP
更多信息请下载全文后查看
因篇幅问题不能全部显示,请点此查看更多更全内容