IC testing apparatus and method

专利名称：IC testing apparatus and method发明人：Yuji Wada,Kaoru Fukuda,Yoshio

Kamiko,Masaaki Mochiduki

申请号：US09/115793申请日：19980715公开号：US06138257A公开日：20001024

摘要：Main tester unit tests an IC device for presence of a defect for each of aplurality of addresses of the IC device under predetermined test conditions and storestest results for the individual addresses into a first memory. Curing analysis processingsection cures each of the addresses of the IC device determined as defective, on the basisof the test results for the individual addresses stored in the first memory. To this end,the curing analysis processing section may rearrange an address logic of the IC device toreplace a physical space of the defective addresses with an extra or redundant addressspace and thereby place each of the defective addresses in a usable condition. In parallelwith the operations by the curing analysis processing section, a defect analysis sectionacquires, from the main tester unit, the test results for the individual addresses alongwith data indicative of the predetermined test conditions for storage into a secondmemory, and analyzes a specific cause of the defect in the IC device on the basis of thestored data in the second memory. With this arrangement, it is possible to acquireinformation necessary for analyzing the defect in the IC during a curability determininganalysis test on a mass production line and thereby can effectively analyze the specificcause of the detected defect.

申请人：HITACHI ELECTRONICS ENGINEERING CO., LTD.

代理机构：Morrison & Foerster

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