PCA9674资料

2022-04-05 来源：步旅网

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PCA9674/74A

Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt

Rev. 02 — 12 October 2006

Product data sheet

1.General description

The PCA9674/74A provide general purpose remote I/O expansion for most

microcontroller families via the two-line bidirectional bus (I2C-bus) and is a part of theFast-mode Plus (Fm+) family.

ThePCA9674/74Aisadrop-inupgradeforthePCF8574/74AprovidinghigherFast-modePlus I2C-bus speeds (1MHz versus 400kHz) so that the output can support PWM

dimming of LEDs, higher I2C-bus drive (30mA versus 3mA) so that many more devicescan be on the bus without the need for bus buffers, higher total package sink capacity(200mA versus 100mA) that supports having all LEDs on at the same time and moredevice addresses (64 versus 8) are available to allow many more devices on the buswithout address conﬂicts.

The devices consist of an 8-bit quasi-bidirectional port and an I2C-bus interface. The

PCA9674/74Ahavelowcurrentconsumptionandincludelatchedoutputswith25mAhighcurrent drive capability for directly driving LEDs.

They also possess an interrupt line (INT) that can be connected to the interrupt logic ofthe microcontroller. By sending an interrupt signal on this line, the remote I/O can informthemicrocontrollerifthereisincomingdataonitsportswithouthavingtocommunicateviathe I2C-bus.

The internal Power-On Reset (POR) or Software Reset sequence initializes the I/Os asinputs.

2.Features

IIIIIIIIIIIII

1MHz I2C-bus interface

Compliant with the I2C-bus Fast and Standard modesSDA with 30mA sink capability for 4000pF buses2.3V to 5.5V operation with 5.5V tolerant I/Os

8-bit remote I/O pins that default to inputs at power-up

Latched outputs with 25mA sink capability for directly driving LEDsTotal package sink capability of 200mAActive LOW open-drain interrupt output

64 programmable slave addresses using 3 address pins

Readable device ID (manufacturer, device type, and revision)Low standby current

−40°C to +85°C operation

ESD protection exceeds 2000V HBM per JESD22-A114, 200V MM perJESD22-A115, and 1000V CDM per JESD22-C101

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NXP Semiconductors

PCA9674/74A

Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt

ILatch-up testing is done to JEDEC standard JESD78 which exceeds 100mAIPackages offered: DIP16, SO16, SSOP20, TSSOP16, HVQFN16

3.Applications

IIIIIIII

LED signs and displaysServers

Industrial controlMedical equipmentPLCs

Cellular telephonesGaming machines

Instrumentation and test measurement

4.Ordering information

Table 1.

Ordering information

Topsidemark9674674APCA9674DPCA9674ADPCA9674NPCA9674ANPCA9674PA9674APCA9674PCA9674A

SSOP20TSSOP16

plastic thin shrink small outline package; 16 leads;bodywidth4.4mm

plastic shrink small outline package; 20 leads;bodywidth4.4mm

SOT403-1SOT266-1

DIP16

plastic dual in-line package; 16 leads (300mil); long body

SOT38-1

SO16PackageNameHVQFN16DescriptionVersionplasticthermalenhancedverythinquadﬂatpackage;noleads;SOT758-116 terminals; body 3×3×0.85mm

plastic small outline package; 16 leads; body width 7.5mm

SOT162-1

Type numberPCA9674BSPCA9674ABSPCA9674DPCA9674ADPCA9674NPCA9674ANPCA9674PWPCA9674APWPCA9674TSPCA9674ATS

Product data sheetRev. 02 — 12 October 20062 of 34

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NXP Semiconductors

PCA9674/74A

Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt

5.Block diagram

PCA9674PCA9674AINTAD0AD1AD2SCLSDAINPUTFILTERINTERRUPTLOGICLP FILTERI2C-BUSCONTROLSHIFTREGISTER8 BITSI/OPORTP0 to P7VDDVSSPOWER-ONRESETwrite pulseread pulse002aac108Fig 1.Block diagram of PCA9674/74Awrite pulseItrt(pu)data from Shift RegisterDFFCISpower-on resetDFFread pulsedata to Shift RegisterCISQQ100 µAIOHVDDIOLP0 to P7VSSto interrupt logic002aac109Fig 2.Simpliﬁed schematic diagram of P0 to P7 PCA9674_PCA9674A_2© NXP B.V. 2006. All rights reserved.

Product data sheetRev. 02 — 12 October 20063 of 34

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NXP Semiconductors

PCA9674/74A

Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt

6.Pinning information

6.1Pinning

AD0AD1AD2P0P1P2P3VSS12345678002aac11116VDD15SDA14SCLAD0AD1AD2P0P1P2P3VSS12345678002aac11316VDD15SDA14SCLPCA9674DPCA9674AD13INT12P711P610P59P4PCA9674PWPCA9674APW13INT12P711P610P59P4Fig 3.Pin conﬁguration for SO16PCA9674NPCA9674ANAD0AD1AD2P0P1P2P3VSS12345678002aac110Fig 4.Pin conﬁguration for TSSOP1616VDD15SDA14SCL13INT12P711P610P59P4INTSCLn.c.SDAVDDAD0AD1n.c.AD212345678920P719P618n.c.17P5PCA9674TSPCA9674ATS16P415VSS14P313n.c.12P211P1P010002aac112Fig 5.Pin conﬁguration for DIP16Fig 6.Pin conﬁguration for SSOP20PCA9674BSPCA9674ABSterminal 1index areaAD2P0P1P21234567813SDA12SCL11INT10P79P6P516AD115AD0VSSP3P414VDD002aac114Transparent top viewFig 7.Pin conﬁguration for HVQFN16 PCA9674_PCA9674A_2

Product data sheetRev. 02 — 12 October 20064 of 34

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PCA9674/74A

Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt

6.2Pin description

Table 2.SymbolAD0AD1AD2P0P1P2P3VSSP4P5P6P7INTSCLSDAVDDTable 3.SymbolINTSCLn.c.SDAVDDAD0AD1n.c.AD2P0P1P2n.c.P3VSSP4P5n.c.P6P7

Pin description for DIP16, SO16, TSSOP16

Pin12345678910111213141516

Descriptionaddress input 0address input 1address input 2quasi-bidirectional I/O0quasi-bidirectional I/O1quasi-bidirectional I/O2quasi-bidirectional I/O3supply ground

quasi-bidirectional I/O4quasi-bidirectional I/O5quasi-bidirectional I/O6quasi-bidirectional I/O7interrupt output (activeLOW)serial clock lineserial data linesupply voltage

Pin description for SSOP20

Pin1234567891011121314151617181920

Descriptioninterrupt output (activeLOW)serial clock linenot connectedserial data linesupply voltageaddress input 0address input 1not connectedaddress input 2quasi-bidirectional I/O0quasi-bidirectional I/O1quasi-bidirectional I/O2not connected

quasi-bidirectional I/O3supply ground

quasi-bidirectional I/O4quasi-bidirectional I/O5not connected

quasi-bidirectional I/O6quasi-bidirectional I/O7

Product data sheetRev. 02 — 12 October 20065 of 34

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PCA9674/74A

Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt

Pin description for HVQFN16

Pin12345678910111213141516

Descriptionaddress input 2quasi-bidirectional I/O0quasi-bidirectional I/O1quasi-bidirectional I/O2quasi-bidirectional I/O3supply ground

quasi-bidirectional I/O4quasi-bidirectional I/O5quasi-bidirectional I/O6quasi-bidirectional I/O7interrupt output (activeLOW)serial clock lineserial data linesupply voltageaddress input 0address input 1

Table 4.SymbolAD2P0P1P2P3VSS[1]P4P5P6P7INTSCLSDAVDDAD0AD1

[1]

HVQFNpackagediesupplygroundisconnectedtoboththeVSSpinandtheexposedcenterpad.TheVSSpinmustbeconnectedtosupplygroundforproperdeviceoperation.Forenhancedthermal,electrical,andboard-level performance, the exposed pad needs to be soldered to the board using a correspondingthermal pad on the board, and for proper heat conduction through the board thermal vias need to beincorporated in the PCB in the thermal pad region.

7.Functional description

Refer toFigure 1 “Block diagram of PCA9674/74A”.

7.1Device address

Following a START condition, the bus master must send the address of the slave it isaccessing and the operation it wants to perform (read or write). The address of the

PCA9674/74A is shown inFigure8. Slave address pins AD2, AD1, and AD0 choose 1 of64slave addresses. To conserve power, no internal pull-up resistors are incorporated onAD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found inTable 5 “PCA9674 address map” andTable 6 “PCA9674A address map”.

Remark:When using the PCA9674A, the General Call address (00000000b) and theDeviceID address (1111100Xb) are reserved and cannot be used as device address.Failure to follow this requirement will cause the PCA9674A not to acknowledge.

Remark:WhenusingthePCA9674orthePCA9674A,reservedI2C-busaddressesmustbe used with caution since they can interfere with:

•“reserved for future use” I2C-bus addresses (0000011, 1111101, 1111110,

1111111)

•slave devices that use the 10-bit addressing scheme (11110xx)•High speed mode (Hs-mode) master code (00001xx)

PCA9674_PCA9674A_2

Product data sheetRev. 02 — 12 October 20066 of 34

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PCA9674/74A

Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt

slave addressA6A5A4A3A2A1A0R/Wprogrammable002aab636Fig 8.PCA9674/74A addressThe last bit of the ﬁrst byte deﬁnes the operation to be performed. When set to logic1 aread is selected, while a logic0 selects a write operation.

When AD2, AD1 and AD0 are held to VDD or VSS, the same address as the PCF8574 orPCF8574A is applied.

7.1.1Address maps

Table 5.AD2VSSVSSVSSVSSVDDVDDVDDVDDVSSVSSVSSVSSVDDVDDVDDVDDVSSVSSVSSVSSVDDVDDVDDVDD

PCA9674 address mapAD1SCLSCLSDASDASCLSCLSDASDASCLSCLSDASDASCLSCLSDASDAVSSVSSVDDVDDVSSVSSVDDVDD

AD0VSSVDDVSSVDDVSSVDDVSSVDDSCLSDASCLSDASCLSDASCLSDAVSSVDDVSSVDDVSSVDDVSSVDD

A6000000000000000000000000

A5000000000000000011111111

A4111111111111111100000000

A3000000001111111100000000

A2000011110000111100001111

A1001100110011001100110011

A0010101010101010101010101

Address20h22h24h26h28h2Ah2Ch2Eh30h32h34h36h38h3Ah3Ch3Eh40h42h44h46h48h4Ah4Ch4Eh

Product data sheetRev. 02 — 12 October 20067 of 34

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PCA9674/74A

Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt

PCA9674 address map …continuedAD1VSSVSSVDDVDDVSSVSSVDDVDDSCLSCLSDASDASCLSCLSDASDASCLSCLSDASDASCLSCLSDASDAVSSVSSVDDVDDVSSVSSVDDVDDVSSVSSVDDVDDVSSVSSVDDVDD

AD0SCLSDASCLSDASCLSDASCLSDAVSSVDDVSSVDDVSSVDDVSSVDDSCLSDASCLSDASCLSDASCLSDAVSSVDDVSSVDDVSSVDDVSSVDDSCLSDASCLSDASCLSDASCLSDA

A60000000011111111111111111111111111111111

A51111111100000000000000001111111111111111

A40000000011111111111111110000000011111111

A31111111100000000111111110000000000000000

A20000111100001111000011110000111100001111

A10011001100110011001100110011001100110011

A00101010101010101010101010101010101010101

Address50h52h54h56h58h5Ah5Ch5EhA0hA2hA4hA6hA8hAAhAChAEhB0hB2hB4hB6hB8hBAhBChBEhC0hC2hC4hC6hC8hCAhCChCEhE0hE2hE4hE6hE8hEAhEChEEh

Table 5.AD2VSSVSSVSSVSSVDDVDDVDDVDDSCLSCLSCLSCLSDASDASDASDASCLSCLSCLSCLSDASDASDASDASCLSCLSCLSCLSDASDASDASDASCLSCLSCLSCLSDASDASDASDA

Product data sheetRev. 02 — 12 October 20068 of 34

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NXP Semiconductors

PCA9674/74A

Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt

PCA9674A address mapAD1SCLSCLSDASDASCLSCLSDASDASCLSCLSDASDASCLSCLSDASDAVSSVSSVDDVDDVSSVSSVDDVDDVSSVSSVDDVDDVSSVSSVDDVDDSCLSCLSDASDASCLSCLSDASDA

AD0VSSVDDVSSVDDVSSVDDVSSVDDSCLSDASCLSDASCLSDASCLSDAVSSVDDVSSVDDVSSVDDVSSVDDSCLSDASCLSDASCLSDASCLSDAVSSVDDVSSVDDVSSVDDVSSVDD

A60000000000000000000000001111111111111111

A50000000011111111111111110000000000000000

A40000000011111111111111110000000000000000

A31111111100000000111111110000000011111111

A20000111100001111000011110000111100001111

A10011001100110011001100110011001100110011

A00101010101010101010101010101010101010101

Address10h12h14h16h18h1Ah1Ch1Eh60h62h64h66h68h6Ah6Ch6Eh70h72h74h76h78h7Ah7Ch7Eh80h82h84h86h88h8Ah8Ch8Eh90h92h94h96h98h9Ah9Ch9Eh

Table 6.AD2VSSVSSVSSVSSVDDVDDVDDVDDVSSVSSVSSVSSVDDVDDVDDVDDVSSVSSVSSVSSVDDVDDVDDVDDVSSVSSVSSVSSVDDVDDVDDVDDSCLSCLSCLSCLSDASDASDASDA

Product data sheetRev. 02 — 12 October 20069 of 34

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PCA9674/74A

Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt

PCA9674A address map …continuedAD1SCLSCLSDASDASCLSCLSDASDAVSSVSSVDDVDDVSSVSSVDDVDDVSSVSSVDDVDDVSSVSSVDDVDD

AD0SCLSDASCLSDASCLSDASCLSDAVSSVDDVSSVDDVSSVDDVSSVDDSCLSDASCLSDASCLSDASCLSDA

A6111111111111111100000000

A5111111111111111100000000

A4111111111111111100000000

A3000000001111111100000000

A2000011110000111100001111

A1001100110011001100110011

A0010101010101010101010101

AddressD0hD2hD4hD6hD8hDAhDChDEhF0hF2hF4hF6h-[1]FAhFChFEh-[1]02h04h06h08h0Ah0Ch0Eh

Table 6.AD2SCLSCLSCLSCLSDASDASDASDASCLSCLSCLSCLSDASDASDASDASCLSCLSCLSCLSDASDASDASDA

[1]

The PCA9674A does not acknowledge when AD2, AD1, AD0 follows this conﬁguration.

7.2Software Reset Call, and device ID addresses

Two other different addresses can be sent to the PCA9674/74A.

•General Call address: allows to reset the PCA9674/74A through the I2C-bus upon

receptionoftherightI2C-bussequence.SeeSection7.2.1“SoftwareReset”formoreinformation.

•Device ID address: allows to read ID information from the device (manufacturer, part

identiﬁcation, revision). SeeSection 7.2.2 “Device ID (PCA9674/74A ID ﬁeld)” formore information.

Product data sheetRev. 02 — 12 October 200610 of 34

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PCA9674/74A

Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt

1111100R/W002aac116Fig 10.Device ID address7.2.1Software Reset

The Software Reset Call allows all the devices in the I2C-bus to be reset to the power-upstate value through a speciﬁc formatted I2C-bus command. To be performed correctly, itimplies that the I2C-bus is functional and that there is no device hanging the bus.The Software Reset sequence is deﬁned as following:1.A START command is sent by the I2C-bus master.

2.ThereservedGeneralCallI2C-busaddress‘0000000’withtheR/Wbitsetto0(write)is sent by the I2C-bus master.3.The PCA9674/74A device(s) acknowledge(s) after seeing the General Call address‘00000000’(00h)only.IftheR/Wbitissetto1(read),noacknowledgeisreturnedtothe I2C-bus master.4.Once the General Call address has been sent and acknowledged, the master sends1byte. The value of the byte must be equal to 06h.a.ThePCA9674/74Aacknowledgesthisvalueonly.Ifthebyteisnotequalto06h,thePCA9674/74A does not acknowledge it.If more than 1byte of data is sent, the PCA9674/74A does not acknowledge anymore.

5.Once the right byte has been sent and correctly acknowledged, the master sends aSTOPcommandtoendtheSoftwareResetsequence:thePCA9674/74Athenresetsto the default value (power-up value) and is ready to be addressed again within thespeciﬁed bus free time. If the master sends a Repeated START instead, no reset isperformed.The I2C-bus master must interpret a non-acknowledge from the PCA9674/74A (at anytime) as a ‘Software Reset Abort’. The PCA9674/74A does not initiate a reset of itsregisters.

The unique sequence that initiates a Software Reset is described inFigure11.

SWRST Call I2C-bus addressS00000000R/Wacknowledgefrom slave(s)A0SWRST data = 06h0000110APSTART conditionacknowledgefrom slave(s)PCA9674/74A is(are) reset.Registers are set to default power-up values.002aac262Fig 11.Software Reset sequence PCA9674_PCA9674A_2© NXP B.V. 2006. All rights reserved.

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PCA9674/74A

Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt

7.2.2Device ID (PCA9674/74A ID ﬁeld)

The Device ID ﬁeld is a 3-byte read-only (24bits) word giving the following information:

•8bits with the manufacturer name, unique per manufacturer (for example, NXP).•13bits with the part identiﬁcation, assigned by manufacturer, the 7MSBs with the

category ID and the 6 LSBs with the feature ID (for example, for examplePCA9674/74A 16-bit quasi-output I/O expander).

•3bits with the die revision, assigned by manufacturer (for example, Rev X).

The Device ID is read-only, hardwired in the device and can be accessed as follows:1.START command

2.The master sends the Reserved Device ID I2C-bus address ‘1111100’ with the R/Wbit set to 0 (write).3.The master sends the I2C-bus slave address of the slave device it needs to identify.TheLSBisa‘Don’tcare’value.Onlyonedevicemustacknowledgethisbyte(theonethat has the I2C-bus slave address).4.The master sends a Re-START command.

Remark:ASTOPcommandfollowedbyaSTARTcommandwillresettheslavestatemachine and the Device ID read cannot be performed.

Remark:A STOP command or a Re-START command followed by an access to

anotherslavedevicewillresettheslavestatemachineandtheDeviceIDreadcannotbe performed.

5.The master sends the Reserved Device ID I2C-bus address ‘1111100’ with the R/Wbit set to 1 (read).6.The device ID read can be done, starting with the 8 manufacturer bits (ﬁrst byte+4MSB of the second byte), followed by the 13 part identiﬁcation bits and then the3die revision bits (3LSB of the third byte).7.The master ends the reading sequence by NACKing the last byte, thus resetting theslave device state machine and allowing the master to send the STOP command.Remark:The reading of the Device ID can be stopped anytime by sending a NACKcommand.

Remark:If the master continues to ACK the bytes after the third byte, the

PCA9674/74A rolls back to the ﬁrst byte and keeps sending the Device ID sequenceuntil a NACK has been detected.

For the PCA9674/74A, the Device ID is as shown inFigure12.

manufacturer00000000part identification0000001001011category identificationfeature identificationrevision000002aac118Fig 12.PCA9674/74A ID PCA9674_PCA9674A_2

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PCA9674/74A

Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt

acknowledge from oneor several slave(s)device ID addressS11111000R/Wdon't careAA6A5A4A3A2A1A0XI2C-bus slave address ofthe device to be identifiedacknowledgefrom masteracknowledge fromslave to be identifiedacknowledge fromslave to be identified1001R/WAA1111START conditiondevice ID addressacknowledgefrom masterno acknowledgefrom masterPM7M6M5M4M3M2M1M0AC6C5C4C3C2C1C0F5AF4P3P2P1P0R2R1R0Acategory identification= 0000001revision = 000feature identification= 001011manufacturer name= 00000000STOPcondition002aac119If more than 2 bytes are read, the slave device loops back to the ﬁrst byte (manufacturer byte)and keeps sending data until the master generates a ‘no acknowledge’.Fig 13.Device ID ﬁeld reading8.I/O programming

8.1Quasi-bidirectional I/O architecture

The PCA9674/74A’s 8ports (seeFigure2) are entirely independent and can be usedeither as input or output ports. Input data is transferred from the ports to the

microcontroller in the Read mode (seeFigure15). Output data is transmitted to the portsin the Write mode (seeFigure14).

This quasi-bidirectional I/O can be used as an input or output without the use of a controlsignal for data directions. At power-on the I/Os are HIGH. In this mode only a currentsource (IOH) to VDD is active. An additional strong pull-up to VDD (Itrt(pu)) allows fast risingedgesintoheavilyloadedoutputs.ThesedevicesturnonwhenanoutputiswrittenHIGH,andareswitchedoffbythenegativeedgeofSCL.TheI/OsshouldbeHIGHbeforebeingused as inputs. After power-on, as all the I/Os are set HIGH, all of them can be used asinputs. Any change in setting of the I/Os as either inputs or outputs can be done with thewrite mode.

Remark:If a HIGH is applied to an I/O which has been written earlier to LOW, a largecurrent (IOL) will ﬂow to VSS.

8.2Writing to the port (Output mode)

To write, the master (microcontroller) ﬁrst addresses the slave device. By setting the lastbit of the byte containing the slave address to logic0 the write mode is entered. ThePCA9674/74A acknowledges and the master sends the data byte for P7 to P0 and isacknowledged by the PCA9674/74A. The 8-bit data is presented on the port lines after ithas been acknowledged by the PCA9674/74A.

The number of data bytes that can be sent successively is not limited. The previous datais overwritten every time a data byte has been sent.

PCA9674_PCA9674A_2

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PCA9674/74A

Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt

SCL123456789data 1data 2slave addressSDASA6A5A4A3A2A1A00START conditionR/WAP7P61P4P3P2P1P0AP70P5P4P3P2P1P0AP5acknowledgefrom slaveP5acknowledgefrom slavetv(Q)acknowledgefrom slavewrite to porttv(Q)DATA 1 VALIDDATA 2 VALIDdata output from portP5 output voltageP5 pull-up output currentINTItrt(pu)IOHtd(rst)002aac120Fig 14.Write mode (output)8.3Reading from a port (Input mode)

All ports programmed as input should be set to logic1. To read, the master

(microcontroller) ﬁrst addresses the slave device after it receives the interrupt. By settingthe last bit of the byte containing the slave address to logic1 the Read mode is entered.The data bytes that follow on the SDA are the values on the ports.

If the data on the input port changes faster than the master can read, this data may belost.

slave addressSDASA6A5A4A3A2A1A01START conditionread fromportR/WAdata from portDATA 1Adata from portDATA 4no acknowledgefrom master1PSTOPconditionacknowledgefrom slaveacknowledgefrom masterDATA 2data intoportth(D)INTtv(Q)td(rst)td(rst)002aac121DATA 3tsu(D)DATA 4ALOW-to-HIGHtransitionofSDAwhileSCLisHIGHisdeﬁnedastheSTOPcondition(P).TransferofdatacanbestoppedatanymomentbyaSTOPcondition.Whenthisoccurs,datapresentatthelastacknowledgephaseisvalid(Outputmode).Input data is lost.Fig 15.Read input port register PCA9674_PCA9674A_2© NXP B.V. 2006. All rights reserved.

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PCA9674/74A

Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt

8.4Power-on reset

When power is applied to VDD, an internal Power-On Reset (POR) holds the

PCA9674/74A in a reset condition until VDD has reached VPOR. At that point, the resetcondition is released and the PCA9674/74A registers and I2C-bus/SMBus state machinewill initialize to their default states. Thereafter VDD must be lowered below 0.2V to resetthe device.

8.5Interrupt output (INT)The PCA9674/74A provides an open-drain interrupt (INT) which can be fed to acorrespondinginputofthemicrocontroller(seeFigure14,Figure15,andFigure16).Thisgives these chips a kind of master function which can initiate an action elsewhere in thesystem.

Aninterruptisgeneratedbyanyrisingorfallingedgeoftheportinputs.Aftertimetv(D)thesignalINT is valid.Theinterruptdisappearswhendataontheportischangedtotheoriginalsettingordataisread from or written to the device which has generated the interrupt.

Inthewritemode,theinterruptmaybecomedeactivated(HIGH)ontherisingedgeofthewrite to port pulse. On the falling edge of the write to port pulse the interrupt is deﬁnitelydeactivated (HIGH).

The interrupt is reset in the read mode on the rising edge of the read from port pulse.During the resetting of the interrupt itself, any changes on the I/Os may not generate aninterrupt.AftertheinterruptisresetanychangeinI/OswillbedetectedandtransmittedasanINT.VDDdevice 1device 2device 8PCA9674MICROCOMPUTERINTINTPCA9674INTPCA9674INT002aac122Fig 16.Application of multiple PCA9674s with interrupt PCA9674_PCA9674A_2© NXP B.V. 2006. All rights reserved.

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PCA9674/74A

Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt

9.Characteristics of the I2C-bus

TheI2C-busisfor2-way,2-linecommunicationbetweendifferentICsormodules.Thetwolines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stagesof a device. Data transfer may be initiated only when the bus is not busy.

9.1Bit transfer

Onedatabitistransferredduringeachclockpulse.ThedataontheSDAlinemustremainstable during the HIGH period of the clock pulse as changes in the data line at this timewill be interpreted as control signals (seeFigure17).

SDASCLdata linestable;data validchangeof dataallowedmba607Fig 17.Bit transfer9.1.1START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transitionofthedatalinewhiletheclockisHIGHisdeﬁnedastheSTARTcondition(S).ALOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOPcondition (P) (seeFigure18.)

SDASDASCLSSTART conditionPSTOP conditionSCLmba608Fig 18.Deﬁnition of START and STOP conditions9.2System conﬁguration

A device generating a message is a ‘transmitter'; a device receiving is the ‘receiver'. Thedevice that controls the message is the ‘master' and the devices which are controlled bythe master are the ‘slaves' (seeFigure19).

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Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt

SDASCLMASTERTRANSMITTER/RECEIVERSLAVERECEIVERSLAVETRANSMITTER/RECEIVERMASTERTRANSMITTERMASTERTRANSMITTER/RECEIVERI2C-BUSMULTIPLEXERSLAVE002aaa966Fig 19.System conﬁguration9.3Acknowledge

The number of data bytes transferred between the START and the STOP conditions fromtransmitter to receiver is not limited. Each byte of eightbits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,whereas the master generates an extra acknowledge related clock pulse.

Aslavereceiverwhichisaddressedmustgenerateanacknowledgeafterthereceptionofeach byte. Also a master must generate an acknowledge after the reception of each bytethat has been clocked out of the slave transmitter. The device that acknowledges has topulldowntheSDAlineduringtheacknowledgeclockpulse,sothattheSDAlineisstableLOW during the HIGH period of the acknowledge related clock pulse; set-up and holdtimes must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating anacknowledge on the last byte that has been clocked out of the slave. In this event, thetransmitter must leave the data line HIGH to enable the master to generate a STOPcondition.

data outputby transmitternot acknowledgedata outputby receiveracknowledgeSCL from masterSSTARTcondition128clock pulse foracknowledgement9002aaa987Fig 20.Acknowledgement on the I2C-bus PCA9674_PCA9674A_2© NXP B.V. 2006. All rights reserved.

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10.Application design-in information

10.1Bidirectional I/O expander applications

Inthe8-bitI/OexpanderapplicationshowninFigure21,P0andP1areinputs,andP2toP7 are outputs. When used in this conﬁguration, during a write, the input (P0 and P1)must be written as HIGH so the external devices fully control the input ports. The desiredHIGHorLOWlogiclevelsmaybewrittentotheI/Osusedasoutputs(P2toP7).Duringaread, the logic levels of the external devices driving the input ports (P0 and P1) and theprevious written logic level to the output ports (P2 to P7) will be read.

The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic ofthemicroprocessor.Bysendinganinterruptsignalonthisline,theremoteI/Oinformsthemicroprocessorthatthereisincomingdataorachangeofdataonitsportswithouthavingto communicate via the I2C-bus.

VDDVDDVDDCOREPROCESSORSDASCLINTAD0AD1AD2P0P1P2P3P4P5P6P7temperature sensorbattery statuscontrol for latchcontrol for switchcontrol for audiocontrol for cameracontrol for MP3002aac123Fig 21.Bidirectional I/O expander application10.2High current-drive load applications

The GPIO has a maximum sinking current of 25mA per bit. In applications requiringadditional drive, two port pins in the same octal may be connected together to sink up to50mA current. Both bits must then always be turned on or off together. Up to 8 pins (oneoctal) can be connected together to drive 200mA.

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11.Limiting values

Table 7.Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).SymbolVDDIDDISSVIIIIOPtotP/outTstgTamb

[1]

Parametersupply voltagesupply currentground supply currentinput voltageinput currentoutput currenttotal power dissipationpower dissipation per outputstorage temperatureambient temperature

ConditionsMin−0.5--VSS−0.5-[1]

Max+6±100±4005.5±20±50400100+150+85

UnitVmAmAVmAmAmWmW°C°C

---−65

operating−40

Total package (maximum) output current is 400mA.

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12.Static characteristics

Table 8.Static characteristics

VDD=2.3V to 5.5V; VSS=0V; Tamb=−40°Cto+85°C; unless otherwise speciﬁed.SymbolSuppliesVDDIDD

supply voltagesupply current

Operating mode; no load;

VI=VDD or VSS; fSCL=1MHz;AD0, AD1, AD2=static H or LStandby mode; no load;

VI=VDD or VSS; fSCL=0kHz

[1]

ParameterConditionsMin2.3-

Typ-200

Max5.5500

UnitVµA

IstbVPORVILVIHIOL

standby currentpower-on reset voltageLOW-level input voltageHIGH-level input voltageLOW-level output current

--−0.50.7VDD

4.51.8--354457-5263340-−138−1.02.12.1-3---3.5

102.0+0.3VDD5.5---+110---200−300-1010-5+0.3VDD5.5+15

µAVVVmAmAmAµApFmAmAmAmAµAmApFpFmApFVVµApF

Input SCL; input/output SDA

VOL=0.4V; VDD=2.3VVOL=0.4V; VDD=3.0VVOL=0.4V; VDD=4.5V

202530−1-[2][2][2][2]

ILCiIOL

leakage currentinput capacitanceLOW-level output current

VI=VDDorVSSVI=VSS

VOL=0.5V; VDD=2.3VVOL=0.5V; VDD=3.0VVOL=0.5V; VDD=4.5V

I/Os; P0 to P7

121725-−30−0.5[3][3]

IOL(tot)IOHItrt(pu)CiCoIOLCoVILVIHILICi

[1][2][3]

total LOW-level output currentHIGH-level output currentinput capacitanceoutput capacitanceLOW-level output currentoutput capacitanceLOW-level input voltageHIGH-level input voltageinput leakage currentinput capacitance

VOL=0.5V; VDD=4.5VVOH=VSS

transientboostedpull-upcurrentVOH=VSS; seeFigure14--3.0-−0.50.7VDD−1-

InterruptINT (seeFigure15 andFigure14)VOL=0.4VInputs AD0, AD1, AD2

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13.Dynamic characteristics

Table 9.Dynamic characteristics

VDD=2.3V to 5.5V; VSS=0V; Tamb=−40°Cto+85°C; unless otherwise speciﬁed.SymbolParameterConditionsStandardmodeFastmode I2C-busFast-modePlusUnitI2C-busI2C-busMinfSCLtBUFtHD;STAtSU;STAtSU;STOtHD;DATtVD;ACKtVD;DATtSU;DATtLOWtHIGHtftrtSP

SCL clock frequencybus free time between a

STOP and START conditionhold time (repeated) STARTcondition

set-up time for a repeatedSTART conditionset-up time for STOPconditiondata hold time

data valid acknowledgetime[1]

data valid time[2]data set-up time

LOWperiodoftheSCLclockHIGH period of the SCLclock

fall time of both SDA andSCL signals

rise time of both SDA andSCL signals

pulse width of spikes thatmust be suppressed by theinput ﬁlter[6]

data output valid timedata input setup timedata input hold timedata input valid timereset delay time

[4][5]

Max100-----3.45----300100050

Min01.30.60.60.600.1501001.30.620+0.1Cb[3]20+0.1Cb[3]

Max400-----0.9----30030050

Min00.50.260.260.2600.0550500.50.26---

Max1000-----0.45450---12012050

kHzµsµsµsµsnsµsnsnsµsµsnsnsns

04.74.04.74.000.33002504.74.0---

Port timing; CL≤100pF (seeFigure14 andFigure15)tv(Q)tsu(D)th(D)tv(D)td(rst)

[1][2][3][4][5]

-04--

4--44

-04--

4--44

-04--

4--44

µsµsµsµsµs

Interrupt timing; CL≤100pF (seeFigure14 andFigure15)tVD;ACK=time for Acknowledgement signal from SCL LOW to SDA (out) LOW.tVD;DAT=minimum time for SDA data out to be valid following SCL LOW.Cb=total capacitance of one bus line in pF.

A master device must internally provide a hold time of at least 300ns for the SDA signal (refer to the VIL of the SCL signal) in order tobridge the undeﬁned region SCL’s falling edge.

The maximum tf for the SDA and SCL bus lines is speciﬁed at 300ns. The maximum fall time for the SDA output stage tf is speciﬁed at250ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines withoutexceeding the maximum speciﬁed tf.

Input ﬁlters on the SDA and SCL inputs suppress noise spikes less than 50ns.

[6]

PCA9674_PCA9674A_2

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protocolSTARTcondition(S)tSU;STAbit 7MSB(A7)tLOWtHIGHbit 6(A6)bit 0(R/W)acknowledge(A)STOPcondition(P)1/fSCLSCLtBUFSDAtrtftHD;STAtSU;DATtHD;DATtVD;DATtVD;ACKtSU;STO002aab175Rise and fall times refer to VIL and VIH.Fig 23.I2C-bus timing diagram PCA9674_PCA9674A_2© NXP B.V. 2006. All rights reserved.

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14.Package outline

HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;16 terminals; body 3 x 3 x 0.85 mm

SOT758-1

DBAterminal 1index areaEAA1cdetail Xe11/2 eCb8vMCABwMCy1Cye5L49eEh1/2 ee2112terminal 1index area16Dh013X2.5scale5 mmDIMENSIONS (mm are the original dimensions)UNITmmA(1)max.1A10.050.00b0.300.18c0.2D(1)3.12.9Dh1.751.45E(1)3.12.9Eh1.751.45e0.5e11.5e21.5L0.50.3v0.1w0.05y0.05y10.1Note1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINEVERSION SOT758-1 REFERENCES IEC- - - JEDECMO-220 JEITA- - -EUROPEANPROJECTIONISSUE DATE02-03-2502-10-21Fig 24.Package outline SOT758-1 (HVQFN16)

PCA9674_PCA9674A_2

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SO16: plastic small outline package; 16 leads; body width 7.5 mmSOT162-1

DEAXcyHEvMAZ169QA2pin 1 indexLpL1ebp8wMdetail XA1(A )3θA05scale10 mmDIMENSIONS (inch dimensions are derived from the original mm dimensions)UNITmminchesAmax.2.650.1A10.30.1A22.452.25A30.250.01bp0.490.36c0.320.23D(1)10.510.10.410.40E(1)7.67.40.300.29e1.270.05HE10.6510.00L1.4Lp1.10.4Q1.11.00.0430.039v0.250.01w0.250.01y0.10.004Z(1)θ8oo00.90.40.0350.0160.0120.0960.0040.0890.0190.0130.0140.0090.4190.0430.0550.3940.016Note1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINEVERSION SOT162-1 REFERENCES IEC 075E03 JEDEC MS-013 JEITAEUROPEANPROJECTIONISSUE DATE99-12-2703-02-19Fig 25.Package outline SOT162-1 (SO16)

PCA9674_PCA9674A_2

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DIP16: plastic dual in-line package; 16 leads (300 mil); long bodySOT38-1

Dseating planeMEA2ALA1cZeb1b169wM(e )1MHpin 1 indexE1805scale10 mmDIMENSIONS (inch dimensions are derived from the original mm dimensions)UNITmminchesAmax.4.70.19A 1min.0.510.02A 2max.3.70.15b1.401.140.0550.045b10.530.380.0210.015c0.320.230.0130.009D(1)21.821.40.860.84E(1)6.486.200.260.24e2.540.1e17.620.3L3.93.40.150.13ME8.257.800.320.31MH9.58.30.370.33w0.2540.01Z(1)max.2.20.087Note1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINEVERSIONSOT38-1 REFERENCES IEC050G09 JEDECMO-001 JEITASC-503-16EUROPEANPROJECTIONISSUE DATE99-12-2703-02-13Fig 26.Package outline SOT38-1 (DIP16)

PCA9674_PCA9674A_2

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TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mmSOT403-1

DEAXcyHEvMAZ169QA2pin 1 index(A )3A1θLpLA1ebp8wMdetail X02.5scale5 mmDIMENSIONS (mm are the original dimensions)UNITmmAmax.1.1A10.150.05A20.950.80A30.25bp0.300.19c0.20.1D(1)5.14.9E(2)4.54.3e0.65HE6.66.2L1Lp0.750.50Q0.40.3v0.2w0.13y0.1Z(1)0.400.06θ8o0oNotes1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.OUTLINEVERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITAEUROPEANPROJECTIONISSUE DATE99-12-2703-02-18Fig 27.Package outline SOT403-1 (TSSOP16)

PCA9674_PCA9674A_2

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SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mmSOT266-1

DEAXcyHEvMAZ2011QA2pin 1 indexA1(A )3θLpLA1ebp10wMdetail X02.5scale5 mmDIMENSIONS (mm are the original dimensions)UNITmmAmax.1.5A10.150A21.41.2A30.25bp0.320.20c0.200.13D(1)6.66.4E(1)4.54.3e0.65HE6.66.2L1Lp0.750.45Q0.650.45v0.2w0.13y0.1Z(1)0.480.18θ10o0oNote1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINEVERSION SOT266-1 REFERENCES IEC JEDEC MO-152 JEITAEUROPEANPROJECTIONISSUE DATE99-12-2703-02-19Fig 28.Package outline SOT266-1 (SSOP20)

PCA9674_PCA9674A_2

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15.Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.

However,tobecompletelysafeyoumusttakenormalprecautionsappropriatetohandlingintegrated circuits.

16.Soldering

16.1Introduction

There is no soldering method that is ideal for all surface mount IC packages. Wave

solderingcanstillbeusedforcertainsurfacemountICs,butitisnotsuitableforﬁnepitchSMDs. In these situations reﬂow soldering is recommended.

16.2Through-hole mount packages

16.2.1Soldering by dipping or by solder wave

Typicaldwelltimeoftheleadsinthewaverangesfrom3secondsto4secondsat250°Cor 265°C, depending on solder material applied, SnPb or Pb-free respectively.The total contact time of successive solder waves must not exceed 5seconds.

The device may be mounted up to the seating plane, but the temperature of the plasticbody must not exceed the speciﬁed maximum storage temperature (Tstg(max)). If the

printed-circuit board has been pre-heated, forced cooling may be necessary immediatelyafter soldering to keep the temperature within the permissible limit.

16.2.2Manual soldering

Apply the soldering iron (24V or less) to the lead(s) of the package, either below the

seatingplaneornotmorethan2mmaboveit.Ifthetemperatureofthesolderingironbitisless than 300°C it may remain in contact for up to 10seconds. If the bit temperature isbetween 300°Cand400°C, contact may be up to 5seconds.

16.3Surface mount packages

16.3.1Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-freeversusSnPbsoldering;notethatalead-freereﬂowprocessusuallyleadsto

higher minimum peak temperatures (seeFigure29) than a PbSn process, thusreducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperatureishighenoughforthesoldertomakereliablesolderjoints(asolderpastecharacteristic). In addition, the peak temperature must be low enough that the

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packages and/or boards are not damaged. The peak temperature of the packagedepends on package thickness and volume and is classiﬁed in accordance withTable10 and11

Table 10.

SnPb eutectic process (from J-STD-020C)

Package reﬂow temperature (°C)Volume (mm3)< 350< 2.5≥ 2.5Table 11.

235220

Lead-free process (from J-STD-020C)

Package reﬂow temperature (°C)Volume (mm3)< 350< 1.61.6 to 2.5> 2.5

260260250

350 to 2000260250245

> 2000260245245

≥ 350220220

Package thickness (mm)Package thickness (mm)Moisture sensitivity precautions, as indicated on the packing, must be respected at alltimes.

Studies have shown that small packages reach higher temperatures during reﬂowsoldering, seeFigure29.

temperaturemaximum peak temperature= MSL limit, damage levelminimum peak temperature= minimum soldering temperaturepeak temperaturetime001aac844MSL: Moisture Sensitivity LevelFig 29.Temperature proﬁles for large and small componentsFor further information on temperature proﬁles, refer to Application NoteAN10365“Surface mount reﬂow soldering description”.

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16.3.2Wave soldering

Conventional single wave soldering is not recommended for surface mount devices(SMDs) or printed-circuit boards with a high component density, as solder bridging andnon-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcallydeveloped.

If wave soldering is used the following conditions must be observed for optimal results:

•Use a double-wave soldering method comprising a turbulent wave with high upward

pressure followed by a smooth laminar wave.

•For packages with leads on two sides and a pitch (e):

–larger than or equal to 1.27mm, the footprint longitudinal axis ispreferred to beparallel to the transport direction of the printed-circuit board;–smaller than 1.27mm, the footprint longitudinal axismust be parallel to thetransport direction of the printed-circuit board.The footprint must incorporate solder thieves at the downstream end.

•For packages with leads on four sides, the footprint must be placed at a 45° angle to

the transport direction of the printed-circuit board. The footprint must incorporatesolder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet ofadhesive. The adhesive can be applied by screen printing, pin transfer or syringedispensing. The package can be soldered after the adhesive is cured.

Typicaldwelltimeoftheleadsinthewaverangesfrom3secondsto4secondsat250°Cor 265°C, depending on solder material applied, SnPb or Pb-free respectively.Amildly-activated ﬂux will eliminate the need for removal of corrosive residues in mostapplications.

16.3.3Manual soldering

Fixthecomponentbyﬁrstsolderingtwodiagonally-oppositeendleads.Usealowvoltage(24V or less) soldering iron applied to the ﬂat part of the lead. Contact time must belimited to 10seconds at up to 300°C.

When using a dedicated tool, all other leads can be soldered in one operation within2secondsto5seconds between 270°Cand320°C.

16.4Package related soldering information

Table 12.MountingThrough-hole mountThrough-hole-surfacemount

Suitability of IC packages for wave, reﬂow and dipping soldering methods

Package[1]CPGA, HCPGADBS, DIP, HDIP, RDBS, SDIP, SILPMFP[4]

Soldering methodWavesuitablesuitable[3]not suitable

Reﬂow[2]−−

not suitable

Dipping−suitable−

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Table 12.MountingSuitability of IC packages for wave, reﬂow and dipping soldering methods …continuedPackage[1]Soldering methodWaveReﬂow[2]suitable

Dipping−

Surface mount

not suitableBGA, HTSSON..T[5], LBGA,

LFBGA,SQFP,SSOP..T[5],TFBGA,VFBGA, XSON

DHVQFN, HBCC, HBGA, HLQFP,HSO, HSOP, HSQFP, HSSON,HTQFP, HTSSOP, HVQFN,HVSON, SMSPLCC[7], SO, SOJLQFP, QFP, TQFP

SSOP, TSSOP, VSO, VSSOPCWQCCN..L[10], WQCCN..L[10]

not suitable[6]

suitable−

suitable

not recommended[7][8]not recommended[9]not suitable

suitablesuitablesuitablenot suitable

−−−−

[1][2]

For more detailed information on the BGA packages refer to the(LF)BGA Application Note (AN01026); order a copy from your NXPSemiconductors sales ofﬁce.

All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (withrespect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization ofthe moisture in them (the so called popcorn effect).

For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.Hot bar soldering or manual soldering is suitable for PMFP packages.

These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must on no account be processedthrough more than one soldering cycle or subjected to infrared reﬂow soldering with peak temperature exceeding 217°C±10°Cmeasured in the atmosphere of the reﬂow oven. The package body peak temperature must be kept as low as possible.

These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetratebetween the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on theheatsink surface.

If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. Thepackage footprintmust incorporate solder thieves downstream and at the side corners.

Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8mm; it is deﬁnitely not suitable forpackages with a pitch (e) equal to or smaller than 0.65mm.

WavesolderingissuitableforSSOP,TSSOP,VSOandVSSOPpackageswithapitch(e)equaltoorlargerthan0.65mm;itisdeﬁnitelynot suitable for packages with a pitch (e) equal to or smaller than 0.5mm.

[3][4][5]

[6]

[7][8][9]

[10]Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on ﬂex foil.

However, the image sensor package can be mounted by the client on a ﬂex foil by using a hot bar soldering process. The appropriatesoldering proﬁle can be provided on request.

17.Abbreviations

Table 13.AcronymCDMCMOSESDGPIOHBMLEDICI2C-bus

PCA9674_PCA9674A_2

Abbreviations

DescriptionCharged Device ModelComplementary Metal Oxide SemiconductorElectroStatic DischargeGeneral Purpose Input/OutputHuman Body ModelLight Emitting DiodeIntegrated Circuit

Inter-Integrated Circuit bus

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Table 13.AcronymIDLSBMMMSBPLCPWMRAIDSMBus

Abbreviations …continuedDescriptionIdentiﬁcationLeast Signiﬁcant BitMachine ModelMost Signiﬁcant Bit

Programmable Logic ControllerPulse Width Modulation

Redundant Array of Independent DisksSystem Management Bus

18.Revision history

Table 14.

Revision history

Release date20061012

Data sheet statusProduct data sheet

Change notice-SupersedesPCA9674_PCA9674A_1

Document IDPCA9674_PCA9674A_2Modiﬁcations:

•••••

The format of this data sheet has been redesigned to comply with the new identityguidelines of NXP Semiconductors.

Legal texts have been adapted to the new company name where appropriate.Changed data sheet status to “Product data sheet”

Table 1 “Ordering information”: Topside mark for PCA9674ABS changed from “9674A” to“674A”

Table 8 “Static characteristics”, limits for IDD, supply current changed from “100µA (typ.);200µA (max.)” to “200µA (typ.); 500µA (max.)”

Objective data sheet

PCA9674_PCA9674A_120060905

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NXP Semiconductors

PCA9674/74A

Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt

19.Legal information

19.1Data sheet status

Document status[1][2]Objective [short] data sheetPreliminary [short] data sheetProduct [short] data sheet

[1][2][3]

Product status[3]DevelopmentQualiﬁcationProduction

DeﬁnitionThis document contains data from the objective speciﬁcation for product development.This document contains data from the preliminary speciﬁcation.This document contains the product speciﬁcation.

Please consult the most recently issued document before initiating or completing a design.The term ‘short data sheet’ is explained in section “Deﬁnitions”.

Theproductstatusofdevice(s)describedinthisdocumentmayhavechangedsincethisdocumentwaspublishedandmaydifferincaseofmultipledevices.Thelatestproductstatusinformation is available on the Internet at URLhttp://www.nxp.com.

19.2Deﬁnitions

Draft —The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result inmodiﬁcations or additions. NXP Semiconductors does not give anyrepresentations or warranties as to the accuracy or completeness of

informationincludedhereinandshallhavenoliabilityfortheconsequencesofuse of such information.

Short data sheet —A short data sheet is an extract from a full data sheetwiththesameproducttypenumber(s)andtitle.Ashortdatasheetisintendedforquickreferenceonlyandshouldnotbereliedupontocontaindetailedandfull information. For detailed and full information see the relevant full datasheet, which is available on request via the local NXP Semiconductors salesofﬁce. In case of any inconsistency or conﬂict with the short data sheet, thefull data sheet shall prevail.

result in personal injury, death or severe property or environmental damage.NXP Semiconductors accepts no liability for inclusion and/or use of NXPSemiconductors products in such equipment or applications and thereforesuch inclusion and/or use is at the customer’s own risk.

Applications —Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for thespeciﬁed use without further testing or modiﬁcation.

Limiting values —Stress above one or more limiting values (as deﬁned intheAbsoluteMaximumRatingsSystemofIEC60134)maycausepermanentdamagetothedevice.Limitingvaluesarestressratingsonlyandoperationofthe device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limitingvalues for extended periods may affect device reliability.

Terms and conditions of sale —NXP Semiconductors products are soldsubjecttothegeneraltermsandconditionsofcommercialsale,aspublishedathttp://www.nxp.com/proﬁle/terms, including those pertaining to warranty,intellectual property rights infringement and limitation of liability, unlessexplicitly otherwise agreed to in writing by NXP Semiconductors. In case ofany inconsistency or conﬂict between information in this document and suchterms and conditions, the latter will prevail.

No offer to sell or license —Nothing in this document may be interpretedor construed as an offer to sell products that is open for acceptance or thegrant,conveyanceorimplicationofanylicenseunderanycopyrights,patentsor other industrial or intellectual property rights.

19.3Disclaimers

General —Information in this document is believed to be accurate and

reliable.However,NXPSemiconductorsdoesnotgiveanyrepresentationsorwarranties,expressedorimplied,astotheaccuracyorcompletenessofsuchinformation and shall have no liability for the consequences of use of suchinformation.

Right to make changes —NXPSemiconductorsreservestherighttomakechanges to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and withoutnotice.Thisdocumentsupersedesandreplacesallinformationsuppliedpriorto the publication hereof.

Suitability for use —NXP Semiconductors products are not designed,authorized or warranted to be suitable for use in medical, military, aircraft,space or life support equipment, nor in applications where failure or

malfunctionofaNXPSemiconductorsproductcanreasonablybeexpectedto

19.4Trademarks

Notice:Allreferencedbrands,productnames,servicenamesandtrademarksare the property of their respective owners.I2C-bus —logois a trademark of NXP B.V.

20.Contact information

For additional information, please visit:http://www.nxp.com

For sales ofﬁce addresses, send an email to:salesaddresses@nxp.com

Pleasebeawarethatimportantnoticesconcerningthisdocumentandtheproduct(s)described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 12 October 2006

Document identifier: PCA9674_PCA9674A_2

元器件交易网www.cecb2b.com

NXP Semiconductors

PCA9674/74A

Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt

21.Contents

1General description. . . . . . . . . . . . . . . . . . . . . . 12Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Ordering information. . . . . . . . . . . . . . . . . . . . . 25Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 36Pinning information. . . . . . . . . . . . . . . . . . . . . . 46.1Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46.2Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 57Functional description . . . . . . . . . . . . . . . . . . . 67.1Device address. . . . . . . . . . . . . . . . . . . . . . . . . 67.1.1Address maps. . . . . . . . . . . . . . . . . . . . . . . . . . 77.2Software Reset Call, and device ID addresses 107.2.1Software Reset. . . . . . . . . . . . . . . . . . . . . . . . 117.2.2Device ID (PCA9674/74A ID ﬁeld) . . . . . . . . . 128I/O programming . . . . . . . . . . . . . . . . . . . . . . . 138.1Quasi-bidirectional I/O architecture . . . . . . . . 138.2Writing to the port (Output mode). . . . . . . . . . 138.3Reading from a port (Input mode) . . . . . . . . . 148.4Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 158.5Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 159Characteristics of the I2C-bus. . . . . . . . . . . . . 169.1Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 169.1.1START and STOP conditions . . . . . . . . . . . . . 169.2System conﬁguration . . . . . . . . . . . . . . . . . . . 169.3Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 1710Application design-in information . . . . . . . . . 1810.1Bidirectional I/O expander applications . . . . . 1810.2High current-drive load applications. . . . . . . . 1811Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 1912Static characteristics. . . . . . . . . . . . . . . . . . . . 2013Dynamic characteristics . . . . . . . . . . . . . . . . . 2114Package outline . . . . . . . . . . . . . . . . . . . . . . . . 2315Handling information. . . . . . . . . . . . . . . . . . . . 2816Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2816.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 2816.2Through-hole mount packages. . . . . . . . . . . . 2816.2.1Soldering by dipping or by solder wave . . . . . 2816.2.2Manual soldering . . . . . . . . . . . . . . . . . . . . . . 2816.3Surface mount packages . . . . . . . . . . . . . . . . 2816.3.1Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 2816.3.2Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 3016.3.3Manual soldering . . . . . . . . . . . . . . . . . . . . . . 3016.4Package related soldering information . . . . . . 3017

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 31

18Revision history . . . . . . . . . . . . . . . . . . . . . . . 3219Legal information . . . . . . . . . . . . . . . . . . . . . . 3319.1Data sheet status. . . . . . . . . . . . . . . . . . . . . . 3319.2Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 3319.3Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 3319.4Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 3320Contact information . . . . . . . . . . . . . . . . . . . . 3321

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pleasebeawarethatimportantnoticesconcerningthisdocumentandtheproduct(s)described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 12 October 2006

Document identifier: PCA9674_PCA9674A_2

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