IA4221-DS v2.3r

2023-11-26 来源：步旅网

IA4221 Universal ISM Band FSK Transmitter

DESCRIPTION

Integration’s IA4221 is a single chip, low power, multi-channel FSKtransmitter designed for use in applications requiring FCC or ETSIconformance for unlicensed use in the 433, 868, and 915 MHz bands.Used in conjunction with IA4320, Integration’s FSK receiver, the IA4221transmitter features EZRadioTM technology, which produces a flexible, lowcost, and highly integrated solution that does not require productionalignments. All required RF functions are integrated. Only an externalcrystal and bypass filtering are needed for operation. The IA4221 builds onthe features presented by the IA4220 by offering a higher output powerand an improved phase noise characteristic. The IA4221 shares the samepinout and control command set as the IA4220. The IA4221 offers all ofthe frequencies as the IA4220, with the exception of the 315 MHz band. The IA4221 features a completely integrated PLL for easy RF design, andits rapid settling time allows for fast frequency hopping, bypassingmultipath fading and interference to achieve robust wireless links. Inaddition, highly stable and accurate FSK modulation is accomplished bydirect closed-loop modulation with bit rates up to 115.2 kbps. The PLL’shigh resolution allows the use of multiple channels in any of the bands. The integrated power amplifier of the transmitter has an open-collectordifferential output that directly drive a loop antenna with programmableoutput level. No additional matching network is required. An automaticantenna tuning circuit is built in to avoid costly trimming procedures andde-tuning due to the “hand effect”.

For low-power applications, the device supports automatic activation fromsleep mode. Active mode can be initiated by several wake-up events (on-chip timer timeout, low supply voltage detection, or activation of any of thefour push-button inputs).

The IA4221’s on-chip digital interface supports both a microcontrollermode and an EEPROM mode. The latter allows complete data transmitteroperation without a microcontroller (both control commands and data areread from the EEPROM). Any wake-up event can start a transmission of thecorresponding data stored in the EEPROM.

IA4221

PIN ASSIGNMENT

Microcontroller Mode EEPROM Mode

This document refers to IA4221-IC Rev A1. See www.integration.com for any applicable errata.

See back page for ordering information.

FEATURES

• • • • • • • • • • • • • • • • • • • • • • •

Fully integrated (low BOM, easy design-in) No alignment required in production

Fast settling, programmable, high-resolution PLL Fast frequency hopping capability

Stable and accurate FSK modulation with programmable deviation

Programmable PLL loop bandwidth Direct loop antenna drive

Automatic antenna tuning circuit Programmable output power level Alternative OOK support EEPROM mode supported

SPI bus for applications with microcontroller Clock output for microcontroller

Integrated programmable crystal load capacitor

Multiple event handling options for wake-up activation Push-button event handling with switch de-bounce Wake-up timer

Low battery detection

2.2 to 5.4 V supply voltage Low power consumption Low standby current (0.3 µA) Compact 16-pin TSSOP package Transmit bit synchronization

FUNCTIONAL BLOCK DIAGRAM

CRYSTALOSCILLATORREFERENCERFP

SYNTHESIZERRFN

XTLCLOCKFREQUENCYLOAD CAPMODLOWBATTERYDETECTLOW BATTRESHOLDCONTROLLERLEVELOOKnIRQ/nLBDCLK/SDOSDISCK

TYPICAL APPLICATIONS

• • • • • • • • •

Remote control

Home security and alarm

Wireless keyboard/mouse and other PC peripherals Toy control

Remote keyless entry Tire pressure monitoring Telemetry

Personal/patient data logging Remote automatic meter reading

VDDVSS

TIMEOUTWAKE-UPTIMERPERIODnSELFSK

PB1PB2PB3PB4

IA4221-DS Rev 2.3r 0308 www.integration.com

IA4221

DETAILED DESCRIPTION

The IA4221 FSK transmitter is designed to cover the unlicensed frequency bands at 433, 868, and 915 MHz. The device facilitates compliance with FCC and ETSI requirements.

Wake-Up Timer

The wake-up timer has very low current consumption (1.5 µA typical) and can be programmed from 1 ms to several days with an accuracy of ±5%.

It calibrates itself to the crystal oscillator at every startup, and then every 30 seconds. When the oscillator is switched off, the calibration circuit switches on the crystal oscillator only long enough for a quick calibration (a few milliseconds) to facilitate accurate wake-up timing. The auto calibration feature can be disabled by setting the a bit in the Low Battery Detector Command.

PLL

The programmable PLL synthesizer determines the operating frequency, while preserving accuracy based on the on-chip crystal-controlled reference oscillator. The PLL’s high resolution allows the usage of multiple channels in any of the bands. The FSK deviation is selectable (from 30 to 210 kHz with 30 kHz increments) to accommodate various bandwidth, data rate and crystal tolerance requirements, and it is also highly accurate due to the direct closed-loop modulation of the PLL. The transmitted digital data can be sent asynchronously through the FSK pin or over the control interface using the appropriate command. The RF VCO in the PLL performs automatic calibration, which requires only a few microseconds. To ensure proper operation in the programmed frequency band, the RF VCO is automatically calibrated upon activation of the synthesizer. If temperature or supply voltage change significantly or operational band has changed, VCO recalibration is recommended.. Recalibration can be initiated at any time by switching the synthesizer off and back on again.

Event Handling

In order to minimize current consumption, the device supports sleep mode. Active mode can be initiated by several wake-up events: timeout of wake-up timer, detection of low supply voltage, pressing any of the four push-button inputs, or through the serial interface. The push-button inputs can be driven by a logic signal from a microcontroller or controlled directly by normally open switches. Pull-up resistors are integrated.

If any wake-up event occurs, the wake-up logic generates an interrupt, which can be used to wake up the microcontroller, effectively reducing the period the microcontroller has to be active. The cause of the interrupt can be read out from the transmitters by the microcontroller through the nIRQ pin.

RF Power Amplifier (PA)

The power amplifier has an open-collector differential output and can directly drive a loop antenna with a programmable output power level. An automatic antenna tuning circuit is built in to avoid costly trimming procedures and the so-called “hand effect.” The transmitters can operate in On-Off Keying (OOK) mode by switching the power amplifier on and off. When the appropriate control bit is set using the Power Setting Command, the FSK pin becomes an enable input (active high) for the power amplifier.

Interface

An SPI compatible serial interface lets the user select the operating frequency band and center frequency of the synthesizer, polarity and deviation of FSK modulation, and output power level. Division ratio for the microcontroller clock, wake-up timer period, and low battery detector threshold are also programmable. Any of these auxiliary functions can be disabled when not needed. All parameters are set to default after power-on; the programmed values are retained during sleep mode.

Crystal Oscillator

The chip has a single-pin crystal oscillator circuit, which provides a 10 MHz reference signal for the PLL. To reduce external parts and simplify design, the crystal load capacitor is internal and programmable. Guidelines for selecting the appropriate crystal can be found later in this datasheet.

The transmitters can supply the clock signal for the microcontroller, so accurate timing is possible without the need for a second crystal. When the chip receives a Sleep Command from the microcontroller and turns itself off, it provides several further clock pulses (“clock tail”) for the microcontroller to be able to go to idle or sleep mode. The length of the clock tail is programmable.

EEPROM Mode

In simple applications, the on-chip digital controller provides the transmitters with direct interface to a serial (SPI) EEPROM. In this case, no external microcontroller is necessary. Wake-up events initiate automatic readout of the assigned command sequence from EEPROM memory. For every event, there is a dedicated starting address available in the EEPROM.

Programming the EEPROM is very simple. Any control command can be programmed in the EEPROM sequentially (same as in microcontroller mode).

The internal power-on reset (POR) is a dedicated event, which can be used to program the basic settings of the transmitters. In this case the chip starts to read out the preprogrammed data from the 00h address in EEPROM. Data can be transmitted with the help of the Data Transmit Command, which tells the transmitters how many bytes must be transmitted. The whole process finishes with a Sleep Command.

Low Battery Voltage Detector

The low battery voltage detector circuit monitors the supply voltage and generates an interrupt if it falls below a programmable threshold level. The detector circuit has 50 mV hysteresis.

IA4221

PACKAGE PIN DEFINITIONS, MICROCONTROLLER MODE

Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output

Microcontroller Mode Pin Assignment

Pin Name Type Function

1 SDI DI Data input of serial control interface 2 SCK DI Clock input of serial control interface

3 nSEL DI Chip select input of serial control interface (active low) 4 PB1 DI Push-button input #1 (active low with internal pull-up resistor) 5 PB2 DI Push-button input #2 (active low with internal pull-up resistor) 6 PB3 DI Push-button input #3 (active low with internal pull-up resistor) 7 PB4 DI Push-button input #4 (active low with internal pull-up resistor) 8 CLK DO Microcontroller clock (1 MHz-10 MHz)

9 XTL AIO Crystal connection (other terminal of crystal to VSS) 10 VSS S Ground reference

11 MOD DI Connect to logic high (microcontroller mode) 12 RFN AO Power amplifier output (open collector) 13 RFP AO Power amplifier output (open collector)

14 nIRQ DO Interrupt request output for microcontroller (active low) and status read output 15 VDD S Positive supply voltage

FSK

Serial data input for FSK modulation

IA4221

Typical Application, Microcontroller Mode

VDDC11uC2100pC310pGNDR1470GP3GP6To otherGP7circuitsGP8GP9MICRO CONTROLLERGP4GP2GP1GP0SDISCKnSELPB1PB2GP5GNDCLKin (EC osc. mode)PB3PB4CLK12345678161514131211109FSKVDDnIRQRFPRFNMODVSSXTLX110MHzGNDGNDOPTIONALGNDAntennaD1LEDREDOPTIONALIA4221S1S2S3S4

IA4221

PACKAGE PIN DEFINITIONS, EEPROM MODE

Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output

EEPROM Mode Pin Assignment

Pin Name Type Function

1 SDI DI Data input of serial control interface 2 SCK DO Clock output of serial control interface

3 nSEL DO Chip select output of serial control interface (active low) 4 PB1 DI Push-button input #1 (active low with internal pull-up resistor) 5 PB2 DI Push-button input #2 (active low with internal pull-up resistor) 6 PB3 DI Push-button input #3 (active low with internal pull-up resistor) 7 PB4 DI Push-button input #4 (active low with internal pull-up resistor) 8 SDO DO Data output of serial control interface

9 XTL AIO Crystal connection (other terminal of crystal to VSS) 10 VSS S Ground reference

11 MOD DI Connect to logic low (EEPROM mode) 12 RFN AO Power amplifier output (open collector) 13 RFP AO Power amplifier output (open collector) 14 nLBD DO Low battery voltage detector output (active low) 15 VDD S Positive supply voltage

FSK

Not used, connect to VDD or VSS

IA4221

Typical Application, EEPROM Mode

VDDC11uC2100pC310pnCSSOnWPGND12348765VCCHOLDSCKSIGNDR1470EEPROM25AA080D1LEDREDGNDOPTIONALSDISCKnSELPB1PB2PB3PB4SD012345678IA4221161514131211109FSKVDDnLBDRFPRFNMODVSSXTLAntennaxX110MHzS1S2S3S4GNDGNDGND

IA4221

GENERAL DEVICE SPECIFICATIONS

All voltages are referenced to Vss, the potential on the ground reference pin VSS.

Absolute Maximum Ratings (non-operating)

Symbol Vdd Vin Voc Iin ESD Tst Tld

Parameter

Positive supply voltage

Voltage on any pin except open collector outputs Voltage on open collector outputs

Input current into any pin except VDD and VSS Electrostatic discharge with human body model Storage temperature

Lead temperature (soldering, max 10 s)

Min -0.5 -0.5 -0.5 -25 -55

Max 6.0 6.0 25 1000 125 260

Units V V mA V ºC ºC

Vdd+0.5 V

Recommended Operating Range

Symbol Vdd Voc Top

Parameter

Positive supply voltage

Voltage on open collector outputs (Max 6.0 V) Ambient operating temperature

Min 2.2 Vdd - 1 -40

Max 5.4 Vdd + 1 85

Units V V ºC

ELECTRICAL SPECIFICATION

(Min/max values are valid over the whole recommended operating range, typical conditions: Top = 27 oC; Vdd = Voc = 2.7 V)

DC Characteristics

Symbol Idd_TX_0

Parameter

Supply current

(TX mode, Pout = 0 dBm)

Conditions/Notes

433 MHz band 868 MHz band 915 MHz band

Idd_TX_PMAX

Supply current

(TX mode, Pout = Pmax) Standby current in sleep mode (Note 1)

Wake-up timer current consumption Low battery detector current consumption Idle current

Low battery detection accuracy Low battery detector threshold Digital input low level Digital input high level Digital input current Digital input current Digital output low level Digital output high level

433 MHz band 868 MHz band 915 MHz band

Ipd Iwt Ilb Ix Vlba Vlb Vil Vih Iil Iih Vol Voh

All blocks disabled

Only crystal oscillator is on

Programmable in 0.1 V steps Vil = 0 V

Vih = Vdd, Vdd = 5.4 V Iol = 2 mA Ioh = -2 mA

Min 2.25 -1 -1

Typ 12 14 15 21 23 24 0.3 1.5 0.5 1.5 +/-3

Max 5.35 1 1 0.4

µA µA µA mA % V V µA µA V V mA mA Units

0.3*Vdd V

0.7*Vdd

Vdd-0.4

Note for table above is on page 7.

IA4221

AC Characteristics

Symbol fref

Parameter

PLL reference frequency

Conditions/Notes

Crystal operation mode is parallel (Note 2)

433 MHz band, 2.5 kHz resolution

fo Transmitter frequency

868 MHz band, 5.0 kHz resolution 915 MHz band, 7.5 kHz resolution

tlock

PLL lock time

Frequency error < 10 kHz after 10 MHz

step, POR default PLL setting (Note 7) After turning on from idle mode, with crystal oscillator already stable, POR default PLL setting (Note 7) At all bands

With opt. antenna impedance (Note 4) With opt. antenna impedance (Note 4) Selectable in 3 dB steps (Note 3) At max power with loop antenna (Note 5) At low bands At high bands

100 kHz from carrier 1 MHz from carrier (Note 7) (Note 7)

Programmable in 30 kHz steps

Programmable in 0.5 pF steps, tolerance +/- 10%

After Vdd has reached 90% of final value Crystal ESR < 100 Ohms (Note 8) Crystal oscillator must be enabled to ensure proper calibration at startup (Note 8)

15 pF pure capacitive load

Min

Typ

Max

Units

8 10 12 MHz 430.24 860.48 900.72

439.75 879.51 929.27

20 µs tsp IOUT PmaxL PmaxH Pout Psp Co Qo Lout BRFSK dffsk Cxl tPOR tsx tPBt twake-up Cin, D tr, f

PLL startup time

Open collector output current (Note

Available output power (433 MHz band) Available output power (868 and 915 MHz band) Typical output power Spurious emission

Output capacitance (set by the automatic antenna tuning circuit) Quality factor of the output capacitance Output phase noise FSK bit rate

FSK frequency deviation Crystal load capacitance See Crystal Selection Guidelines Internal POR timeout (Note 6)

Crystal oscillator startup time Wake-up timer accuracy Programmable wake-up time Digital input capacitance Digital output rise/fall time

250 µs

0.5 6 mA 8 dBm 6 dBm Pmax-21 1.5 1.6 16 30 8.5 1

2.3 2.2 18 -85 -105

Pmax dBm -50 3.1 2.8 22

dBc pF dBc/Hz

115.2 kbps 512 kbps 210 16

kHz pF

BROOK OOK bit rate

150 ms 1.5 5 ms +/-10 %

5 ·

1110

2 pF 10 ns All notes for table above are on page 7.

IA4221

Note 1: Using a CR2032 battery (225 mAh capacity), the expected battery life is greater than 2 years using a 60-second wake-up period for sending 100 byte packets in length at 19.2 kbps with +3 dBm output power in the 915 MHz band.

Note 2: Using anything but a 10 MHz crystal is allowed but not recommended because all crystal-referred timing and frequency

parameters will change accordingly. Note 3: Adjustable in 8 steps.

Note 4: Optimal antenna admittance/impedance for the IA4221:

434 MHz 868 MHz 915 MHz

Yantenna [S] 1.3E-3 - j6.3E-3 1.35E-3 - j1.2E-2 1.45E-3 - j1.3E-2

Zantenna [Ohm]

31 + j152 9 + j82 8.7 + j77

Lantenna [nH]

58.00 15.20 13.60

Note 5: With selective resonant antennas (see: Application Notes available from http://www.integration.com).

Note 6: During this period, no commands are accepted by the chip. For detailed information see the Reset modes section.

Note 7: The maximum FSK bitrate and the Output phase noise are dependent on the on the actual setting of the PLL Setting Command. Note 8: The crystal oscillator start-up time strongly depends on the capacitance seen by the oscillator. Using low capacitance and low ESR

crystal is recommended. When designing the PCB layout keep the trace connecting to the crystal short to minimize stray capacitance.

IA4221

TYPICAL PERFORMANCE DATA

Phase noise measurements in the 868 MHz ISM band

50% Charge pump current setting (Ref. level: -60 dBc/Hz, 10 dB/div)

11:52:47 May 5, 2005Carrier Power-11.11 dBmAtten 0.00 dBRef -60.00dBc/Hz10.001dB/2100, 50, 33% Charge pump current settings

(Ref. level: -70 dBc/Hz, 5 dB/div)

13:30:49 May 5, 2005Phase NoisePhase NoiseLMkr4 5.00800 MHz-115.65 dBc/HzLMkr1 1.00000 MHz-101.95 dBc/HzCarrier Power-11.03 dBmAtten 0.00 dBRef -70.00dBc/Hz5.00dB/3412310 kHzMarker1234Frequency OffsetTypeSpot FreqSpot FreqSpot FreqSpot Freq 10 MHzX Axis 10 kHz 151 kHz 1 MHz5.008 MHz10 kHzMarker123Frequency OffsetTypeSpot FreqSpot FreqSpot Freq 10 MHzX Axis 1 MHz 1 MHz 1 MHzTrace2222Value-76.65 dBc/Hz-86.95 dBc/Hz-107.11 dBc/Hz-115.65 dBc/HzTrace123Value-101.95 dBc/Hz-107.05 dBc/Hz-109.98 dBc/Hz Unmodulated RF Spectrum

The output spectrum is measured at different frequencies. The output is loaded with 50 Ohms through a matching network.

At 868 MHz

10:26:50 May 5, 2005Ref 0 dBmSampLog10dB/Atten 10 dB1At 915 MHz

LMkr1 868.0010 MHz -12.2 dBm Ref 0 dBmSampLog10dB/10:34:57 May 5, 2005Atten 10 dB1LMkr1 915.0020 MHz-14.09 dBm VAvg100W1S2S3FCAAVAvg100W1S2S3FCAACenter 868 MHzRes BW 10 kHzVBW 10 kHzSpan 2 MHzSweep 40.74 ms (2001 pts)Center 915 MHzRes BW 10 kHzVBW 10 kHzSpan 2 MHzSweep 40.74 ms (2001 pts)

IA4221

Modulated RF Spectrum

At 433 MHz with

180 kHz Deviation at 64 kbps

17:11:41 Dec 7, 2005At 868 MHz with

180 kHz Deviation at 64 kbps

17:26:17 Dec 7, 2005Ref 10 dBm#SampLog10dB/Atten 20 dBRef 10 dBm#SampLog10dB/Atten 20 dBVAvg24W1S2S3FCAAVAvg50W1S2S3FCAACenter 434 MHz#Res BW 1 kHz#VBW 1 kHzSpan 2 MHzSweep 4.074 s (2000 pts)Center 868 MHz#Res BW 1 kHz#VBW 1 kHzSpan 2 MHzSweep 4.074 s (2000 pts) Spurious RF Spectrum

With 10 MHz CLK Output Enabled at 433 MHz

17:18:23 Dec 7, 2005 Antenna Tuning Characteristics

750–970 MHz

Ref 10 dBm#PeakLog10dB/Atten 20 dB1RMkr1 ∆ 19.98 MHz-44.23 dB 1VAvg3W1S2S3FCAACenter 434 MHz#Res BW 3 kHz#VBW 300 HzSpan 50 MHzSweep 45.47 s (2000 pts)

The antenna tuning characteristics was recorded in “max-hold” state of the spectrum analyzer. During the measurement, the transmitters were forced to change frequencies by forcing an external reference signal to the XTL pin. While the carrier was changing the antenna tuning circuit switched trough all the available states of the tuning circuit. The graph clearly demonstrates that while the complete output circuit had about a 40 MHz bandwidth, the tuning allows operating in a 220 MHz band. In other words, the tuning circuit can compensate for 25% variation in the resonant frequency due to any process or manufacturing spread.

IA4221

CONTROL INTERFACE

Commands to the transmitters are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. The number of bits sent is an integer multiple of 8. All commands consist of a command code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-bit command). Bits having no influence (don’t care) are indicated with X. The Power On Reset (POR) circuit sets default values in all control and command registers.

The status information or received data can be read serially over the IRQ pin. Bits are shifted out upon the falling edge of CLK signal

Timing Specification

Symbol tCH tCL tSS tSH tSHI tDS tDH tOD tBL

Parameter Clock high time Clock low time

Select setup time (nSEL falling edge to SCK rising edge) Select hold time (SCK falling edge to nSEL rising edge) Select high time

Data setup time (SDI transition to SCK rising edge) Data hold time (SCK rising edge to SDI transition) Data delay time

Push-button input low time

Minimum value [ns]

25 25 10 10 25 5 5 10 25

Timing Diagram

tSSnSELtCHtCLtODtSHtSHISCKtDSSDItDHBIT15BIT14BIT13BIT8BIT7BIT1BIT0nIRQPORWK-UPnIRQ

IA4221

Control Commands

1 2 3 4 5 6 7 8 9 10 11 12

Control Command

Configuration Setting Command Power Management Command Frequency Setting Command Data Rate Command Power Setting Command Low Battery Detector Command Sleep Command Push-Button Command Wake-Up Timer Command Data Transmit Command Status Register Command

PLL Setting and Reset Mode Command

Related Parameters/Functions

Frequency band, microcontroller clock output, crystal load capacitance, frequency deviation

Crystal oscillator, synthesizer, power amplifier, low battery detector, wake-up timer, clock output buffer Carrier frequency Bit rate

Nominal output power, OOK mode

Low battery threshold limit, transmit bit synchronizer, wake-up timer calibration

Length of the clock tail after power down Push-button related functions Wake-up time period Data transmission Transmitter status read PLL bandwidth, reset mode

Related control bits b1 to b0, d2 to d0, x3 to x0, ms, m2 to m0 a1 a0, ex, es, ea, eb, et, dc f11 to f0 r7 to r0 ook, p2 to p0 dwc, ebs, t4 to t0 s7 to s0

p4, d1 to d0, b4 to b1, bc

r4 to r0, m7 to m0

bw1 to bw0, dr

Note: In the following tables the POR column shows the default values of the command registers after power-on.

1. Configuration Setting Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 b1 b0 d2 d1 d0 x3 x2 x1 x0 ms m2 m1 m0 POR

8080h

b10011b00101Frequency Band {MHz]315433868915 d200001111d100110011d001010101 x30000x20000x10011x00101Crystal Load Capacitance [pF]8.59.09.510.0…Clock OutputFrequency [MHz]11.251.6622.53.335101111110115.516.0 The resulting output frequency can be calculated as:

fout = f0 – (-1)SIGN * (M + 1) * (30 kHz)

where:

f0 is the channel center frequency (see the next command) M is the three bit binary number SIGN = (ms) XOR (FSK input) Note:

•

Use M in a range from 0 to 6.

IA4221

2. Power Management Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 0 0 0 0 a1 a0 ex es ea eb et dc POR

C000h

Bits 5-0, enable the corresponding block of the transmitters, i.e. the crystal oscillator is enabled by the ex bit, the synthesizer by es, the power amplifier by ea and the low battery detector by eb, while the wake-up timer by et. The bit dc disables the clock output buffer. When receiving the Data Transmit Command, the chip supports automatic on/off control over the crystal oscillator, the PLL and the PA. If bit a1 is set, the crystal oscillator and the synthesizer are controlled automatically. Data Transmit Command starts up the crystal oscillator and as soon as a stable reference frequency is available the synthesizer starts. After a subsequent delay to allow locking of the PLL, if a0 is set the power amplifier is turned on as well. Note:

• • •

To enable the automatic internal control of the crystal oscillator, the synthesizer and the power amplifier, the corresponding bits (ex, es, ea) must be zero in the Power Management Command.

In microcontroller mode, the ex bit should be set in the Power Management Command for the correct control of es and ea. The oscillator can be switched off by clearing the ex bit after the transmission.

In EEPROM operation mode after an identified Data Transmit Command the internal logic switches on the synthesizer and PA. At the end of Data Transmit Command header if necessary the current clock cycle is automatically extended to ensure the PLL stabilization and RF power ramp-up.

In EEPROM operation mode the internal logic switches off the PA when the given number of bytes is transmitted. (See: Data Transmit Command in EEPROM operation.)

When the chip is controlled by a microcontroller, the Sleep Command can be used to indicate the end of the data transmission process, because in microcontroller mode the Data Transmit Command does not contain the length of the TX data.

For processing the events caused by the peripheral blocks (POR, LBD, wake-up timer, push-buttons) the chip requires operation of the crystal oscillator. This operation is fully controlled internally, independently from the status of the ex bit, but if the dc bit is zero, the oscillator remains active until Sleep Command is issued. (This command can be considered as an event controller reset.)

• • •

Oscillator control logic

IA4221

3. Frequency Setting Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 POR

A7D0h

The 12-bit parameter of the Frequency Setting Command has the value F. The value F should be in the range of 96 and 3903. When F is out of range, the previous value is kept. The synthesizer center frequency f0 can be calculated as:

f0 = 10 MHz * C1 * (C2 + F/4000)

The constants C1 and C2 are determined by the selected band as:

Band [MHz] C1 C2

433 1 43 868 2 43 Note:

•

915 3 30 For correct operation of the frequency synthesizer, the frequency and band of operation need to be programmed before the

synthesizer is started. Directly after activation of the synthesizer, the RF VCO is calibrated to ensure proper operation in the programmed frequency band.

4. Data Rate Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 0 0 0 r7 r6 r5 r4 r3 r2 r1 r0 POR

C800h

In EEPROM mode the transmitted bit rate is determined by the 8-bit value R (bits ) as:

BR = 10 MHz / 29 / (R+1)

Apart from setting custom values, the standard bit rates from 2.4 to 115.2 kbps can be approximated with minimal error. The commands are read out with a different fixed bit rate: Note:

•

PLL bandwidth should be set according the data rate. Please see the PLL Setting Command. Fsck = 10 MHz / 29 / 3 [~115.2 kHz]

5. Power Setting Command

bit 7 6 5 4 3 2 1 0 1 0 1 1 ook p2 p1 p0 POR

B0h

The bit ook enables the OOK mode for the PA, in this case the data to be transmitted are received through the FSK pin.

p2 p1 p0 Relative Output Power [dB]0000111100110011010101010-3-6-9-12-15-18-21The output power is given in the table as relative to the maximum available power, which depends on the actual antenna impedance. (See: Antenna Application Note available from www.integration.com).

IA4221

6. Low Battery Detector Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 0 0 1 0 dwc0 ebst4 t3 t2 t1 t0 POR

C200h

Bit 7 Disables the Wake-up timer periodical (every 30 second) calibration if this bit is set.

Bit 5 Enables the TX bit synchronization circuit. The data rate must be set by the Data Rate Command.

The 5-bit value T of determines the threshold voltage Vlb of the detector:

Vlb = 2.25 V + T * 0.1 V

7. Sleep Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 0 1 0 0 s7 s6 s5 s4 s3 s2 s1 s0 POR C410h

The effect of this command depends on the Power Management Command. It immediately disables the power amplifier (if a0=1 and ea=0) and the synthesizer (if a1=1 and es=0). Stops the crystal oscillator after S periods of the microcontroller clock (if a1=1 and ex=0) to enable the microcontroller to execute all necessary commands before entering sleep mode itself. The 8-bit value S is determined by bits .

IA4221

8. Push-Button Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 0 1 0 p4 d1 d0 b4 b3 b2 b1 bc POR

CA00h

If the corresponding bit was set (b1-b4) the event remains active while the button is pressed. In EEPROM mode, the chip is continuously performing the routine assigned to the push-button while it is pressed. In microcontroller mode, the chip continuously generates interrupts on nIRQ until the push-button is released. Weak pull-up currents are switched off when bc is high. The d0, d1 bits set the de-bouncing time period:

d1 0 0 1 1

d0 0 1 0 1

De-bouncing Time [ms] 160 40 10

0 (Bypassed)

Note:

• • •

Until the de-bouncing time has expired, the crystal oscillator remains switched on, independent of the status of the ex bit in the Power Management Command. (Because the circuit uses the crystal oscillator signal for timing.)

If the p4 bit is set, the controller performs the routine assigned to the fourth button when PB1 and PB2 are pressed down simultaneously. With the addition of this feature, there is a way to build a device that uses 3 buttons, but performs 4 functions. It is possible to detect multiple pressed push-buttons, in both modes. In EEPROM mode the controller executes sequentially all the routines belonging to the pressed buttons.

IA4221

Simultaneously Pressed Push-Button Detect by Microcontroller

Microcontroller modeVddPOR(internal)Push buttoninput 1Push buttoninput 2nIRQPORPB1PB_nIRQdly*PB1PB2PB1PB2PB1SPIStatus rdStatus rdStatus rdStatus rdStatus rdStatus rdStatus rdNote:*PB_nIRQdly is equal with thedebounce time Simplified Block Diagram of Push-Button 1–4 Inputs

POR, LBD, WAKE UP TIMER, P. BUTTONS EVENT FLAGSVDDWEAK PULL-UP ENABLE/DISABLEVDDNotice:Only one EVENT is serviced simultaneously the others are pending.bcEVENT FLAGDQPush-button1,2,3CLKDigital glitch filterCLR for P.B1,2CLRSLEEP Command *STAT. REG. READ Command **Internal blocker signal to Push-button1 and Push-button2p4Push-button1Push-button2COUNT/SINGLEb1, b2, b3To Digital glitch filter forPush-button4With internal weak pull-upPush-button4Note:* In EEprom mode** In uC controlled mode

IA4221

9. Wake-Up Timer Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 r4 r3 r2 r1 r0 m7 m6 m5 m4 m3 m2 m1 m0 POR E000h

The wake-up time period can be calculated as:

Twake-up = M * 2R [ms] ,

where M is defined by the digital value and R is defined by the digital value.

The value of R should be in the range of 0 and 23. The maximum achievable wake-up time period can be up to 24 days. Note:

•

Software reset: Sending FE00h command to the chip triggers software reset. For more details see the Reset modes section.

For continual operation the et bit should be cleared and set at the end of every cycle.

10. Data Transmit Command

In EEPROM operation mode:

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 0 1 1 0 n7 n6 n5 n4 n3 n2 n1 n0 POR - -

In microcontroller slave mode:

bit 7 6 5 4 3 2 1 0 1 1 0 0 0 1 1 0 This command indicates that the following bitstream coming in via the serial interface is to be transmitted. In EEPROM mode, the 8-bit value N of bits contains the number of data bytes to follow. Note:

• • • • •

This command is not needed if the transmitters’ power management bits (ex, es, ea) are fully controlled by the microcontroller and TX data comes through the FSK pin.

If the crystal oscillator was formerly switched off (ex=0), the internal oscillator needs tsx time, to switch on. The actual value depends on the type of quartz crystal used.

If the synthesizer was formerly switched off (es=0), the internal PLL needs tsp startup time. Valid data can be transmitted only when the internal locking process is finished.

In EEPROM mode, before issuing the Data Transmit Command, the power amplifier must be enabled, with the ea or a0 bit in the Power Management Command.

In EEPROM mode, when N bytes have been read and transmitted the controller continues reading the EEPROM and processing the data as control commands. This process stops after Sleep Command has been read from the EEPROM.

IA4221

Data Transmit Sequence Through the FSK Pin

nSELP o w e r M a n a g e m e n t C o m m a n dC 0 hSCKinstructionSDI3 8 htsx *Internal operationsa0, a1 = 0ex, es, ea = 1Xtal osc staustsp *synthesizer / PLL / PA statussynthesizer on, PLL locked, PA ready to transmitxtal osc. stableFSKd o n ' t c a r eT X D A T ANOTE:* See page 6 for the timing values Data Transmit Sequence Through the SDI Pin

Note:

• • •

Do not send CLK pulses with the TX data bits, otherwise they will be interpreted as commands. This mode is not SPI compatible, therefore it is not recommended in microcontroller mode. If the crystal oscillator and the PLL are running, the tsx+tsp delay is not needed.

IA4221

11. Status Register Read Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 POR - -

With this command, it is possible to read the chip’s status register through the nIRQ pin. This command clears the last serviced interrupt and

processing the next pending one will start (if there is any).

Status Register Read Sequence

nSEL0SCKinstructionSDIstatus outnIRQPORPB1PB2PB3PB4LBDWK-UPnIRQ123456789101112131415 12. PLL Setting and Reset Mode Command

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 1 0 0 1 0 bw1bw00 0 0 0 dr 0 POR

D200h

Bits 7-6 select the PLL bandwidth:

bw1 bw0 Max datarate

[kbps]

19.2 38.4 68.9 115.2

Phase Noise at 1MHz offset

[dBc/Hz] (typical)

-112 -110 -107 -102

Charge pump current

25% 33% 50% 100%

0 1 1 1 0 0 1 0 Bit 1 (dr): Disables the highly sensitive RESET mode. If this bit is cleared, a 600 mV glitch in the power supply may cause a system reset. For more detailed description see the Reset modes section.

IA4221

EEPROM MODE

In this mode, the transmitters can operate with a standard at least 1 kbyte serial EEPROM with an SPI interface, and no microcontroller is necessary. The following events cause wake-up of the device:

Event Number N

1 2 3 4 5 6

EEPROM entry point

0080h 0100h 0180h 0200h 0280h 0300h

Description

low level on input PB1 low level on input PB2 low level on input PB3 low level on input PB4 low supply voltage level wake-up timer timeout

0 0000h power-on

After any of these events, the crystal oscillator turns on and the device starts to read bytes from the EEPROM continuously (block read)

starting from address N * 128 (decimal) and executes them as commands as described in the previous section. Note:

Zero bytes can be put in the EEPROM for timing purposes. Never put more than 31 consecutive zero bytes into the EEPROM’s active region (between the actual entry point and the closing Sleep Command).

Example EEPROM Hexa Content

Power-On Reset:

00000000 C0 C4 CA 1E C8 23 C4 00 00 00 00 00 00 00 00 00 00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000060 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000070 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Short Explanation:

Data in Address, Command, and Parameter fields are hexadecimal values. For the detailed description of the control command bits, see previous section.

Address

Command

Parameter

Related Control Command

Remarks

Crystal– Synthesizer – Power Amplifier auto on/off mode enable

Continuous execution for all push buttons BR=10M/29/(35+1)~9600 bps Power down

00–01 C0 02–03 CA 04–05

06-07 C4

C4 Power Management 1E Push Button 23

Bit Rate

00 Sleep

IA4221

Push-button 1:

00000080 88 72 A6 10 C6 60 55 55 55 55 55 55 55 55 55 55 00000090 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 000000A0 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 000000B0 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 000000C0 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 000000D0 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 000000E0 55 55 55 55 55 55 C4 00 00 00 00 00 00 00 00 00 000000F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Short Explanation:

Address

Command

Parameter

Related Control Command

Remarks

433MHz band, Xtal CL=12pF

80–81 8 872 Configuration Control

fdev=90kHz 82–83 A 610 Frequency 84–85 E6–E7

C6 C4

60 00

Data Transmit Sleep

86–E5 60x55

fc=(43+1552/4000)*10MHz Transmit the next 96 bytes Data

Power down, go to address 80

Note:

This routine is repeatedly executed while PB1 is pressed, because continuous execution was selected at POR (CA1E code issued in the power-on reset section before).

RX-TX ALIGNMENT PROCEDURES

RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To minimize these errors it is suggested to use the same crystal type and the same PCB layout for the crystal placement on the RX and TX PCBs.

To verify the possible RX-TX offset it is suggested to measure the CLK output of both chips with a high level of accuracy. Do not measure the output at the XTL pin since the measurement process itself will change the reference frequency. Since the carrier frequencies are derived from the reference frequency, having identical reference frequencies and nominal frequency settings at the TX and RX side there should be no offset if the CLK signals have identical frequencies.

It is possible to monitor the actual RX-TX offset using the AFC status report included in the status byte of the receiver. By reading out the status byte from the receiver the actual measured offset frequency will be reported. In order to get accurate values the AFC has to be disabled during the read by clearing the \"en\" bit in the AFC Control Command (bit 0).

IA4221

CRYSTAL SELECTION GUIDELINES

The crystal oscillator of the IA4221 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load capacitor in order to minimize the external component count. The internal load capacitance value is programmable from 8.5 pF to 16 pF in 0.5 pF steps. With appropriate PCB layout, the total load capacitance value can be 10 pF to 20 pF so a variety of crystal types can be used.

When the total load capacitance is not more than 20 pF and a worst case 7 pF shunt capacitance (C0) value is expected for the crystal, the oscillator is able to start up with any crystal having less than 100 ohms ESR (equivalent series loss resistance). However, lower C0 and ESR values guarantee faster oscillator startup. It is recommended to keep the PCB parasitic capacitances on the XTL pin as low as possible. The crystal frequency is used as the reference of the PLL, which generates the RF carrier frequency (fc). Therefore fc is directly proportional to the crystal frequency. The accuracy requirements for production tolerance, temperature drift and aging can thus be determined from the maximum allowable carrier frequency error.

Maximum XTAL Tolerances Including Temperature and Aging [ppm]

Bit Rate:2.4 kbps433 MHz868 MHz915 MHzBit Rate:9.6 kbps433 MHz868 MHz915 MHzBit Rate:38.4 kbps433 MHz868 MHz915 MHzBit Rate:115.2 kbps433 MHz868 MHz915 MHz30don't usedon't usedon't use60don't usedon't usedon't use30don't usedon't usedon't use60201010301588605025253020101060502525Transmitter Deviation [+/- kHz]9012015075100100406075405075Transmitter Deviation [+/- kHz]9012015075100100406075405070Transmitter Deviation [+/- kHz]901201505075100304060254060Transmitter Deviation [+/- kHz]90120150don't usedon't use30don't usedon't use20don't usedon't use151801001007521010010010018010075752101001001001801007575210100100751805030302101005050

Whenever a low frequency error is essential for the application, it is possible to “pull” the crystal to the accurate frequency by changing the load capacitor value. The widest pulling range can be achieved if the nominal required load capacitance of the crystal is in the “midrange”, for example 16 pF. The “pull-ability” of the crystal is defined by its motional capacitance and C0. Note:

•

There may be other requirements for the TX carrier accuracy with regards to the requirements as defined by standards and/or channel separations.

IA4221

RESET MODES

The chip will enter into reset mode if any of the following conditions are met:

• • •

Power-on reset: During a power up sequence until the Vdd has reached the correct level and stabilized Power glitch reset: Transients present on the Vdd line Software reset: Special control command received by the chip

Power-on reset

After power up the supply voltage starts to rise from 0V. The reset block has an internal ramping voltage reference (reset-ramp signal), which is rising at 100mV/ms (typical) rate. The chip remains in reset state while the voltage difference between the actual Vdd and the internal reset-ramp signal is higher than the reset threshold voltage, which is 600 mV (typical). As long as the Vdd voltage is less than 1.6V (typical) the chip stays in reset mode regardless the voltage difference between the Vdd and the internal ramp signal.

The reset event can last up to 150ms supposing that the Vdd reaches 90% its final value within 1ms. During this period the chip does not accept control commands via the serial control interface. Power-on reset example:

Power glitch reset

The internal reset block has two basic mode of operation: normal and sensitive reset. The default mode is sensitive, which can be changed by the appropriate control command (see Related control commands at the end of this section). In normal mode the power glitch detection circuit is disabled.

There can be spikes or glitches on the Vdd line if the supply filtering is not satisfactory or the internal resistance of the power supply is too high. In such cases if the sensitive reset is enabled an (unwanted) reset will be generated if the positive going edge of the Vdd has a rising rate greater than 100mV/ms and the voltage difference between the internal ramp signal and the Vdd reaches the reset threshold voltage (600 mV). Typical case when the battery is weak and due to its increased internal resistance a sudden decrease of the current consumption (for example turning off the power amplifier) might lead to an increase in supply voltage. If for some reason the sensitive reset cannot be disabled step-by-step decrease of the current consumption (by turning off the different stages one by one) can help to avoid this problem. Any negative change in the supply voltage will not cause reset event unless the Vdd level reaches the reset threshold voltage (250mV in normal mode, 1.6V in sensitive reset mode).

If the sensitive mode is disabled and the power supply turned off the Vdd must drop below 250mV in order to trigger a power-on reset event when the supply voltage is turned back on. If the decoupling capacitors keep their charges for a long time it could happen that no reset will be generated upon power-up because the power glitch detector circuit is disabled.

Note that the reset event reinitializes the internal registers, so the sensitive mode will be enabled again.

IA4221

Sensitive Reset Enabled, Ripple on Vdd:

VddReset threshold voltage (600mV)Reset ramp line (100mV/ms)1.6VtimenRes output HL Sensitive reset disabled:

VddReset threshold voltage (600mV)Reset ramp line (100mV/ms)250mVtimenRes output HL Software reset

Software reset can be issued by sending the appropriate control command (described at the end of the section) to the chip. The result of the command is the same as if power-on reset was occurred. Vdd line filtering

During the reset event (caused by power-on, fast positive spike on the supply line or software reset command) it is very important to keep the Vdd line as smooth as possible. Noise or periodic disturbing signal superimposed the supply voltage may prevent the part getting out from reset state. To avoid this phenomenon use adequate filtering on the power supply line to keep the level of the disturbing signal below 10mVp-p in the DC – 50kHz range for 200ms from Vdd ramp start.. Typical example when a switch-mode regulator is used to supply the radio, switching noise may be present on the Vdd line. Follow the manufacturer’s recommendations how to decrease the ripple of the regulator IC and/or how to shift the switching frequency. Related control commands

“PLL setting and Reset Mode Command”

Setting bit<1> to high will change the reset mode to normal from the default sensitive.

“SW Reset Command”

Issuing FE00h command will trigger software reset. See the Wake-up Timer Command.

IA4221

SIMPLIFIED INTERNAL CONTROL AND TIMING

The internal controller uses the clock generated by the crystal oscillator to sequentially process the various events and to de-bounce the push-button (PB) inputs. If the oscillator is not running, internal logic automatically turns it on temporarily and then off again. Such events are: any wake-up event (POR, PB press, wake-up timer timeout and low supply voltage detection), PB release and status read request by the microcontroller.

If two wake-up events occur in succession, the crystal oscillator stays on until the next status read (acknowledgment of the first event).

Simplified Internal Control and Timing Diagrams

Microcontrollermode(ec=0, ex=0)VddPOR(internal)Push-buttoninputxDebouncing Time + TOsc_On(Internal)sx*SPIStatusrdcmdStatusrdcmdnIRQStat. bits(POR)Tsx*Stat. bits(PBx)Tsx*Microcontroller modewithmultiple eventread(ec=0, ex=0)VddPOR(internal)Push-buttoninputxOsc_On(Internal)SPIStatusrdcmdStatusrdcmdnIRQStat. bits(POR)1usStat. bits(PBx)Tsx*Microcontrollermode(ec=1, ex=0)VddPOR(internal)Push-buttoninputxOsc_On(Internal)SPIStatus rdSleepcmdTclk_tail**Status rdSleepcmdTclk_tail**Note:* Tsx : Crystal oscillator startup timeand** Length of Tclk_tail is determined by the parameter in the Sleep comm

IA4221

MATCHING NETWORK FOR A 50 OHM SINGLE ENDED OUTPUT

Matching Network Schematic

IA4221 433 MHz 868 MHz 915 MHz

L1 [nH]

L2 [nH]

L3 [nH]

L4 [nH]

C1 [pF] (Note 1)

C1 [pF] (Note 2)

C2 [pF]

C3 [pF]

C4 [pF] (Note 3)

16 47 390 16 3.3 3.3 6.0 2.7 220 5.1 24 100 5.1 2 1.5 2.2 1.2 47 4.3 24 100 4.3 2 1.8 2.2 1.2 33

Note 1: 1 mm thick board Note 2: 1.5 mm thick board

Note 3: C4 must be connected parallel to the supply decoupling capacitors (10nF + 2.2µF recommended) as close as possible to the VDD and VSS pins

IA4221

EXAMPLE APPLICATIONS: DATA PACKET TRANSMISSION

Data packet structure

An example data packet structure using the IA422x – IA4320 pair for data transmission. This packet structure is an example of how to use the high efficiency FIFO mode at the receiver side:

AAAAAA2DD4D0D1D2Preamble. . .DNDatabytes (received in the FIFO of the receiver)Synchron pattern

The first 3 bytes compose a 24 bit length ‘01’ pattern to let enough time for the clock recovery of the receiver to lock. The next two bytes compose a 16 bit synchron pattern which is essential for the receiver’s FIFO to find the byte synchron in the received bit stream. The synchron patters is followed by the payload. The first byte transmitted after the synchron pattern (D0 in the picture above) will be the first received byte in the FIFO.

Important: The bytes of the data stream should follow each other continuously, otherwise the clock recovery circuit of the receiver side will be unable to track.

Further details of packet structures can be found in the IA ISM-UGSB1 software development kit manual.

IA4221

EXAMPLE APPLICATIONS

For Microcontroller Mode

Schematic

IA4221

PCB Layout of Keyboard Transmitter Demo Circuit Using Microcontroller Mode (operating in the 915 MHz band)

Top Layer

Bottom Layer

IA4221

For EEPROM Mode

Schematic

PCB Layout of Push-Button Transmitter Demo Circuit Using EEPROM Mode (operating in the 434 MHz band)

Top Layer

Bottom Layer

IA4221

PACKAGE INFORMATION

16-pin TSSOP

SeeDetail“A”SectionB-BGaugePlane0.25Detail“A”SymbolAA1A2bb1cc1DeEE1LL1RR1123DimensionsinmmMin.Nom.Max.1,200,050,150,800,901,050,190,300,190,220,250,090,200,090,164,905,005,100.65BSC.6.40BSC.4,304,404,500,500,600,751.00REF.0,090,090812REF.12REF.DimensionsinInchesMin.Nom.Max.0,0470,0020,0060,0310,0350,0410,0070,0120,0070,0090,0100,0040,0080,0040,0060,1930,1970,2010.026BSC.0.252BSC.0,1690,1730,1770,0200,0240,0300.39REF.0,0040,0040812REF.12REF.

IA4221

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IA4221

全部栏目

IA4221-DS v2.3r