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5429FCT521DTSOB资料

2021-07-27 来源:步旅网
元器件交易网www.cecb2b.comMULTILEVELPIPELINE REGISTERSIntegrated Device Technology, Inc.IDT29FCT520AT/BT/CT/DTIDT29FCT521AT/BT/CT/DTFEATURES:••••

A, B, C and D speed grades

Low input and output leakage ≤1µA (max.)CMOS power levels

True TTL input and output compatibility– VOH = 3.3V (typ.)– VOL = 0.3V (typ.)

High drive outputs (-15mA IOH, 48mA IOL)

Meets or exceeds JEDEC standard 18 specificationsProduct available in Radiation Tolerant and RadiationEnhanced versions

Military product compliant to MIL-STD-883, Class Band DESC listed (dual marked)

Available in DIP, SOIC, SSOP, QSOP, CERPACK andLCC packages

DESCRIPTION:The IDT29FCT520AT/BT/CT/DT and IDT29FCT521AT/BT/CT/DT each contain four 8-bit positive edge-triggeredregisters. These may be operated as a dual 2-level or as asingle 4-level pipeline. A single 8-bit input is provided and anyof the four registers is available at the 8-bit, 3-state output.These devices differ only in the way data is loaded into andbetween the registers in 2-level operation. The difference isillustrated in Figure 1. In the IDT29FCT520AT/BT/CT/DTwhen data is entered into the first level (I = 2 or I = 1), theexisting data in the first level is moved to the second level. Inthe IDT29FCT521AT/BT/CT/DT, these instructions simplycause the data in the first level to be overwritten. Transfer ofdata to the second level is achieved using the 4-level shiftinstruction (I = 0). This transfer also causes the first level tochange. In either part I=3 is for hold.

•••••

FUNCTIONAL BLOCK DIAGRAM

D -D07

8MUXI ,I012REGISTERCONTROL1OCTAL REG. A1OCTAL REG. B1CLK

OCTAL REG. A2OCTAL REG. B2S ,S012MUXOE82619 drw 01Y -Y07

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

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©1994 Integrated Device Technology, Inc.

APRIL 1994

DSC-4215/4

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PIN CONFIGURATIONS

I0I1D0D1D2D3D4D5D6D7CLKGND

123456789101112IDT29FCT520AT/BT/CT/DT, 521AT/BT/CT/DTMULTILEVEL PIPELINE REGISTERS

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242322P24-1D24-1SO24-2SO24-7SO24-8*&E24-1212019181716151413D7CLKGNDNCOEY7Y6VccS0S1Y0Y1Y2Y3Y4Y5Y6Y7OE2619 drw 02

INDEXD0I1I0NCVccS0S143212827262524235678910D1D2D3NCD4D5D6L28-1222120111912131415161718Y0Y1Y2NCY3Y4Y52619 drw 03*FCT520 only

DIP/SOIC/SSOP/QSOP/CERPACK

TOP VIEWLCCTOP VIEW

DEFINITION OF FUNCTIONAL TERMSPin NamesDnCLKI0, I1S0, S1OEYnDescriptionRegister input Port.Clock input. Enter data into registers on LOW-to-HIGH transitions.Instruction inputs. See Figure 1 and in-struction Control Tables.Multiplexer select. Inputs either register A1, A2,B1 or B2 data to be available at the output port.Output enable for 3-state output port.Register output port.2619 tbl 01

REGISTER SELECTIONS10011S00101RegisterB2B1A2A12619 tbl 02

DUAL 2-LEVELSINGLE 4-LEVELA1IDT29FCT520TA2I = 2B1A1B1A1B1B2A2I = 1B2A2I = 0B2A1IDT29FCT521TA2I = 2NOTE:

1. I = 3 for hold.

B1A1B1A1B1B2A2I = 1B2A2I = 0B2Figure 1. Data Loading in 2-Level Operation

2619 drw 04

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IDT29FCT520AT/BT/CT/DT, 521AT/BT/CT/DTMULTILEVEL PIPELINE REGISTERS

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ABSOLUTE MAXIMUM RATINGS(1)

SymbolRatingCommercialVTERM(2)Terminal Voltage–0.5 to +7.0with Respect toGNDVTERM(3)Terminal Voltage–0.5 towith Respect toVCC +0.5GNDTAOperating0 to +70TemperatureTBIASTemperature–55 to +125Under BiasTSTGStorage–55 to +125TemperaturePTPower Dissipation0.5IOUTDC OutputCurrentMilitary–0.5 to +7.0UnitVCAPACITANCE (TA = +25°C, f = 1.0MHz)SymbolParameter(1)CINInput CapacitanceCOUTOutput CapacitanceConditionsVIN = 0VVOUT = 0VTyp.68Max.Unit10pF12pF2619 lnk 04–0.5 toVCC +0.5–55 to +125–65 to +135–65 to +1500.5V°C°C°CWNOTE:1. This parameter is measured at characterization but not tested.

–60 to +120 –60 to +120 mA2619 lnk 03NOTES:1.Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-INGS may cause permanent damage to the device. This is a stress ratingonly and functional operation of the device at these or any other conditionsabove those indicated in the operational sections of this specification isnot implied. Exposure to absolute maximum rating conditions forextended periods may affect reliability. No terminal voltage may exceedVCC by +0.5V unless otherwise noted.2.Input and VCC terminals only.3.Outputs and I/O terminals only.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%SymbolVIHVILIIHIILIOZHIOZLIIVIKIOSVOHParameterInput HIGH LevelInput LOW LevelInput HIGH CurrentHigh Impedance(4)Output CurrentInput HIGH Current(4)Clamp Diode VoltageShort Circuit CurrentOutput HIGH VoltageVCC = Max., VI = VCC (Max.)VCC = Min., IN = –18mAVCC = Max.(3), VO = GNDVCC = Min.VIN = VIH or VILIOH = –6mA MIL.IOH = –8mA COM’L.IOH = –12mA MIL.IOH = –15mA COM’L.VOLVHICCOutput LOW VoltageInput HysteresisQuiescent PowerSupply CurrentVCC = Max.VIN = GND or VCCVCC = Min.VIN = VIH or VIL—IOL = 32mA MIL.IOL = 48mA COM’L.——2000.01—1mVmA2619 tbl 05

Test Conditions(1)Guaranteed Logic HIGH LevelGuaranteed Logic LOW Level(4)Min.2.0—Typ.(2)———————–0.7–1203.33.00.3Max.—0.8±1±1±1±1±1–1.2–225——0.5UnitVVµAµAµAµAVmAVVCC = Max.VCC = Max.VCC = Max.VI = 2.7VVI = 0.5VVO = 2.7VVO = 0.5V——————–602.42.0—Input LOW Current(4)VNOTES:1.For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.2.Typical values are at VCC = 5.0V, +25°C ambient.

3.Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.4.The test limit for this parameter is ±5µA at TA = -55°C.

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IDT29FCT520AT/BT/CT/DT, 521AT/BT/CT/DTMULTILEVEL PIPELINE REGISTERS

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POWER SUPPLY CHARACTERISTICSSymbol∆ICCICCDParameterQuiescent Power SupplyCurrent, TTL Inputs HIGHDynamic Power Supply Current(4)Test Conditions(1)VCC = Max.VIN = 3.4V(3)VCC = Max., Outputs OpenOE = GNDOne Input Toggling50% Duty CycleVCC = Max., Outputs OpenfCP = 10MHz50% Duty CycleOE = GNDOne Bit Togglingat fi = 5MHz50% Duty CycleVCC = Max., Outputs OpenfCP = 10MHz50% Duty CycleOE = GNDEight Bits Togglingat fi = 2.5MHz50% Duty CycleVIN = VCCVIN = GNDMin.——Typ.(2)0.50.15Max.2.00.25UnitmAmA/MHzICTotal Power Supply Current(6)VIN = VCCVIN = GND—1.53.5mAVIN = 3.4VVIN = GNDVIN = VCCVIN = GND—2.05.5—3.87.3(5)VIN = 3.4VVIN = GND—6.016.3(5)NOTES:

1.For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.2.Typical values are at VCC = 5.0V, +25°C ambient.

3.Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.

4.This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

5.Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.6.IC = IQUIESCENT +IINPUTS + IDYNAMIC

IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)ICC = Quiescent Current

∆ICC = Power Supply Current for a TTL HIgh Input (VIN = 3.4V)DH = Duty Cycle for TTL Inputs HighNT = Number of TTL inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)fi = Input Frequency

Ni = Number of Inputs at fi

All currents are in milliamps and all frequencies are in megahertz.

2619 tbl 06

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IDT29FCT520AT/BT/CT/DT, 521AT/BT/CT/DTMULTILEVEL PIPELINE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGEFCT520AT/521ATCom'l.SymboltPHLtPLHtPHLtPLHtSUtHtSUtHtPHZtPLZtPZHtPZLtWParameterPropagation DelayCLK to YnPropagation DelayS0 or S1 to YnSet-up Time, HIGH or LOWDn to CLKHold Time, HIGH or LOWDn to CLKSet-up Time, HIGH or LOWI0 or I1 to CLKHold Time, HIGH or LOWI0 or I1 to CLKOutput Disable TimeOutput Enable TimeClock Pulse Width HIGH or LOWCondition(1)CL = 50pFRL = 500ΩMin.(2)2.02.05.02.05.02.01.51.57.0Max.14.013.0————12.015.0—Mil.Min.(2)2.02.06.02.06.02.01.51.58.0Max.16.015.0————13.016.0—FCT520BT/521BTCom'l.Min.(2)2.02.02.52.04.02.01.51.55.5Max.7.57.5————7.07.5—Mil.Min.(2)2.02.02.82.04.52.01.51.56.0Max.8.08.0————7.58.0—Unitnsnsnsnsnsnsnsnsns2619 tbl 07FCT520CT/521CTCom'l.SymboltPHLtPLHtPHLtPLHtSUtHtSUtHtPHZtPLZtPZHtPZLtWParameterPropagation DelayCLK to YnPropagation DelayS0 or S1 to YnSet-up Time, HIGH or LOWDn to CLKHold Time, HIGH or LOWDn to CLKSet-up Time, HIGH or LOWI0 or I1 to CLKHold Time, HIGH or LOWI0 or I1 to CLKOutput Disable TimeOutput Enable TimeClock Pulse Width HIGH or LOW(3)Condition(1)CL = 50pFRL = 500ΩMin.(2)2.02.02.52.04.02.01.51.55.5Max.6.06.0————6.06.0—Mil.Min.(2)2.02.02.82.04.52.01.51.56.0Max.7.07.0————6.07.0—FCT520DT/521DTCom'l.Min.(2)2.02.01.51.02.01.01.51.53.0Max.5.24.8————4.84.0—Mil.Min.(2)—————————Max.—————————Unitnsnsnsnsnsnsnsnsns2619 tbl 08

NOTES:1.See test circuit and waveforms.

2.Minimum units are guaranteed but not tested on Propagation Delays.

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IDT29FCT520AT/BT/CT/DT, 521AT/BT/CT/DTMULTILEVEL PIPELINE REGISTERS

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TEST CIRCUITS AND WAVEFORMSTEST CIRCUITS FOR ALL OUTPUTS

VCC500ΩVINPulseGeneratorRTD.U.T.50pFCL2619 drw 05

SWITCH POSITIONTest7.0VSwitchOpen DrainDisable LowEnable LowAll Other TestsClosedOpenVOUT500ΩDEFINITIONS:2619 lnk 09CL=Load capacitance: includes jig and probe capacitance.

RT =Termination resistance: should be equal to ZOUT of the Pulse

Generator.

SET-UP, HOLD AND RELEASE TIMESPULSE WIDTH

DATAINPUTTIMING INPUTASYNCHRONOUS CONTROLPRESETCLEARETC.SYNCHRONOUS CONTROLPRESETCLEARCLOCK ENABLEETC.tSUtHtREM3V1.5V0V3V1.5V0V3V1.5V0V3V1.5V0V2619 drw 06

LOW-HIGH-LOWPULSEtWHIGH-LOW-HIGHPULSE1.5V1.5V2619 drw 07

tSUtHPROPAGATION DELAY

3V1.5V0VVOH1.5VVOL3V1.5V0V2619 drw 08

ENABLE AND DISABLE TIMES

ENABLEDISABLE3VCONTROLINPUTtPZLOUTPUTNORMALLYLOWOUTPUTNORMALLYHIGHSWITCHCLOSEDtPZHSWITCHOPEN1.5V0V0V2619 drw 09

SAME PHASEINPUT TRANSITIONtPLHOUTPUTtPLHOPPOSITE PHASEINPUT TRANSITIONtPHLtPHL1.5VtPLZ3.5V1.5VtPHZ0.3VVOH0.3V0V3.5VVOLNOTES:

1.Diagram shown for input Control Enable-LOW and input Control Disable-HIGH

2.Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns

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IDT29FCT520AT/BT/CT/DT, 521AT/BT/CT/DTMULTILEVEL PIPELINE REGISTERS

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ORDERING INFORMATION

29FCTXXXTemperatureFamilyRangeXXDevice TypeXPackageXProcessBlankBPDLSOPYEQ520AT521AT520BT521BT520CT521CT520DT521DTBlank25474Commercial MIL-STD-883, Class BPlastic DIPCERDIPLeadless Chip CarrierSmall Outline ICShrink Small Outline PackageCERPACKQuarter-size Small Outline PackageMultilevel Pipeline RegisterMultilevel Pipeline RegisterHigh DriveBalanced Drive-55°C to +125°C0°C to +70°C2619 drw 10

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