Method of fabricating a vertical quadruple conduct

专利名称：Method of fabricating a vertical quadruple

conduction channel insulated gate transistor

发明人：Thomas Skotnicki,Emmanuel Josse申请号：US10114672申请日：20020402公开号：US06746923B2公开日：20040608

专利附图：

摘要：The vertical insulated gate transistor includes, on a semiconductor substrate, avertical pillar incorporating one of the source and drain regions at the top, a gatedielectric layer situated on the flanks of the pillar and on the top surface of the

substrate, and a semiconductor gate resting on the gate dielectric layer. The other of thesource and drain regions is in the bottom part of the pillar PIL and the insulated gateincludes an isolated external portion resting on the flanks of the pillar and an isolatedinternal portion situated inside the pillar between the source and drain regions. Theisolated internal portion is separated laterally from the isolated external portion by twoconnecting semiconductor regions PL, PLextending between the source and drainregions, and forming two very fine pillars.

申请人：STMICROELECTRONICS S.A.

代理机构：Fleit, Kain, Gibbons, Gutman, Bongini & Bianco P.L.

代理人：Lisa K. Jorgenson,Jon A. Gibbons

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