CY62147DV30
4-Mbit (256K x 16) Static RAM
Features
•Temperature Ranges—Industrial: –40°C to +85°C—Automotive-A: –40°C to +85°C—Automotive-E: –40°C to +125°C•Very high speed: 45 ns
•Wide voltage range: 2.20V–3.60V
•Pin-compatible with CY62147CV25, CY62147CV30, and CY62147CV33•Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz— Typical active current: 8 mA @ f = fmax •Ultra low standby power
•Easy memory expansion with CE, and OE features•Automatic power-down when deselected•CMOS for optimum speed/power
•Available in Pb-free and non Pb-free 48-ball VFBGA and non Pb-free 44-pin TSOPII•Byte power-down feature
vanced circuit design to provide ultra-low active current. Thisis ideal for providing More Battery Life™ (MoBL®) in portableapplications such as cellular telephones. The device also hasan automatic power-down feature that significantly reducespower consumption. The device can also be put into standbymode reducing power consumption by more than 99% whendeselected (CE HIGH or both BLE and BHE are HIGH). Theinput/output pins (I/O0 through I/O15) are placed in a high-im-pedance state when: deselected (CE HIGH), outputs are dis-abled (OE HIGH), both Byte High Enable and Byte Low Enableare disabled (BHE, BLE HIGH), or during a write operation (CELOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), iswritten into the location specified on the address pins (A0through A17). If Byte High Enable (BHE) is LOW, then datafrom I/O pins (I/O8 through I/O15) is written into the locationspecified on the address pins (A0 through A17).
Reading from the device is accomplished by taking ChipEnable (CE) and Output Enable (OE) LOW while forcing theWrite Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,then data from the memory location specified by the addresspins will appear on I/O0 to I/O7. If Byte High Enable (BHE) isLOW, then data from memory will appear on I/O8 to I/O15. Seethe truth table at the back of this data sheet for a completedescription of read and write modes.
The CY62147DV30 is available in a 48-ball VFBGA, 44 PinTSOPII packages.
Functional Description[1]
The CY62147DV30 is a high-performance CMOS static RAMorganized as 256K words by 16 bits. This device features ad-
Logic Block Diagram
A10A9A8A7A6A5A4A3A2A1A0
DATA IN DRIVERS
ROW DECODER 256K x 16RAM Array
SENSE AMPSI/O0–I/O7I/O8–I/O15
COLUMN DECODER
BHEWECEOEBLE
A11A12A13A14A15A16CE
Power-DownCircuit
BHEBLE
Note:
1.For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
A17CypressSemiconductorCorporationDocument #: 38-05340 Rev. *F
•198 Champion Court•
SanJose,CA 95134-1709•408-943-2600
Revised August 31, 2006
[+] Feedb
元器件交易网www.cecb2b.com
Pin Configuration[2, 3, 4]
CY62147DV30
44 TSOP II (Top View)
VFBGA (Top View)
1BLEI/O8I/O9VSSVCCI/O14I/O15NC
2OEBHEI/O10I/O113A0A3A5A17
4A1A4A6A7A16A15A13A10
5A2CEI/O1I/O3I/O4I/O5WEA11
6NCI/O0I/O2VccVssI/O6I/O7NC
ABCDEFGH
A4A3A2A1A0CEI/O0I/O1I/O2I/O3VCCVSSI/O4I/O5I/O6I/O7WEA17A16A15A14A13
12345678910111213141516171819202122
44434241403938373635343332313029282726252423
I/O12 DNUI/O13NCA8
A14A12A9
A5A6A7OEBHEBLEI/O15I/O14I/O13I/O12VSSVCCI/O11I/O10I/O9I/O8NCA8A9A10A11A12
Product Portfolio
Power Dissipation
ProductCY62147DV30LLCY62147DV30LLCY62147DV30LCY62147DV30LLCY62147DV30LL
RangeIndustrialIndustrialAuto-EIndustrialAuto-A
2.2V
3.0
3.6
70
1.5
3
8
15
2
VCC Range (V)Min.2.2V2.2V
Typ.[5]3.03.0
Max.3.63.6
4555Speed (ns)
Operating ICC (mA)f = 1MHzTyp.[5]1.51.5
Max.33
f = fmaxTyp.[5]108
Max.2015
Standby ISB2
(µA)Typ.[5]22
Max.882588
Notes:
2.NC pins are not internally connected on the die.
3.DNU pins have to be left floating or tied to VSS to ensure proper application.
4.Pins H1, G2, and H6 in the VFBGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively.
5.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05340 Rev. *FPage 2 of 12
[+] Feedb
元器件交易网www.cecb2b.com
Maximum Ratings
(Above which the useful life may be impaired. For user guide-lines, not tested.)
Storage Temperature .................................–65°C to +150°CAmbient Temperature with
Power Applied.............................................–55°C to +125°CSupply Voltage to Ground
Potential......................................–0.3V to + VCC(MAX) + 0.3VDC Voltage Applied to Outputs
in High-Z State[6,7]..........................–0.3V to VCC(MAX) + 0.3VDC Input Voltage
[6,7]
CY62147DV30
Output Current into Outputs (LOW).............................20 mAStatic Discharge Voltage........................................... >2001V(per MIL-STD-883, Method 3015)
Latch-up Current......................................................>200 mA
Operating Range
DeviceCY62147DV30LCY62147DV30LL
RangeIndustrial
AmbientTemperature
[TA][9]–40°C to +85°C
VCC2.20Vto3.60V
Automotive-E–40°C to +125°CAutomotive-A–40°C to +85°C
.....................–0.3V to VCC(MAX) + 0.3V
Electrical Characteristics (Over the Operating Range)
–45
ParameterDescriptionVOHVOLVIHVILIIX
Test Conditions
VCC = 2.20V VCC = 2.70V VCC = 2.20VVCC = 2.70V
1.82.2–0.3–0.3
Ind’lAuto-A[9]Auto-E[9]IOZ
Output Leakage Current
GND < VO < VCC,Output Disabled
Ind’lAuto-A[9]Auto-E[9]VCC = VCCmaxIOUT = 0 mACMOS levels
101.5
2038
–1
+1
–1
Min.Typ.[5]2.02.4
0.40.4VCC + 0.3VVCC + 0.3V
0.60.8+1
1.82.2–0.3–0.3–1–1–4–1–1–4
81.5
Max.
Output HIGH IOH = –0.1 mAVoltage
IOH = –1.0 mAOutput LOW IOL = 0.1 mAVoltage
IOL = 2.1 mAInput HIGH VoltageInput LOW Voltage
VCC = 2.2V to 2.7VVCC= 2.7V to 3.6VVCC = 2.2V to 2.7VVCC= 2.7V to 3.6V
2.02.4
0.40.4VCC + 0.3VVCC + 0.3V
0.60.8+1+1+4+1+1+41538825
–55/–70
Min.Typ.[5]
Max.
UnitVVVVVVVVµAµAµAµAµAµAmAmAµA
Input Leakage GND < VI < VCCCurrent
ICC
VCC Operating f = fMAX = 1/tRCSupply
f = 1 MHz
Current Automatic CEPower-Down Current — CMOS Inputs
ISB1
Ind’lLLCE > VCC−0.2V,
VIN>VCC–0.2V, VIN<0.2V) Auto-A[9]LL
f = fMAX (Address and Data Only),Auto-E[9]L f = 0 (OE, WE, BHE and BLE), VCC = 3.60V
Ind’l
LL
Auto-A[9]LLAuto-E[9]L
ISB2
Automatic CE CE > VCC – 0.2V,Power-Down VIN > VCC – 0.2V or Current — VIN < 0.2V,CMOS Inputsf = 0, VCC = 3.60V
88825
µA
Notes:
6.VIL(min.) = –2.0V for pulse durations less than 20 ns.
7.VIH(max.) = VCC + 0.75V for pulse durations less than 20 ns.
8.Full device AC operation assumes a 100-µs ramp time from 0 to VCC(min) and 200-µs wait time after VCC stabilization.9.Auto-A is available in –70 and Auto-E is available in –55.
Document #: 38-05340 Rev. *FPage 3 of 12
[+] Feedb
元器件交易网www.cecb2b.com
Capacitance (for all packages)[10]
Parameter
CINCOUT
Description
Input CapacitanceOutput Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,VCC = VCC(typ)
CY62147DV30
Max.1010
UnitpFpF
Thermal Resistance[10]
Parameter
ΘJAΘJC
Description
Thermal Resistance (Junction to Ambient)Thermal Resistance (Junction to Case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board
VFBGA728.86
TSOP II75.138.95
Unit°C/W°C/W
AC Test Loads and Waveforms[10]
VCCOUTPUT50 pFINCLUDINGJIG ANDSCOPE
R1
VCC
R2
10%GND
Rise Time = 1 V/ns
ALL INPUT PULSES
90%90%
10%
Fall Time = 1 V/ns
Equivalentto:
THÉ VENINEQUIVALENT
RTH
OUTPUTV
3.0V110315546451.75
UnitΩΩΩV
Parameters
R1R2RTHVTH
2.50V166671538580001.20
Data Retention Characteristics (Over the Operating Range)
ParameterVDRICCDR
Description
VCC for Data RetentionData Retention Current
VCC= 1.5V
CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2VL (Auto-E)LL (Ind’l/Auto-A)
Conditions
Min.1.5
156
Typ.[5]Max.
UnitVµA
tCDR[10]tR[12]Chip Deselect to Data Retention Time
Operation Recovery Time
0tRC
nsns
Data Retention Waveform[13]
VCCCE orBHE.BLE
VCC(min)
tCDR
DATA RETENTION MODE
VDR>1.5 V
VCC(min)
tR
Notes:
10.Tested initially and after any design or process changes that may affect these parameters.11.Test condition for the 45-ns part is a load capacitance of 30 pF.
12.Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
13.BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05340 Rev. *FPage 4 of 12
[+] Feedb
元器件交易网www.cecb2b.com
CY62147DV30
Switching Characteristics Over the Operating Range[14]
45 ns[11]ParameterRead CycletRCtAAtOHAtACEtDOEtLZOEtHZOEtLZCEtHZCEtPUtPDtDBEtLZBEtHZBE
Write Cycle[17]tWCtSCEtAWtHAtSAtPWEtBWtSDtHDtHZWEtLZWE
Write Cycle TimeCE LOW to Write EndAddress Set-up to Write EndAddress Hold from Write EndAddress Set-up to Write StartWE Pulse Width
BLE/BHE LOW to Write EndData Set-up to Write EndData Hold from Write EndWE LOW to High-Z[15, 16]WE HIGH to Low-Z[15]10454040003540250
15
10554040004040250
20
10706060004560300
25
nsnsnsnsnsnsnsnsnsnsns
Read Cycle TimeAddress to Data Valid
Data Hold from Address ChangeCE LOW to Data ValidOE LOW to Data ValidOE LOW to LOW Z[15]OE HIGH to High Z[15, 16]CE LOW to Low Z[15]CE HIGH to High Z[15, 16]CE LOW to Power-UpCE HIGH to Power-DownBLE/BHE LOW to Data ValidBLE/BHE LOW to Low Z[15]BLE/BHE HIGH to HIGH Z[15, 16]10
15
0
4545
10
20
10
20
0
5555
10
25
5
15
10
20
0
7070
10
4525
5
20
10
25
45
45
10
5525
5
25
55
55
10
7035
70
70
nsnsnsnsnsnsnsnsnsnsnsnsnsns
Description
Min.
Max.
Min.
55 ns
Max.
Min.
70 ns
Max.
Unit
Notes:
14.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
15.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
16.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.
17.The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05340 Rev. *FPage 5 of 12
[+] Feedb
元器件交易网www.cecb2b.com
CY62147DV30
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[18, 19]
tRC
ADDRESS
tOHA
DATA OUT
PREVIOUS DATA VALID
tAA
DATA VALID
Read Cycle No. 2 (OE Controlled)[19, 20]
ADDRESS
CEtACEOEtDOEBHE/BLEtLZOEtRCtPDtHZCEtHZOEtHZBEtDBEtLZBEDATA OUTHIGH IMPEDANCEtLZCEVCCSUPPLYCURRENTtPU50%50%ICCISBDATA VALIDHIGH IMPEDANCENotes:
18.The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.19.WE is HIGH for read cycle.
20.Address valid prior to or coincident with CE and BHE, BLE transition LOW.
Document #: 38-05340 Rev. *FPage 6 of 12
[+] Feedb
元器件交易网www.cecb2b.com
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[17, 21, 22]
tWC
ADDRESS
tSCE
CE
tAW
WE
tSA
tPWE
tHA
CY62147DV30
BHE/BLE
tBW
OE
tSD
DATA I/O
NOTE23
tHZOE
DATAIN
tHD
Write Cycle No. 2 (CE Controlled)[17, 21, 22]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tPWE
tHA
WE
BHE/BLE
tBW
OE
tSD
DATAI/O
NOTE23
tHZOE
Notes:
21.Data I/O is high impedance if OE = VIH.
22.If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state.23.During this period, the I/Os are in output state and input signals should not be applied.
tHD
DATAIN
Document #: 38-05340 Rev. *FPage 7 of 12
[+] Feedb
元器件交易网www.cecb2b.com
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[22]
tWC
ADDRESS
tSCE
CE
tBW
CY62147DV30
BHE/BLE
tAW
tSA
WE
tHA
tPWE
tSD
DATAI/O
NOTE 23
tHZWE
DATAIN
tHD
tLZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[22]
tWC
ADDRESS
CE
tSCEtAWBHE/BLEtSAWEtHZWE
tHAtBWtPWEtSDDATAINtLZWE
tHD
DATA I/ONOTE 23
Document #: 38-05340 Rev. *FPage 8 of 12
[+] Feedb
元器件交易网www.cecb2b.com
CY62147DV30
Truth Table
CEHXLLLLLLLLL
WEXXHHHHHHLLL
OEXXLLLHHHXXX
BHEXHLHLLHLLHL
BLEXHLLHLLHLLH
Inputs/OutputsHigh ZHigh Z
Data Out (I/OO–I/O15)Data Out (I/OO–I/O7);I/O8–I/O15 in High ZData Out (I/O8–I/O15);I/O0–I/O7 in High ZHigh ZHigh ZHigh Z
Data In (I/OO–I/O15)Data In (I/OO–I/O7);I/O8–I/O15 in High ZData In (I/O8–I/O15);I/O0–I/O7 in High Z
Mode
Deselect/Power-DownDeselect/Power-DownReadReadRead
Output DisabledOutput DisabledOutput DisabledWriteWriteWrite
Power
Standby (ISB)Standby (ISB)Active (ICC)Active (ICC)Active (ICC)Active (ICC)Active (ICC)Active (ICC)Active (ICC)Active (ICC)Active (ICC)
Ordering Information
Speed(ns)4555
Ordering CodeCY62147DV30LL-45BVXICY62147DV30LL-45ZSXICY62147DV30LL-55BVICY62147DV30LL-55BVXICY62147DV30LL-55ZSXICY62147DV30L-55BVXECY62147DV30L-55ZSXE70
CY62147DV30LL-70BVICY62147DV30LL-70BVXA
Package Diagram
Package Type
Operating RangeIndustrialIndustrial
51-8515048-ball (6 mm × 8mm × 1 mm) VFBGA (Pb-free)51-8508744-pin TSOP II (Pb-free)
51-8515048-ball (6 mm × 8mm × 1 mm) VFBGA
48-ball (6 mm × 8mm × 1 mm) VFBGA (Pb-free)
51-8508744-pin TSOP II (Pb-free)
51-8515048-ball (6 mm × 8mm × 1 mm) VFBGA (Pb-free)51-8508744-pin TSOP II (Pb-free)
51-8515048-ball (6 mm × 8mm × 1 mm) VFBGA
48-ball (6 mm × 8mm × 1 mm) VFBGA (Pb-free)
Automotive-EIndustrialAutomotive-A
Document #: 38-05340 Rev. *FPage 9 of 12
[+] Feedb
元器件交易网www.cecb2b.com
CY62147DV30
Package Diagram
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)TOPVIEWA1CORNER123456ABC01.0D±00E.8FGHAB6.00±0.10.XCA5M5250..050C.0±1021..00SEATINGPLANE.XCAXMA6M20.00.1Document #: 38-05340 Rev. *FBOTTOMVIEWA1CORNERØ0.05MCØ0.25MCABØ0.30±0.05(48X)654321ABC507.10D.502±.05E0.852F6.2GHA1.8750.753.75B6.00±0.100.15(4X)51-85150-*DPage 10 of 12
[+] Feedb
元器件交易网www.cecb2b.com
Package Diagram (continued)
44-Pin TSOP II (51-85087)
CY62147DV30
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product andcompany names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05340 Rev. *FPage 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to beused for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize itsproducts for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypressproducts in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedb
元器件交易网www.cecb2b.com
Document History Page
Document Title:CY62147DV30 MoBL® 4-Mbit (256K x 16) Static RAMDocument Number: 38-05340REV.***A*B
ECN NO.Issue Date127481131010213252
06/17/0301/23/04See ECN
Orig. of ChangeHRTCBDAJU
New Data Sheet
Changed from Advance to Preliminary
Description of Change
CY62147DV30
Changed from Preliminary to FinalAdded 70 ns speed bin
Modified footnote 7 to include ramp time and wait timeModified input and output capacitance values to 10 pFModified Thermal Resistance values on page 4
Added “Byte power-down feature” in the features sectionModified Ordering Information for Pb-free partsModified ordering information for 70-ns Speed Bin
Added 45-ns Speed Bin in AC, DC and Ordering Information tablesAdded Footnote #10 on page #4
Added Pb-free package ordering information on page # 9
Changed 44-lead TSOP-II package name on page 11 from Z44 to ZS44Standardized Icc values across ‘L’ and ‘LL’ binsAdded Automotive product informationAdded Automotive-A rangeAdded note# 9 on page# 3
Updated ordering information table
*C*D
257349316039
See ECNSee ECN
PCIPCI
*E*F
330365498575
See ECNSee ECN
AJUNXR
Document #: 38-05340 Rev. *FPage 12 of 12
[+] Feedb
因篇幅问题不能全部显示，请点此查看更多更全内容