ADC082S101

ADC082S101

2 Channel, 500 ksps to 1 Msps, 8-Bit A/D Converter

General Description

The ADC082S101 is a low-power, two-channel CMOS 8-bitanalog-to-digital converter with a high-speed serial interface.Unlike the conventional practice of specifying performance ata single sample rate only, the ADC082S101 is fully specifiedover a sample rate range of 500 ksps to 1 Msps. The con-verter is based on a successive-approximation register archi-tecture with an internal track-and-hold circuit. It can beconfigured to accept one or two input signals at inputs IN1and IN2.

The output serial data is straight binary, and is compatible withseveral standards, such as SPI™, QSPI™, MICROWIRE,and many common DSP serial interfaces.

The ADC082S101 operates with a single supply that canrange from +2.7V to +5.25V. Normal power consumption us-ing a +3V or +5V supply is 3.2 mW and 9.6 mW, respectively.The power-down feature reduces the power consumption tojust 0.12 µW using a +3V supply, or 0.35 µW using a +5Vsupply.

The ADC082S101 is packaged in an 8-lead MSOP package.Operation over the industrial temperature range of −40°C to+85°C is guaranteed.

Features

■■■■

Specified over a range of sample rates.Two input channels

Variable power management

Single power supply with 2.7V - 5.25V range

Key Specifications

■■■■■

DNLINLSNR

Power Consumption—3V Supply—5V Supply

±0.10 LSB (typ)± 0.13 LSB (typ)

49.6 dB (typ)

3.2 mW (typ)9.6 mW (typ)

Applications

■Portable Systems

■Remote Data Acquisition

■Instrumentation and Control Systems

Pin-Compatible Alternatives by Resolution and Speed

All devices are fully pin and function compatible.

Resolution

12-bit10-bit8-bit

50 to 200 kspsADC122S021ADC102S021ADC082S021

Specified for Sample Rate Range of:

200 to 500 kspsADC122S051ADC102S051ADC082S051

500 ksps to 1 Msps

ADC122S101ADC102S101ADC082S101

Connection Diagram

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Ordering Information

Order Code

ADC082S101CIMMADC082S101CIMMXADC082S101EVAL

Temperature Range−40°C to +85°C−40°C to +85°C

Description8-Lead MSOP Package

8-Lead MSOP Package, Tape & Reel

Evaluation Board

Top MarkX22CX22C

TRI-STATE® is a trademark of National Semiconductor CorporationQSPI™ and SPI™ are trademarks of Motorola, Inc.

© 2010 National Semiconductor Corporation201254www.national.com

ADC082S101Block Diagram

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Pin Descriptions and Equivalent Circuits

Pin No.ANALOG I/O

5,4

DIGITAL I/O

8761

POWER SUPPLY

23

VAGND

Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source andbypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within1 cm of the power pin.The ground return for the die.

SCLKDOUTDINCSDigital clock input. This clock directly controls the conversion and readout processes.Digital data output. The output samples are clocked out of this pin on falling edges of theSCLK pin.

Digital data input. The ADC082S101's Control Register is loaded through this pin on risingedges of the SCLK pin.

Chip select. On the falling edge of CS, a conversion process begins. Conversionscontinue as long as CS is held low.IN1 and IN2

Analog inputs. These signals can range from 0V to VA.

Symbol

Description

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ADC082S101Absolute Maximum Ratings (Note 1, Note

2)

If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Analog Supply Voltage VAVoltage on Any Pin to GND

Input Current at Any Pin (Note 3)Package Input Current (Note 3)Power Consumption at TA = 25°CESD Susceptibility (Note 5) Human Body Model Machine ModelJunction TemperatureStorage Temperature

−0.3V to 6.5V−0.3V to VA +0.3V

±10 mA±20 mASee (Note 4)  2500V 250V+150°C

−65°C to +150°C

Operating Ratings

Operating Temperature Range

(Note 1, Note 2)

−40°C ≤ TA ≤ +85°C+2.7V to +5.25V

o−0.3V to VA

50 kHz to 16 MHz

0V to VA

VA Supply VoltageoooDigital Input Pins Voltage RangeClock FrequencyAnalog Input Voltage

Package Thermal Resistance

Package8-lead MSOP

θJA250°C / W

Sldering prcess must cmply with NatinalSemiconductor's Reflow Temperature Profile specifications.Refer to www.national.com/packaging.(Note 6)

ADC082S101 Converter Electrical Characteristics

(Note 9)

The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to 1 Msps,CL = 50 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.

Parameter

Conditions

Typical

Limits(Note 7)

8±0.4±0.4±0.7±0.3±0.7±0.3

Units

Symbol

STATIC CONVERTER CHARACTERISTICS INLDNLVOFFOEMFSEFSEM

Resolution with No Missing CodesIntegral Non-LinearityDifferential Non-LinearityOffset Error

Channel to Channel Offset Error MatchFull-Scale Error

±0.13±0.10+0.530.0050.520.005

BitsLSB (max)LSB (max)LSB (max)LSB (max)LSB (max)LSB (max)

Channel to Channel Full-Scale Error Match

VA = +2.7V to 5.25V

fIN = 40.3 kHz, −0.02 dBFSVA = +2.7V to 5.25V

fIN = 40.3 kHz, −0.02 dBFSVA = +2.7V to 5.25V

fIN = 40.3 kHz, −0.02 dBFSVA = +2.7V to 5.25V

fIN = 40.3 kHz, −0.02 dBFSVA = +2.7V to 5.25V

fIN = 40.3 kHz, −0.02 dBFSVA = +5.25VfIN = 40.3 kHz

VA = +5.25V

fa = 40.161 kHz, fb = 41.015 kHzVA = +5.25V

fa = 40.161 kHz, fb = 41.015 kHzVA = +5VVA = +3V

DYNAMIC CONVERTER CHARACTERISTICSSINADSNRTHDSFDRENOB

Signal-to-Noise Plus Distortion RatioSignal-to-Noise RatioTotal Harmonic DistortionSpurious-Free Dynamic RangeEffective Number of BitsChannel-to-Channel Crosstalk

Intermodulation Distortion, Second OrderTerms

Intermodulation Distortion, Third OrderTerms

-3 dB Full Power Bandwidth

49.649.6−75677.9−73−78−73118

49.149.2−62637.9

dB (min)dB (min)dB (max)dB (min)Bits (min)dBdBdBMHzMHz

IMD

FPBW

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ADC082S101SymbolParameterConditionsTypical

Limits(Note 7)

Units

ANALOG INPUT CHARACTERISTICSVINIDCLCINA

Input RangeDC Leakage CurrentInput Capacitance

Track ModeHold ModeVA = +5.25VVA = +3.6V

VIN = 0V or VA

ISOURCE = 200 µAISOURCE = 1mAISINK = 200 µAISINK = 1 mA

0 to VA

333 2VA − 0.03VA − 0.10.030.1±0.012

2.4 2.10.8 ±104VA − 0.5

0.4 ±14±1

VµA (max)pFpFV (min)V (min)V (max)µA (max)pF (max)V (min)VV (max)VµA (max)pF (max)

DIGITAL INPUT CHARACTERISTICSVIHVILIINCIND

Input High VoltageInput Low VoltageInput Current

Digital Input Capacitance

DIGITAL OUTPUT CHARACTERISTICSVOHVOLIOZH, IOZLCOUT

Output High VoltageOutput Low Voltage

TRI-STATE® Leakage CurrentTRI-STATE® Output CapacitanceOutput Coding

Straight (Natural) Binary

2.75.252.41.2

V (min)V (max)mA (max)mA (max)

nAnA

12.64.3

mW (max)mW (max)

µWµW

8165001133070316

MHz (min)MHz (max)ksps (min)Msps (max)SCLK cycles% (min)% (max)SCLK cyclesSCLK cycles

POWER SUPPLY CHARACTERISTICS (CL = 10 pF)VA

Supply Voltage

1.820.92002009.63.20.350.12

IA

VA = +5.25V,

Supply Current, Normal Mode (Operational,fSAMPLE = 1 Msps, fIN = 40 kHzCS low)VA = +3.6V,

fSAMPLE = 1 Msps, fIN = 40 kHz

VA = +5.25V,fSAMPLE = 0 kspsVA = +3.6V,fSAMPLE = 0 kspsVA = +5.25VVA = +3.6VVA = +5.25VVA = +3.6V

Supply Current, Shutdown (CS high)PD

Power Consumption, Normal Mode(Operational, CS low)Power Consumption, Shutdown (CS high)AC ELECTRICAL CHARACTERISTICSfSCLKfStCONVDCtACQ

Clock FrequencySample RateConversion TimeSCLK Duty Cycle

Track/Hold Acquisition TimeThroughput Time

(Note 8)(Note 8)

fSCLK = 16 MHzFull-Scale Step Input

Acquisition Time + ConversionTime

50

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ADC082S101ADC082S101 Timing Specifications

The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to 1 Msps,CL = 50 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.SymboltCSUtCLHtENtACCtSUtHtCHtCL

Parameter

Setup Time SCLK High to CS Falling EdgeHold time SCLK Low to CS Falling EdgeDelay from CS Until DOUT activeData Access Time after SCLK Falling EdgeData Setup Time Prior to SCLK Rising EdgeData Valid SCLK Hold TimeSCLK High Pulse WidthSCLK Low Pulse Width

(Note 10)(Note 10)

Output Falling

tDIS

CS Rising Edge to DOUT High-ImpedanceOutput Rising

VA = +3.0VVA = +5.0VVA = +3.0VVA = +5.0VConditions

VA = +3.0VVA = +5.0VVA = +3.0VVA = +5.0VVA = +3.0VVA = +5.0VVA = +3.0VVA = +5.0V

Typical−3.5−0.5+4.5+1.5+4+2+16.5+15+3+3

Limits(Note 7)101030301010

Unitsns (min)ns (min)ns (max)ns (max)ns (min)ns (min)

0.5 x tSCLK0.3 x tSCLKns (min)0.5 x tSCLK0.3 x tSCLKns (min)

1.71.21.01.0

20

ns (max)

Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device isfunctional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteedspecifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed testconditions.

Note 2:All voltages are measured with respect to GND = 0V, unless otherwise specified.

Note 3:When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 20mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The AbsoluteMaximum Rating specification does not apply to the VA pin. The current into the VA pin is limited by the Analog Supply Voltage specification.

Note 4:The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, thejunction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The valuesfor maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are drivenbeyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

Note 5:Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms.Note 6:Reflow temperature profiles are different for lead-free and non-lead-free packages.Note 7:Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 8:This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified underOperating Ratings.

Note 9:The min/max specification limits are guaranteed by design, test, or statistical analysis.

Note 10:Clock may be either high or low when CS is asserted as long as setup and hold times tCSU and tCLH are strictly observed.

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ADC082S101Timing Diagrams

ADC082S101 Operational Timing Diagram

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Timing Test Circuit

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ADC082S101 Serial Timing Diagram

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SCLK and CS Timing Parameters20125450

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ADC082S101Specification Definitions

ACQUISITION TIME is the time required to acquire the inputvoltage. That is, it is time required for the hold capacitor tocharge up to the input voltage.

APERTURE DELAY is the time between the fourth fallingSCLK edge of a conversion and the time when the input signalis acquired or held for conversion.

CONVERSION TIME is the time required, after the input volt-age is acquired, for the ADC to convert the input voltage to adigital word.

CROSSTALK is the coupling of energy from one channel intothe other channel, or the amount of signal energy from oneanalog input that appears at the measured analog input.DIFFERENTIAL NON-LINEARITY (DNL) is the measure ofthe maximum deviation from the ideal step size of 1 LSB.DUTY CYCLE is the ratio of the time that a repetitive digitalwaveform is high to the total time of one period. The specifi-cation here refers to the SCLK.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVEBITS) is another method of specifying Signal-to-Noise andDistortion or SINAD. ENOB is defined as (SINAD − 1.76) /6.02 and says that the converter is equivalent to a perfectADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops 3 dBbelow its low frequency value for a full scale input.

FULL SCALE ERROR (FSE) is a measure of how far the lastcode transition is from the ideal 1½ LSB below VREF+ and isdefined as:

VFSE = Vmax + 1.5 LSB – VREF+

where Vmax is the voltage at which the transition to the maxi-mum code occurs. FSE can be expressed in Volts, LSB orpercent of full scale range.

GAIN ERROR is the deviation of the last code transition(111...110) to (111...111) from the ideal (VREF − 1.5 LSB), af-ter adjusting for offset error.

INTEGRAL NON-LINEARITY (INL) is a measure of the de-viation of each individual code from a line drawn from negativefull scale (½ LSB below the first code transition) through pos-itive full scale (½ LSB above the last code transition). Thedeviation of any given code from this straight line is measuredfrom the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation ofadditional spectral components as a result of two sinusoidalfrequencies being applied to the ADC input at the same time.It is defined as the ratio of the power in the second and thirdorder intermodulation products to the sum of the power in bothof the original frequencies. IMD is usually expressed in dB.MISSING CODES are those output codes that will never ap-pear at the ADC outputs. The ADC082S101 is guaranteed notto have any missing codes.

OFFSET ERROR is the deviation of the first code transition(000...000) to (000...001) from the ideal (i.e. GND + 0.5 LSB).SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed indB, of the rms value of the input signal at the converter outputto the rms value of the sum of all other spectral componentsbelow one-half the sampling frequency, not including d.c. orharmonics included in the THD specification.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D orSINAD) Is the ratio, expressed in dB, of the rms value of theinput signal to the rms value of all of the other spectral com-ponents below half the clock frequency, including harmonicsbut excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-ence, expressed in dB, between the rms values of the inputsignal and the peak spurious signal where a spurious signalis any signal present in the output spectrum that is not presentat the input, excluding d.c.

TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-pressed in dB or dBc, of the rms total of the first five harmoniccomponents at the output to the rms level of the input signalfrequency as seen at the output. THD is calculated as

where Af1 is the RMS power of the input frequency at the out-put and Af2 through Af6 are the RMS power in the first 5harmonic frequencies. Accurate THD measurement requiresa spectrally pure sine wave (monotone) at the ADC input.THROUGHPUT TIME is the minimum time required betweenthe start of two successive conversion. It is the acquisitiontime plus the conversion and read out times. In the case ofthe ADC082S101, this is 16 SCLK periods.

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ADC082S101Typical Performance Characteristics

MHz, fIN = 40.3 kHz unless otherwise stated.

DNL - VA = 3.0V

TA = +25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 8 MHz to 16

INL - VA = 3.0V

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DNL - VA = 5.0VINL - VA = 5.0V

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DNL vs. SupplyINL vs. Supply

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ADC082S101DNL vs. Clock FrequencyINL vs. Clock Frequency

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DNL vs. Clock Duty CycleINL vs. Clock Duty Cycle

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DNL vs. TemperatureINL vs. Temperature

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ADC082S101SNR vs. SupplyTHD vs. Supply

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SNR vs. Clock FrequencyTHD vs. Clock Frequency

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SNR vs. Clock Duty CycleTHD vs. Clock Duty Cycle

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ADC082S101SNR vs. Input FrequencyTHD vs. Input Frequency

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SNR vs. TemperatureTHD vs. Temperature

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SFDR vs. SupplySINAD vs. Supply

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ADC082S101SFDR vs. Clock FrequencySINAD vs. Clock Frequency

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SFDR vs. Clock Duty CycleSINAD vs. Clock Duty Cycle

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SFDR vs. Input FrequencySINAD vs. Input Frequency

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ADC082S101SFDR vs. TemperatureSINAD vs. Temperature

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ENOB vs. SupplyENOB vs. Clock Frequency

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ENOB vs. Clock Duty CycleENOB vs. Input Frequency

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ADC082S101ENOB vs. TemperatureSpectral Response - 3V, 1 Msps

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Spectral Response - 5V, 1 MspsSpectral Response - 3V, 500 ksps

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Spectral Response - 5V, 500 kspsPower Consumption vs. Throughput

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ADC082S101Applications Information

1.0 ADC082S101 OPERATION

The ADC082S101 is a successive-approximation analog-to-digital converter designed around a charge-redistribution dig-ital-to-analog converter. Simplified schematics of the AD-C082S101 in both track and hold modes are shown inFigures 1, 2, respectively. In Figure 1, the ADC082S101 is intrack mode: switch SW1 connects the sampling capacitor toone of two analog input channels through the multiplexer, andSW2 balances the comparator inputs. The ADC082S101 is inthis state for the first three SCLK cycles after CS is broughtlow.

Figure 2 shows the ADC082S101 in hold mode: switch SW1connects the sampling capacitor to ground, maintaining the

sampled voltage, and switch SW2 unbalances the compara-tor. The control logic then instructs the charge-redistributionDAC to add fixed amounts of charge to the sampling capacitoruntil the comparator is balanced. When the comparator isbalanced, the digital word supplied to the DAC is the digitalrepresentation of the analog input voltage. The ADC082S101is in this state for the fourth through sixteenth SCLK cyclesafter CS is brought low.The time when CS is low is considered a serial frame. Eachof these frames should contain an integer multiple of 16 SCLKcycles, during which time a conversion is performed andclocked out at the DOUT pin and data is clocked into the DINpin to indicate the multiplexer address for the next conversion.

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FIGURE 1. ADC082S101 in Track Mode

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FIGURE 2. ADC082S101 in Hold Mode

2.0 USING THE ADC082S101

An ADC082S101 timing diagram and a serial interface timingdiagram for the ADC082S101 are shown in the Timing Dia-grams section. CS is chip select, which initiates conversionsand frames the serial data transfers. SCLK (serial clock) con-trols both the conversion process and the timing of serial data.DOUT is the serial data output pin, where a conversion resultis sent as a serial data stream, MSB first. Data to be writtento the ADC082S101's Control Register is placed at DIN, theserial data input pin. New data is written to DIN with eachconversion.

A serial frame is initiated on the falling edge of CS and endson the rising edge of CS. Each frame must contain an integermultiple of 16 rising SCLK edges. The ADC output data(DOUT) is in a high impedance state when CS is high and isactive when CS is low. Thus, CS acts as an output enable.Additionally, the device goes into a power down state whenCS is high and also between continuous conversion cycles.During the first 3 cycles of SCLK, the ADC is in the trackmode, acquiring the input voltage. For the next 13 SCLK cy-cles the conversion is accomplished and the data is clockedout, MSB first, starting with the 5th clock. If there is more thanone conversion in a frame, the ADC will re-enter the trackmode on the falling edge of SCLK after the N*16th rising edgeof SCLK, and re-enter the hold/convert mode on the N*16+4thfalling edge of SCLK, where \"N\" is an integer.

When CS is brought high, SCLK is internally gated off. If SCLKis stopped in the low state while CS is high, the subsequentfall of CS will generate a falling edge of the internal version ofSCLK, putting the ADC into the track mode. This is seen bythe ADC as the first falling edge of SCLK. If SCLK is stoppedwith SCLK high, the ADC enters the track mode on the firstfalling edge of SCLK after the falling edge of CS.15

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ADC082S101During each conversion, data is clocked into the ADC at DINon the first 8 rising edges of SCLK after the fall of CS. Foreach conversion, it is necessary to clock in the data indicatingthe input that is selected for the conversion after the currentone. See Tables 1, 2 and Table 3.

If CS and SCLK go low within the times defined by tCSU andtCLH, the rising edge of SCLK that begins clocking data in atDIN may or may not be one clock cycle later than expected.

It is, therefore, best to strictly observe the minimum tCSU andtCLH times given in the Timing Specifications.

There are no power-up delays or dummy conversions re-quired with the ADC082S101. The ADC is able to sample andconvert an input to full conversion immediately following pow-er up. The first conversion result after power-up will be that ofIN1.

TABLE 1. Control Register Bits

Bit 7 (MSB)DONTC

Bit 6DONTC

Bit 5ADD2

Bit 4ADD1

Bit 3ADD0

Bit 2DONTC

Bit 1DONTC

Bit 0DONTC

TABLE 2. Control Register Bit Descriptions

Bit #:7 - 6, 2 - 0

345

Symbol:DONTCADD0ADD1ADD2

Description

Don't care. The value of these bits do not affect the device.

These bits determine which input channel will be sampled and converted in thenext track/hold cycle. The mapping between codes and channels is shown inTable 3.

TABLE 3. Input Channel Selection

ADD2xxx

ADD1001

ADD001x

Input ChannelIN1 (Default)

IN2

Not allowed. The output signal at the DOUT pin

is indeterminate if ADD1 is high.

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ADC082S1013.0 ADC082S101 TRANSFER FUNCTION

The output format of the ADC082S101 is straight binary.Code transitions occur midway between successive integerLSB values. The LSB width for the ADC082S101 is VA/256.

The ideal transfer characteristic is shown in Figure 3. Thetransition from an output code of 0000 0000 to a code of 00000001 is at 1/2 LSB, or a voltage of VA/512. Other code tran-sitions occur at steps of one LSB.

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FIGURE 3. Ideal Transfer Characteristic

4.0 TYPICAL APPLICATION CIRCUIT

A typical application of the ADC082S101 is shown inFigure 4. Power is provided, in this example, by the NationalSemiconductor LP2950 low-dropout voltage regulator, avail-able in a variety of fixed and adjustable output voltages. Thepower supply pin is bypassed with a capacitor network locat-ed close to the ADC082S101. Because the reference for theADC082S101 is the supply voltage, any noise on the supply

will degrade device noise performance. To keep noise off thesupply, use a dedicated linear regulator for this device, orprovide sufficient decoupling from other circuitry to keep noiseoff the AC082S101 supply pin. Because of theADC082S101's low power requirements, it is also possible touse a precision reference as a power supply to maximize per-formance. The four-wire interface is shown connected to amicroprocessor or DSP.

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FIGURE 4. Typical Application Circuit

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ADC082S1015.0 ANALOG INPUTS

An equivalent circuit for one of the ADC082S101's input chan-nels is shown in Figure 5. Diodes D1 and D2 provide ESDprotection for the analog inputs. At no time should any inputgo beyond (VA + 300 mV) or (GND − 300 mV), as these ESDdiodes will begin conducting, which could result in erratic op-eration. For this reason, these ESD diodes should NOT beused to clamp the input signal.

The capacitor C1 in Figure 5 has a typical value of 3 pF, andis mainly the package pin capacitance. Resistor R1 is the onresistance of the multiplexer and track / hold switch, and istypically 500 ohms. Capacitor C2 is the ADC082S101 sam-pling capacitor and is typically 30 pF. The ADC082S101 willdeliver best performance when driven by a low-impedancesource to eliminate distortion caused by the charging of thesampling capacitance. This is especially important when us-ing the ADC082S101 to sample AC signals. Also importantwhen sampling dynamic signals is a band-pass or low-passfilter to reduce harmonics and noise, improving dynamic per-formance.

The user may trade off throughput for power consumption bysimply performing fewer conversions per unit time. The PowerConsumption vs. Sample Rate curve in the Typical Perfor-mance Curves section shows the typical power consumptionof the ADC082S101 versus throughput. To calculate the pow-er consumption, simply multiply the fraction of time spent inthe normal mode by the normal mode power consumption ,and add the fraction of time spent in shutdown mode multi-plied by the shutdown mode power dissipation.

7.1 Power Management

When the ADC082S101 is operated continuously in normalmode, the maximum throughput is fSCLK/16. Throughput maybe traded for power consumption by running fSCLK at its max-imum 16 MHz and performing fewer conversions per unittime, putting the ADC082S101 into shutdown mode betweenconversions. A plot of typical power consumption versusthroughput is shown in the Typical Performance Curves sec-tion. To calculate the power consumption for a given through-put, multiply the fraction of time spent in the normal mode bythe normal mode power consumption and add the fraction oftime spent in shutdown mode multiplied by the shutdownmode power consumption. Generally, the user will put the partinto normal mode and then put the part back into shutdownmode. Note that the curve of power consumption vs. through-put is nearly linear. This is because the power consumptionin the shutdown mode is so small that it can be ignored for allpractical purposes.

7.2 Power Supply Noise Considerations

The charging of any output load capacitance requires currentfrom the power supply, VA. The current pulses required fromthe supply to charge the output capacitance will cause voltagevariations on the supply. If these variations are large enough,they could degrade SNR and SINAD performance of the ADC.Furthermore, discharging the output capacitance when thedigital output goes from a logic high to a logic low will dumpcurrent into the die substrate, which is resistive. Load dis-charge currents will cause \"ground bounce\" noise in the sub-strate that will degrade noise performance if that current islarge enough. The larger is the output capacitance, the morecurrent flows through the die substrate and the greater is thenoise coupled into the analog channel, degrading noise per-formance.

To keep noise out of the power supply, keep the output loadcapacitance as small as practical. If the load capacitance isgreater than 50 pF, use a 100 Ω series resistor at the ADCoutput, located as close to the ADC output pin as practical.This will limit the charge and discharge current of the outputcapacitance and improve noise performance.

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FIGURE 5. Equivalent Input Circuit

6.0 DIGITAL INPUTS AND OUTPUTS

The ADC082S101's digital output DOUT is limited by, andcannot exceed, the supply voltage, VA. The digital input pinsare not prone to latch-up and, and although not recommend-ed, SCLK, CS and DIN may be asserted before VA withoutany latchup risk.

7.0 POWER SUPPLY CONSIDERATIONS

The ADC082S101 is fully powered-up whenever CS is low,and fully powered-down whenever CS is high, with one ex-ception: the ADC082S101 automatically enters power-downmode between the 16th falling edge of a conversion and the1st falling edge of the subsequent conversion (see TimingDiagrams).

The ADC082S101 can perform multiple conversions back toback; each conversion requires 16 SCLK cycles. The AD-C082S101 will perform conversions continuously as long asCS is held low.www.national.com18

ADC082S101Physical Dimensions inches (millimeters) unless otherwise noted

8-Lead MSOP

Order Number ADC082S101CIMM, ADC082S101CIMMX

NS Package Number P0MUA08A

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