The MSM7557 is a single chip MSK modem with base band voice processor for cordless telephone.The MSM7557 voice transmit block consists of high pass filter, compressor, pre-emphasis, limiterand splatter filter.
Voice receive block consists of Band pass filter, De-emphasis and Expander.
FEATURES
•Available to transmit modem signal and also transmit base band voice signal through wirelesstransmission path (0.3 kHz to 3.4 kHz)•Built-in compandor circuit
•Upper limit of voice band (3306 Hz/3400 Hz/3500 Hz) is selectable•Modem bit rate (2400/1200 bps) is selectable
•Transmit function and receive function operate separately• Emphasis mode selectable
•Built-in bit synchronous detector and frame synchronous detector•Built-in limiter level generator and external limit voltage input•Dynamic range selectable
•Built-in crystal oscillator circuit
•Wide range power supply voltage (2.7V ~ 5.5V)•Package :
56-pin plastic QFP(QFP56-P-910-0.65-2K)(Product name : MSM7557GS-2K)
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IPNPM1233CCCCMCCCCCILTVIOTVI–Com-RC-+pressorHPF1Pre-EmphasisLimiterSplatterFilterLPFTAOSECSDDYNMODCONTTVEBRSTMEEMPVR1RCK1VR2RC-RCK2VR3LPFRDBYPFlameRTVDDDEMODDetFDGNDFPSSGSGBITFDEMix LPFMixerDEM-CSHX1BPFShaperX2OSCRAIO–RAIDe-RC-+RBPFEmphasisHPF2ExpanderLPFRVOVoltage12EENPPDNPDN33RVEREFCCEECCBLOCK DIAGRAM¡ SemiconductorMSM75572/25¡ SemiconductorMSM7557
PIN CONFIGURATION (TOP VIEW)
50PDN49VDD48RVE55TVE44FPS54ME46RD51NCNCSTEMPLIMNCVR1VR2VR3NCTVIOCMPITVICC1CC2
1234567891011121314151617181920212223242526272843NC424140393837363534333231302956SD47RT53X252X145FDNCBITFDEBRBYPRCK2RCK1SECCSHRAINCRAIOCE3PNC
(VDD)GNDDYNCC3NCC3PRVONCTAOCE3NNCCE1Notes: The pin 49 should be used for VDD.
The pin 21 should be connected to VDD or opened. NC : No connect pin
CE2NCSG3/25
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PIN DESCRIPTION
NameTransmit data input.The data on SD pin are took into MSK modulator and the data are available on the positive edge of ST.DescriptionMESD inputtMSSDSTModulatorinput dataIn order to synchronize a receive modem, more than 18bits bit-synchronous signal should be transmitted before data transmission. If S/N ratio of the receive signal is always good, more than 11bits bit-synchronous signal synchronizes the receiver. STTransmit data timing clock output.When digital \"0\" is put on ME pin, ST is fixed to digital \"1\" level.Emphasis path selection.EMPEMP01path Pre-emphasis circuit is connected to thepathTransmit sidePre-emphasis circuit is bypassed to thepathDe-emphasis circuit is connected to thepathReceive sideDe-emphasis circuit is bypassed to theDeviation limiter control.Voice signal maximum Rf modulation level is controlled by connecting external reference voltage to this pin.Input impedance of this pin is about 200 kW.When this pin is left open, internal reference voltage is used as the clamp level.LIMInternal clamp level is as follows.DYN01Internal clamp level0.50 V1.26 VLimiter level–9 dBV–1 dBVThis internal clamp level is made by internal reference voltage which is unrelated with VDD.Negative clamp level is made by internal operational amplifier and the voltage is reversed at VSG.4/25
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(Continued)
NameModulator output level control.Refer to the following figure.–+VR1R1R1 ≥ 40 kWR2 ≥ 40 kWR1 ≥ R2DescriptionFrom modulatorVR1VR2VR3To transmit filterVR2R2VR3VTAO = 20 ¥ log (R2/R1) – 9 dBV (DYN = \"0\" )VTAO = 20 ¥ log (R2/R1) – 1 dBV (DYN = \"1\" )This level is made from internal voltage reference, so this level doesn't depend on power supply voltage.–Transmit side RC active filter input (TVI) and output (TVIO).If over 50 kHz frequency element is in the input signal, folding noise is generated from internal SCF circuit, so second order RC-active filter is needed. (fc = 10 kHz)+CMPIC19C1R3R5C3TVIC2R4SG–+TVIOCompressorR5 ≥ 60 kWC1 and C19 are used for DC cut.TVIOTVIVTVIExample of fc = 10 kHz and 0 dB gainR3 = R4 = R5 = 68 kWC1 = 0.22 mF, C2 = 510 pF, C3 = 110 pFWhen digital \"1\" is applied to TVE pin, transmit voice signal comes out to TAO.CC1CC2CC3NCC3PCapacitor connection pins to remove for DC offset of the compressor.A 1 mF capacitor between SG pin and each pin should be connected.Capacitor connection pins for the compressor attack and recovery time.When DYN is digital \"0\" level, a 0.22 mF capacitor should be connected between CC3N and CC3P.And when DYN is digital \"1\" level, a 0.47 mF capacitor should be connected between them.5/25
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(Continued)
NameCMPICompressor circuit input.A 0.47 mF capacitor should be connected between CMPI and TVIO.Dynamic range control input.For an application of which VDD is always higher than 4.5 V (Base station), by setting DYN = \"1\modem transmit carrier level, typical input signal level, limiter clamp level and compandor DYNstandard input level are up about 8dB to improve S/N ratio.For an application of which VDD is lower than 4.5 V (Hand-set) DYN shall be digital \"0\".To make easier interface with the RF part, one solution is to put digital \"0\" on DYN pin for both Base station and Handset.Built-in analog signal ground. The DC voltage is half of VDD.SGGNDTo make this voltage source impedance lower and to ensure the device performance, it is necessary toput a bypass capacitor of more than 1mF between SG and VDD in close physical proximity to the device.Ground pin, (0V).Transmit analog signal output.According to control data on ME and TVE, TAO is set as follows.METAO001TVE01XVoice signal outputMSK modulator outputX : Don't careReceive voice signal output.RVO pin state is defined by RVE control.RVORVE01CE1CE2CE3NCE3PRAIORAICSHOutput enableRVOOutput disable (potential = SG)TAONo signal output (potential = SG)DescriptionCapacitor connection pins to remove DC offset of the expander.A 1 mF capacitor between SG pin and each pin should be connected.Capacitor connection pins for the expander attack time and recovery time.When DYN is digital \"0\" level, a 0.22 mF capacitor should be connected between CE3N and CE3P.And when DYN is digital \"1\" level, a 0.47 mF capacitor should be connected between them.Receive side amplifier input (RAI) and output (RAIO).Second order RC-active filter is needed like TVIO and TVI.Refer to TVIO and TVI pin description.Capacitor connection pin to remove DC offset of the modem shaper circuit.A 1 mF capacitor should be connected between GND pin and CSH.6/25
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(Continued)
NameSEC
Device test input.
SEC shall be connected to GND.Voice band select.
RCK1RCK2
RCK10X1
Compandor path selection.
BYP
BYP01
Transmit side
Compressor is connected to the path.Compressor is bypassed to the path.
Receive side
Expander is connected to the path.Expander is bypassed to the path.
RCK2101
Upper Limit of Voice Band
3306 Hz3400 Hz3500 Hz
Function
Modem data signaling rate select pin.
BR
BR01
Date signaling rate
1200 bps2400 bps
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(Continued)
NameFrame synchronous signal detector control.When digital \"0\" is applied to this pin, FD pin is fixed to \"0\" level. RT and RD always work.FDEWhen digital \"1\" is applied to this pin, frame synchronous detector works, and RT and RD pins are fixed to \"1\" level untill synchronous signal detector detects frame synchronous signal and FD becomes \"1\" level.Refer to Fig.3 (receive signal timing).Bit synchronous signal detector control.When BIT and FDE pins are digital \"1\" level and when bit synchronous signal and frame synchronous BITsignal are detected continously, FD becomes digital \"1\".When BIT pin is digital \"0\" level and FDE pin is digital \"1\" level and when 16-bit frame synchronous signal is detected, FD pin becomes digital \"1\" level.Refer to FPS pin detection.Frame synchronous pattern control.BITFPS0011FPS0101Detect pattern1001 0011 0011 0110(=9336H)1100 0100 1101 0110(=C4D6H)1010 1001 0011 0011 0110(=A9336H)1010 1100 0100 1101 0110(=AC4D6H)Receiver Handset sideBase stationHandset sideBase stationFunction(Note : This pattern is for Japanese Cordless Telephone.)Frame synchronous detector output.FDWhen receive data correspond to detection pattern, FD pin is held to digital \"1\" level.When FDE is applied to digital \"0\" level, FD pin is reset to digital \"0\" level.And at the full power down state (PDN = \"1\Demodulator serial data output.RDThe data are synchronized with the re-generated timing clock of RT.When FDE is digital \"1\" level and also FD is digital \"0\" level, RD is fixed to digital \"1\" level.Receive data timing clock output.This signal is re-generated by internal digital PLL. The falling edge of this clock output is coincident RTwith the transitions of RD.The rising edge of RT can be used to latch the valid receive data.When FDE pin is applied to digital \"1\" level and also FD pin output digital \"0\" level, RT pin is fixed to digital \"1\" level. Refer to Fig.3.RVEReceive voice signal control.Refer to RVO pin description.Power supply.VDDThis device is sensitive to power supply noises as switched capacitor tequniques are utilized.A bypass capacitor of more than 10 mF between VDD and GND pin should be connected to ensure the performance.8/25
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(Continued)
NamePower down control.Power down state is controlled by PDN, ME, RVE, and TVE.Voice control pathOFFOFFOFFONTransmit sidemodemOFFOFFONONReceive sidemodemOFFONONONX : Don't careFunctionPDNMode1PDNMode2Mode3Mode4110MEXX1RVE010TVEXX0othersAt the mode 4, all functions are powered on.At the full power down mode(PDN = \"1\" and RVE = \"0\"), the demodulator circuit and FD pin are reset.When VDD is turned ON, the demodulator circuit and FD pin should be reset by setting Mode1.Crystal connection. X1X23.6864 MHz crystal shall be connected.When an external master clock is applied, the clock should be supplied to X2 pin via a 200 pF capacitor for AC coupling and X1 should be opened.MSK moudulator output.MEWhen digital \"1\" is applied to this pin, MSK modulator is connected to the splatter filter.Refer to TAO pin description.Transmit side voice signal contorol. Refer to TAO pin description.TVE9/25
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ABSOLUTE MAXIMUM RATINGS
ParameterPower Supply VoltageAnalog Input Voltage *1Digital Input Voltage *2Storage TemperatureSymbol RatingConditionVDDVIAVIDTSTGTa = 25°CRefer to GND—–0.3 to +7.0–0.3 to VDD + 0.3–55 to +150 V°CUnit*1 : LIM, VR2, TVI, RAI, CMPI*2 : SD, EMP, DYN, SEC, RCK1, RCK2, BYP, BR, FDE, BIT, FPS, RVE, PDN, X2, ME, TVERECOMMENDED OPERATING CONDITIONS
ParameterPower Supply VoltageOperating TemperatureCrystal Oscillating Freq.Data Signaling RateC4, C5, C11, C12, C15C6, C13C7, C8C9, C10C14C19C20, C21SymbolVDDTopfX'TALTS————————ConditionfromDYN = \"0\"GND level DYN= \"1\"VDD = 2.7 V to 5.5 V—BR = 0\"BR = \"1\"—DYN = \"0\"DYN = \"1\"—RL ≥ 40kW———Min.2.74.5–303.6860——————————Typ.3.65.0+253.6864120024001.00.220.471.00.22100.4720Max.5.55.5+703.6868——————————pFmFUnitV°CMHzbit/sec10/25
¡ SemiconductorMSM7557
ELECTRICAL CHARACTERISTICS
DC Characteristics
DYN = \"0\" : VDD = 2.7 V to 5.5 V, Ta = –30°C to 70°CDYN = \"1\" : VDD = 4.5 V to 5.5 V, Ta = –30°C to 70°CSymbolIDDIDDS1Power Supply Current *1IDDS2IDDS3Input Leakage Current *2Input Voltege *2Output Voltege *3IILIIHIILIIHVOLVOHConditionNormal3.6 Vmode5.5 V(mode 4)Power downmode 1Power downmode 2Power downmode 3VIN = 0 VVIN = VDD—IOL = –20 mAIOH= 20 mA5.5 VMin.————3.6 V—–1000.7VDD00.8VDD4.6—————9.0+100.2VDDVDD0.1VDDVDDmATyp.9.014.01.03.8Max.1824207.0mAUnitmAmAParameterV*1 Refer to PDN pin description*2 SD, EMP, DYN, SEC, RCK1, RCK2, BYP, BR, FDE, BIT, FPS, RVE, PDN, ME, TVE*3 ST, FD, RD, RT11/25
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AC Characteristics
ParameterTransmitCarrier FrequencyTransmit Carrier Level Receive Carrier Input Level1200Bit Error Ratebps2400bpsBERDefined at RAIOSymbolfM1fS1fM2fS2VOXVIRConditionSD = \"1\"SD= \"0\"SD = \"1\"SD= \"0\"R1 = R2BR = \"0\"ME= \"1\"BR = \"1\"ME= \"1\"DYN = \"0\" : VDD = 2.7 V to 5.5 V, Ta = –30°C to 70°CDYN = \"1\" : VDD = 4.5 V to 5.5 V, Ta = –30°C to 70°CMin.1199179911992399–11–3–328 dB10 dB11 dB13 dBNumber of data bits required for the PLL to be locked in within the phase difference of 22.5° or less Number of data bits required for the PLL to be locked in within the phase difference of 90° or less ————Typ.1200180012002400–9–1—1 ¥ 10-35 ¥ 10-51 ¥ 10-35 ¥ 10-5Max.1201180112012401–7+1–2—————dBVHzUnitDYN = \"0\"DYN = \"1\"——18bitNumber of PLL Lock-inData Bits *1VIR——11*1 Receive MSK signal is bit synchronous signal (modulated signal of alternating \"0\12/25
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Voice Signal Interfaces
ParameterRVO Maximum OutputSignal LevelLimiter Clamp LevelTransmit Output DistortionReceive Output DistortionTransmit GainReceive GainTransmit Idle NoiseReceive Idle Noise
RCV.ÆTran.
Cross Talk
Tran.ÆRCV.
SymbolVOUTVLIMHDTHDRGTGRHITHIRCTTCTRFT1
Transmit FilterResponse
FT3FT25FT34FT60FR1
Receive FilterResponse
FR3FR25FR34FR60
Condition
fIN = 1 kHzBYP = \"0\" *1fIN = 1 kHzLIM = open
DYN = \"0\" : VDD = 2.7 V to 5.5 V, Ta = –30°C to 70°CDYN = \"1\" : VDD = 4.5 V to 5.5 V, Ta = –30°C to 70°C
Min.——–10–2——–1.5–1.5——
*2100 Hz300 Hz2.5 kHz3.4 kHz6 kHz100 Hz300 Hz2.5 kHz3.4 kHz6 kHz
———–12.5+6.5+8.5—+1.5+8.0–9.5–12.5—
Typ.——–9–1–40–40–0.2–0.2–51–85–75–80–28–10.5+8.0+10.5–40+3.0+9.5–8.0–10.5–40
Max.–6+2–80——+1+1——–60–60–23–8.5+9.5+12.5–30+4.5+11.0–6.5–8.5–30
dBdBVdBdBVUnit
DYN = \"0\"DYN = \"1\"DYN = \"0\"DYN = \"1\"
fIN = 1 kHz, –12 dBVBYP = \"0\fIN = 1 kHz, BYP = EMP = \"1\"fIN = 1 kHz, BYP = EMP = \"1\"BYP = \"0\"EMP = \"1\"RAIO = –2 dBVTVIO = –2 dBVEMP = \"1\"BYP = \"1\"RCK2 = \"0\"Ref. = 1 kHzEMP = \"1\"BYP = \"1\"RCK2 = \"0\"Ref. = 1 kHz
*1 S/D ≥ 20 dB
*2 fIN = 1 kHz, BYP = EMP = \"1\"
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(Continued)
DYN = \"0\" : VDD = 2.7 V to 5.5 V, Ta = –30°C to 70°CDYN = \"1\" : VDD = 4.5 V to 5.5 V, Ta = –30°C to 70°CParameterStandard Input LevelMaximum Input LevelOutput Level *3Attack TimeRecovery TimeStandard InputLevelMaximumSymbolVICSfIN = 1 kHzVICMGC2GC4GC5TAT1TAT2TRE1TRE2VIESfIN = 1 kHzVIEMGE1GE2GE3TAT3TAT4TRE3TRE4fIN = 1 kHz *3fIN = 1 kHzConditionDYN = \"0\"DYN = \"1\"DYN = \"0\"DYN = \"1\"–20 dB–40 dB–60 dBDYN = \"0\mFDYN = \"1\mFDYN = \"0\mFDYN = \"1\mF*4*5*6DYN = \"0\"DYN = \"1\"–10 dB–20 dB–30 dBDYN = \"0\mFDYN = \"1\mFDYN = \"0\mFDYN = \"1\mFMin.–16.1–7.1——–10.6–21.0—————–12.9–13.3–4.7——–21.5–42.2—————Typ.–13.7–5.5——–9.9–19.8–29.53.43.51716–10.8–11.2–3.1——–20–40–593.43.51716Max.–11.3–3.9–7+1.0–9.2–18.6—————–8.7–9.1–1.5–6+2–18.3–37.5—————msdBdBVmsdBdBVUnitCompressorExpanderOutput LevelOutputLevelAttackTimeRecoveryTime*3 0 dB is defined as the input level and the output level when the standard input level is input.*4 VDD = 3.6 V, DYN = \"0\"*5 VDD = 5.0 V, DYN = \"0\"*6 VDD = 5.0 V, DYN = \"1\"14/25
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Common Characteristics
arameter Symbol Input ResistanceRIARICROX1Output ResistanceROX2ROX3Output Load ResistanceRXL1RXL2VSGOutput DC VoltageVAOTAO, RVOConditionTVI, RAI, VR2LIMTAODYN = \"0\" : VDD = 2.7 V to 5.5 V, Ta = –30°C to 70°CDYN = \"1\" : VDD = 4.5 V to 5.5 V, Ta = –30°C to 70°CMin.—————*1TVIO4060VDD– 0.1 2 VDD– 0.15 2 Typ.102001750600100——VDD 2 VDD 2 Max.———————VDD+ 0.1 2 VDD+ 0.15 2 kWWUnitMWkWVR1, VR3, RVOTVIO, RAIOS/D ≥ 20 dBSGV*1 VR1, VR3, TAO, RVO, RAIODigital Timing Characteristics
ParameterTransmit DataSet-up TimeTransmit DataPHold TimeDYN = \"0\" : VDD = 2.7 V to 5.5 V, Ta = –30°C to 70°CDYN = \"1\" : VDD = 4.5 V to 5.5 V, Ta = –30°C to 70°CConditionMin.1Refer to Fig. 11Refer to Fig. 1Refer to Fig. 1–3000Typ.————Max.—ms—300834nsmsUnitSymboltStHtDtMSReceive DataOutput DelaySync-signalOutput Delay (MEÆST)15/25
¡ SemiconductorMSM7557
TIMING DIAGRAM
ST
50%SD50%tStHFigure 1 Input Data Timing
RT
50%FD,RD50%tDFigure 2 Output Data Timing
FDERTInternal RDN-2N-1ND1D2D3FDRDD1D2D3N-2, N-1, N : Frame shnchronous signalFigure 3 Receive Signal Timing
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OPERATION DESCRIPTION
Limiter Circuit
AR12 R11 LIM+ –R11 : 1 kWR12 : 200 kWReverseHPF1 or PRE – EMPHASISLimiterSplatter filterDYN = \"0\"DYN = \"1\": Clamp level = VSG ±0.50 V: Clamp level = VSG ±1.26 V
2.In case of using external voltage reference
LIM pin shall be supplied over VSG voltage.Notes
1 )R11 is protection resister from external extra voltage.
2 )Resistor value of R11 and R12 changes 0.7 to 1.3 times from the typical valueby lot variation and temperature variation.
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¡ SemiconductorMSM7557
Frame Detector
Frame detection pattern is defined by BIT and FPS.
BIT0011FPS0101Sync-pattern9336HC4D6HA9336HAC4D6HReceiverS.H.M.T.S.H.M.T.NoteFrame synchronousFrame synchronousBit + Frame synchronousBit + Frame synchronousM.T. = Master telephoneS.H. = Slave handset Fig 3 shows detection timing
First, put digital \"0\" level to FDE pin more than 1 ms, then FD pin is reset to \"0\" level.
Next, put digital \"1\" level to FDE pin, then RT and RD output digital \"1\" level until frame synchronoussignal detected.
When synchronous pattern is detected, FD pin is held to digital \"1\" level.
At the full power down state (PDN = \"1\
In order to detect frame synchronous signal certainly, receive side PLL should be locked insufficiently.
When a modem starts data transmittion, the bit-synchronous signal of more than 18 bits should betransmitted before frame pattern of the upper table.
Frame detection signalInternal RTDCKQQFDFDEDCKQQRTInternal RDFull power down signal(Internal signal)RD18/25
¡ SemiconductorMSM7557
Application Circuit
MSM7557GS-2KTransmit dataTransmit data timing clockEmphasis path selectLimiter circuit clamp voltage inputSDSTEMPLIMVR1R1R2R5C1R3C2C3TVIR4CC1C4CC2C5CC3NC6CC3PDynamic rangeselectDYNSGC8C7GNDVDDTransmit signal outputC10Receive voice outputRVOCE1C11CE2C12CE3NC13CE3PRAIC16RAIOC17CSH+C15–R6R7R8C18Receivesignal inputRCK2SECC9TAORCK1Voice band selectBYPCompandor path selectFDEBRFrame synchronous detectorcontrolModem data signaling rate selectBITBit synchronusdetector controlFPSFDFrame synchronousdetector outputSynchronous pattern selectRDReceive data C19TVEMEX2X1C21PDNVDDC20Transmit voice output controlMSK modulator control3.6864 MHzPower down controlPower supplyC14Receive voice output controlReceive timing clockVR2VR3CMPITVIORVERT+–Transmit voice input
Note : An arrow mark of ( ) indicates connection to the SG pin.19/25
¡ SemiconductorMSM7557
MSM7557 Filter Characteristics
MSM7557 has wide band filters (0.3 kHz to 3.4 kHz) as follows.
Pre-Emphasis........................................................................................................Fig. 4Splatter Filter........................................................................................................Fig. 5RBPF.......................................................................................................................Fig. 6De-Emphasis.........................................................................................................Fig. 7Transmit Total (HPF1 + Pre-Emphasis + Splatter).........................................Fig. 8Receive Total (RBPF + De-Emphasis)...............................................................Fig. 9Transmit and Receive Total................................................................................Fig. 10Fig. 4 to Fig. 10 show the filter characteristics when RCK2 is digital \"0\". When RCK1 is digital \"0\" andRCK2 is digital \"1\becomes narrow) When RCK1 is digital \"1\" and RCK2 is digital \"1\1.029 times on the frequency axis. (pass-band becomes wide)
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¡ Semiconductor100100 1k 10k FREQ [Hz] –10]–20Bd[ LEVEL–30Figure 4 MSM7557 Pre–Emphasis100 1k 10k 0–10FFREQ [Hz] cut(–0.2 dB) = 3.4 kHz–20–30–40–50]–60Bd[ L–70EVEL–80Figure 5 MSM7557 Splatter Filter MSM7557
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¡ Semiconductor0100 1k 10k FREQ [Hz] –10Fcut(–0.2 dB) = 3.4 kHz–20–30–40–50–60]Bd[ –70LEVEL–80Figure 6 MSM7557 RBPF20100100 1k 10k FREQ [Hz] –10]Bd[ LEVEL–20Figure 7 MSM7557 De–EmphasisMSM7557
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¡ Semiconductor100100 1k 10k FREQ [Hz] –10–20–30–40–50]Bd[ –60LEVEL–70Figure 8 MSM7557 Transmit Total (HPF1 + Pre–Emphasis+Splatter)100100 1k 10k –10FREQ [Hz] –20–30–40–50]Bd[ –60LEVEL–70Figure 9 MSM7557 Receive Total (RBPF + De–Emphasis)MSM7557
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¡ Semiconductor0100 1k 10k FREQ [Hz] –10–20–30–40–50–60]Bd[ –70LEVEL–80Figure 10 MSM7557 Transmit and Receive TotalMSM7557
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PACKAGE DIMENSIONS
(Unit : mm)
QFP56-P-910-0.65-2KMirror finishPackage materialLead frame materialPin treatmentSolder plate thicknessPackage weight (g)Epoxy resin42 alloySolder plating5 mm or more0.43 TYP.Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, whichare very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for theproduct name, package name, pin number, package code and desired mounting conditions(reflow method, temperature and times).
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