74HC08
Quad 2−Input AND Gate
High−Performance Silicon−Gate CMOS
The 74HC08 is identical in pinout to the LS08. The device inputs arecompatible with Standard CMOS outputs; with pullup resistors, theyare compatible with LSTTL outputs.
Features
http://onsemi.com
MARKINGDIAGRAMS
14141SOIC−14D SUFFIXCASE 751A
1HC08GAWLYWW•••••••••
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTLOperating Voltage Range: 2.0 to 6.0 VLow Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A RequirementsESD Performance: HBM > 2000 V; Machine Model > 200 VChip Complexity: 24 FETs or 6 Equivalent GatesThese are Pb−Free Devices
LOGIC DIAGRAM
A1B1A2B2A3B3A4B4
12459101213
PIN 14 = VCCPIN 7 = GND
3Y1
14
141TSSOP−14DT SUFFIXCASE 948G
1
HC08ALYWG G
6
Y2Y = AB
8
Y3
HC08= Device CodeA= Assembly LocationWL or L= Wafer LotY= Year
WW or W= Work WeekG or G= Pb−Free Package(Note: Microdot may be in either location)
11
Y4
FUNCTION TABLE
InputsALLHH
BLHLH
OutputYLLLH
Pinout: 14−Lead Packages (Top View)
VCC14B413A412Y411B310A39Y38ORDERING INFORMATION
1A1
2B1
3Y1
4A2
5B2
6Y2
7GND
See detailed ordering and shipping information in the packagedimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 1
1Publication Order Number:
74HC08/D
元器件交易网www.cecb2b.com
74HC08
MAXIMUM RATINGS
SymbolVCCVinVoutIinIoutICCPDTstgTL
Parameter
DC Supply Voltage (Referenced to GND)DC Input Voltage (Referenced to GND)DC Output Voltage (Referenced to GND)DC Input Current, per PinDC Output Current, per Pin
DC Supply Current, VCC and GND PinsPower Dissipation in Still Air,Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
SOIC Package†TSSOP Package†
Value– 0.5 to + 7.0– 0.5 to VCC + 0.5– 0.5 to VCC + 0.5
±20±25±50500450– 65 to + 150
260
UnitVVVmAmAmAmW_C_C
This device contains protectioncircuitry to guard against damagedue to high static voltages or electricfields. However, precautions mustbe taken to avoid applications of anyvoltage higher than maximum ratedvoltages to this high−impedance cir-cuit. For proper operation, Vin andVout should be constrained to therange GND v (Vin or Vout) v VCC.Unused inputs must always betied to an appropriate logic voltagelevel (e.g., either GND or VCC).Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stressratings only. Functional operation above the Recommended Operating Conditions is not implied.Extended exposure to stresses above the Recommended Operating Conditions may affect devicereliability.
†Derating—SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
SymbolVCCVin, Vout
TAtr, tf
Parameter
DC Supply Voltage (Referenced to GND)DC Input Voltage, Output Voltage (Referenced toGND)
Operating Temperature Range, All Package TypesInput Rise/Fall Time(Figure 1)
VCC = 2.0 VVCC = 4.5 VVCC = 6.0 V
Min2.00– 55000
Max6.0VCC+ 1251000500400
UnitVV_Cns
ORDERING INFORMATION
Device
74HC08DR2G74HC08DTR2G
PackageSOIC−14(Pb−Free)TSSOP−14*
Shipping†2500/Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.*This package is inherently Pb−Free.
http://onsemi.com
2
元器件交易网www.cecb2b.com
74HC08
DC CHARACTERISTICS (Voltages Referenced to GND)
SymbolVIH
Parameter
Minimum High−Level Input Voltage
Condition
Vout = 0.1V or VCC −0.1V|Iout| ≤ 20mA
VCC(V)2.03.04.56.02.03.04.56.02.04.56.0
|Iout| ≤ 2.4mA|Iout| ≤ 4.0mA|Iout| ≤ 5.2mA
3.04.56.02.04.56.0
|Iout| ≤ 2.4mA|Iout| ≤ 4.0mA|Iout| ≤ 5.2mA
3.04.56.06.06.0
Guaranteed Limit
−55 to 25°C
1.502.103.154.200.500.901.351.801.94.45.92.483.985.480.10.10.10.260.260.26±0.12.0
≤85°C1.502.103.154.200.500.901.351.801.94.45.92.343.845.340.10.10.10.330.330.33±1.020
≤125°C1.502.103.154.200.500.901.351.801.94.45.92.203.705.200.10.10.10.400.400.40±1.040
mAmAVUnitV
VIL
Maximum Low−Level Input Voltage
Vout = 0.1V or VCC − 0.1V|Iout| ≤ 20mA
V
VOH
Minimum High−Level Output Voltage
Vin = VIH or VIL|Iout| ≤ 20mAVin =VIH or VIL
V
VOL
Maximum Low−Level Output Voltage
Vin = VIH or VIL|Iout| ≤ 20mAVin = VIH or VIL
IinICC
Maximum Input Leakage CurrentMaximum Quiescent SupplyCurrent (per Package)
Vin = VCC or GNDVin = VCC or GNDIout = 0mA
NOTE:Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)
SymboltPLH,tPHL
Parameter
Maximum Propagation Delay, Input A or B to Output Y(Figures 1 and 2)
VCC(V)2.03.04.56.02.03.04.56.0
Guaranteed Limit
−55 to 25°C
753015137527151310
≤85°C954019169532191610
≤125°C11055221911036221910
Unitns
tTLH,tTHL
Maximum Output Transition Time, Any Output(Figures 1 and 2)
ns
Cin
Maximum Input CapacitancepF
NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD
Power Dissipation Capacitance (Per Buffer)*
20
pF
*Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of theON Semiconductor High−Speed CMOS Data Book (DL129/D).
http://onsemi.com
3
元器件交易网www.cecb2b.com
74HC08
trINPUTA OR B
tPLH90%OUTPUT Y
tTLH50%10%tTHL90%50%10%tPHLtfVCC
GND
Figure 1. Switching Waveforms
TESTPOINTOUTPUTDEVICEUNDERTESTCL*
*Includes all probe and jig capacitance
Figure 2. Test Circuit
AB
Y
Figure 3. Expanded Logic Diagram
(1/4 of the Device)
http://onsemi.com
4
元器件交易网www.cecb2b.com
74HC08
PACKAGE DIMENSIONS
SOIC−14CASE 751A−03
ISSUE H
−A−148−B−P7 PL0.25 (0.010)MBM17NOTES:
1.DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.
2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION.
4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.
5.DIMENSION D DOES NOT INCLUDEDAMBAR PROTRUSION. ALLOWABLEDAMBAR PROTRUSION SHALL BE 0.127(0.005) TOTAL IN EXCESS OF THE DDIMENSION AT MAXIMUM MATERIALCONDITION.
GC−T−SEATINGPLANERX 45_FD14 PL0.25 (0.010)KMMSJTBASDIMABCDFGJKMPRMILLIMETERSMINMAX8.558.753.804.001.351.750.350.490.401.251.27 BSC0.190.250.100.250 7 __5.806.200.250.50INCHESMINMAX0.3370.3440.1500.1570.0540.0680.0140.0190.0160.0490.050 BSC0.0080.0090.0040.0090 7 __0.2280.2440.0100.019SOLDERING FOOTPRINT*7X7.0410.5814X14X1.521.27PITCHDIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
5
元器件交易网www.cecb2b.com
74HC08
PACKAGE DIMENSIONS
TSSOP−14CASE 948G−01
ISSUE B
14X REFK
0.10 (0.004)0.15 (0.006)TUSMTUSVNS2XL/21480.25 (0.010)MLPIN 1IDENT.17B−U−NFDETAIL EKK10.15 (0.006)TUSA−V−JJ1NOTES:
1.DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.
2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION A DOES NOT INCLUDE MOLDFLASH, PROTRUSIONS OR GATE BURRS.MOLD FLASH OR GATE BURRS SHALL NOTEXCEED 0.15 (0.006) PER SIDE.
4.DIMENSION B DOES NOT INCLUDEINTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALLNOT EXCEED 0.25 (0.010) PER SIDE.5.DIMENSION K DOES NOT INCLUDEDAMBAR PROTRUSION. ALLOWABLEDAMBAR PROTRUSION SHALL BE 0.08(0.003) TOTAL IN EXCESS OF THE KDIMENSION AT MAXIMUM MATERIALCONDITION.
6.TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.
7.DIMENSION A AND B ARE TO BEDETERMINED AT DATUM PLANE −W−.
DIMABCDFGHJJ1KK1LMMILLIMETERSMINMAX4.905.104.304.50−−−1.200.050.150.500.750.65 BSC0.500.600.090.200.090.160.190.300.190.256.40 BSC0 8 __INCHES
MINMAX0.1930.2000.1690.177−−−0.0470.0020.0060.0200.0300.026 BSC0.0200.0240.0040.0080.0040.0060.0070.0120.0070.0100.252 BSC0 8 __SECTION N−N−W−C0.10 (0.004)−T−SEATINGPLANEDGHDETAIL ESOLDERING FOOTPRINT*
7.0610.65PITCH
0.36
14X
14X1.26DIMENSIONS: MILLIMETERS*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
6
元器件交易网www.cecb2b.com
74HC08
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. ShouldBuyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone: 303−675−2175 or 800−344−3860 Toll Free USA/CanadaFax: 303−675−2176 or 800−344−3867 Toll Free USA/CanadaEmail: orderlit@onsemi.comN. American Technical Support: 800−282−9855 Toll FreeUSA/CanadaEurope, Middle East and Africa Technical Support:Phone: 421 33 790 2910Japan Customer Focus CenterPhone: 81−3−5773−3850ON Semiconductor Website: www.onsemi.comOrder Literature: http://www.onsemi.com/orderlitFor additional information, please contact your localSales Representativehttp://onsemi.com774HC08/D
因篇幅问题不能全部显示，请点此查看更多更全内容